Index

Note: Page numbers followed by “f” and “t” indicate figures and tables respectively.

A
Access Permission field (AP field), 299, 299t
Accidental switching to ARM® state, 282
Advanced High-performance Bus Lite (AHB™ Lite), 13, 166
Advanced Microcontroller Bus Architecture (AMBA®), 23, 32
Advanced Peripheral Bus protocol (APB protocol), 166
Aligned transfers, 180, 180f
ALU status flags, 96, 96t
Application Interrupt and Reset Control Register (AIRCR), 93–94, 224, 224t
register, 227–228
Application Program Status Register (APSR), 93, 117, 661
behaviors, 96–97
Application Programming Interface (API), 42, 80, 141, 244
Application Specific Standard Products (ASSPs), 2, 47
Application-Specific Integrated Circuits (ASICs), 1–2, 47
Architecture Reference Manual (ARM), 23–24
accidental switching to ARM® state, 282
Connected Community Web page, 25, 27f
ecosystem, 24, 25f
processor families, 5–8, 6f
resources on, 28
Arithmetic operations, 127–131
ARM Architecture Procedure Call Standard (AAPCS), 608–610
ARM® Cortex®-M processors, 315
porting software from 8-bit/16-bit microcontrollers to
memory requirements, 637–638
migration from 8051 to ARM Cortex-M0/Cortex-M0+, 639–641
ARM® Cortex®-M programming, 64–74
accessing peripherals in C, 65–69
C programming, 64–65
data in SRAM, 71–73
inside program image, 69–71
microcontroller starts, 73–74
ARM® Keil® Microcontroller Development Kit, 329
ARM7TDMI™ processor, 5, 642
differences with Cortex®-M0/M0+ processor
classic ARM® processors, 641, 642t
instruction set, 644
interrupts, 644
operation mode, 642–643
register bank differences, 643f
ARM926EJ-S processors, 8
ARMv6-M architecture, 87–89
debug system, 105–106
evolution, 88f
exceptions, 102–103
interrupts, 102–103
memory system, 97–100
NVIC, 104–105
program image and start-up sequence, 106–108
programmer’s model
APSR behaviors, 96–97
operation modes and states, 89–90, 89f
registers and special registers, 90–96
SCB, 105
stack memory operations, 100–102
ARMv6-M Architecture Reference Manual (ARMv6-M ARM), 38
Assembly code, 647
assembler directives, 116, 116t
assembly function, 612–613
assembly syntax, 113–117
calling assembly functions from C codes, 618–619
calling C functions from assembly, 617–618
Assembly language, programming techniques for
allocating data space for variables, 628–630
complex branch handling, 630–631
Assembly programming, 608–610
Assembly projects in Keil® MDK-ARM
hello world, 620–621
small project, 619–620
text output functions, 621–624
Assembly wrapper
assembly language wrapper code, 283–284
using embedded assembler in Keil® MDK, 284–285
for HardFault handler, 284f
Atomic access, 647
B
B field, See Bufferable field
BASE register, 127–131
“BE8” big endian mode, See Byte-Invariant big endian mode
Big Endian support, 174–175
Bit and bit field computations, 162–164
Bit data handling in C, 661–663
Bit field clear operation, 164f
Bit field extract operation, 163f
BKPT instruction, See Breakpoint instruction
Blinky Project creation, 187f, 412–420, 416f, 431–433
Boot codes, See Startup
Boot loader, 34, 170–173, 228, 229f
Boot ROM, See Boot loader
Branch instructions, 149t–150t
Branch shadow, 15–16, 16f
Branch table, 151–153
Breadboard Project, 185
Breakpoint instruction (BKPT instruction), 30, 143, 165–166
Breakpoint Unit (BPU), 105, 113–119
Brown Out Detector (BOD), 186, 522
Bufferable attribute, 177
Bufferable field (B field), 299–300
Byte-Invariant big endian mode, 174
C
C codes, calling assembly functions from, 618–619
C compilers, 77
in Keil MDK, 330
optimization levels, 397t
C field, See Cacheable field
C programming, 64–65
accessing peripherals in, 65–69
bit data handling in, 661–663
startup code in, 663–668
C Startup Code, 70
C/C++ with assembly
accessing special instructions
CMSIS-CORE functions, 631
idiom recognitions, 632–633
assembly
code for interrupt control, 624–627
function, 610–613
programming and AAPCS, 608–610
in project developments, 607–608
Embedded Assembler feature, 616–617
inline assembly, 613–616
Cacheable attribute, 177
Cacheable field (C field), 299–300
Central Processing Units (CPUs), 2
Circular buffer mode, 325
CMP, See Compare
CMSIS-RTOS functions, 560–562
See also Real-Time Operating System (RTOS)
for OS kernel management, 572t
for thread management, 573t
Command line options, 433–434
Compare (CMP), 118
Compare and branch if not zero (CBNZ), 653
Compare and branch if zero (CBZ), 653
Compiler options, 396f
Complementary Metal Oxide Semiconductor (CMOS), 22
Configuration and Control Register (CCR), 94–95, 225–226, 226t
Context switching, 267f
in action, 267–277
without PendSV exception, 259f
with PendSV exception, 260f
in simple OS, 256f
CONTROL register, 90, 94–95, 254
CooCox, 330
CoIDE with GNU tools, 445–446
compile options, 451f
debug configurations, 453f
debug session screen, 456f
new project creation, 447–454
output configurations, 453f
project name and path, 449f
Core debug registers, 110–113
CoreMark®, 48
CoreSight Technical Introduction, 320
CoreSight™ Debug Architecture, 30, 319–320
CoreSight™ debug connector, 147
Cortex Microcontroller Software Interface Standard (CMSIS), 78, 79t, 502, 620, 685
APIs, 624
CMSIS-CORE, 78, 79f, 81–82, 84f, 84t
core registers access functions, 57–58
data type, 55–63
exception enumeration, 55–56
files, 391
Keil MDK project with, 333f
functions, 60, 631
header file, 294
nested vectored interrupt controller access functions, 56–57
standardization, 80–81
system
feature accesses, 58–59
and SysTick access functions, 57
using, 81–82
organization, 81
standardizing in, 80–81
versions, 508–510
Cortex-A processors, 6, 559–560
Cortex-M processors, 7, 226–227, 319–320, 502, 559–560, 648, 649
See also Operating system (OS)
debug and trace features, 655–656, 655t
family, 9t
instruction set, 10f
performance, 12t
system level and debug features, 12t
high-level architecture comparison, 648t
low-power features, 230
NVIC and exceptions, 650–652
programmer’s model, 649–650
sleep modes, 231
system level features, 653–654, 654t
Cortex-M1 processors, porting software between Cortex®-M0/M0+ processors, 656
Cortex-M3 processor, 9, 111–112, 657–659
porting software between Cortex®-M0/M0+ processors, 657–659
Cortex-M4/M7 processor, porting software between Cortex®-M0/M0+ processors, 659–660
Cortex-M7 processor, 7
Cortex-R processors, 7
Cortex®-M0/M0+ processors, 2, 29–31, 635
advantages, 40–45
applications, 45–47
ARMv6-M architecture, 37–38
block diagrams, 31–34
bus systems, 166–167
CMSIS functions support for, 632t
porting software
ARM7TDMI™, 645
Cortex-M1 processor, 656
Cortex-M3 processor, 657–659
Cortex-M4/M7 processor, 659–660
software portability, 38–39
Count leading zero (CLZ), 653
Cross Module Optimization operation, 398
D
Data
accesses, 153
alignment, 180–181
memory, 173–174
processing, 158
64-bit/128-bit add, 158
64-bit/128-bit sub, 159
bit and bit field computations, 162–164
bit field clear operation, 164f
bit field extract operation, 163f
integer divide, 159–161
unsigned integer divide function, 160f
unsigned integer square root, 161–162, 162f
space allocation for variables, 628–630
in SRAM, 71–73
conversion, 157
data size conversion, 157
endian conversion, 158
Data Memory Barrier instruction (DMB instruction), 227, 308
Data Synchronization Barrier instruction (DSB instruction), 227, 308, 512
Data Watchpoint and Trace unit (DWT unit), 655
Data Watchpoint unit, 105, 113–117
Debug Access Port, 319
Debug connector arrangements, 147
legacy 20-pin IDC connector arrangement, 147–148
10-pin Cortex® debug connector, 147, 151f
20-pin Cortex® debug + ETM connector, 147–153, 152f
Debug events, 321–324, 323f
Debug Exception and Monitor Control Register (DEMCR), 111–112
Debug features, 21
debug components in Cortex®-M0/Cortex-M0+ microcontrollers, 322f
halt mode, 321–324
instruction tracing support using MTB, 324–327, 326f
overview, 316t
Debug interface, 527
connection inside processors, 319f
CoreSight® debug architecture, 319–320
design considerations with, 320
JTAG, 317–319
Serial Wire Debug Communication Protocol, 317–319
Debug probe, See In-circuit debugger
Debug registers
breakpoint unit, 113–119
core, 110–113
in Cortex®-M0 and Cortex-M0+ processors, 109
data watchpoint unit, 113–117
ROM table registers, 117–118
Debug state, 90
Deep sleep modes, 30, 550–557
Development Studio 5 (DS-5), 70–71, 330, 459, 631
Device memory, 178
Device Under Test (DUT), 530
Direct Memory Access controller (DMA controller), 18–20, 36
DMB instruction, See Data Memory Barrier instruction
Double fault, 286
Dual-in-line (DIP), 185
Dynamic Voltage and Frequency Scaling (DVFS), 525
E
Embedded Application Binary Interface (EABI), 86, 609
Embedded Assembler, 615
See also Inline assembly
feature, 616–617
Embedded Microprocessor Benchmark Consortium (EEMBC), 48
Embedded OS, 244, 253, 559
CMSIS-RTOS, 560–562
hardware resources, 560
implementation, 255
Keil® RTX Kernel, 562–563
RTX configuration settings, 566f
RTX example with Keil MDK, 563–567
RTX_Config_CM.c customization, 604
thread priority, 604
trouble shooting, 601–603
Embedded processors, 1–2
CPU, core, microprocessor, 2–3
learning microcontroller programming, 4
programming on embedded systems, 3–4
Embedded software program flows, 58–63
combination of polling and interrupt driven, 60–61
handling concurrent processes, 61–63
interrupt driven, 60
polling, 58–59
Embedded Trace Macrocell (ETM), 655
Embedded-application binary interface (EABI), 428
ENDIANESS bit, 224
EnergyMonitor, 529
Error Correction Code (ECC), 7
Error handling
during software development, 283–286
in real applications, 283
Event communication interface, 517–519
Exception return instruction (EXC_RETURN instruction), 195–200
Exception(s), 102–103, 185–186
acceptance of exception request, 194
Cortex®-M0 and Cortex-M0+ processors, 187–189
entry sequence, 212–215
registers update, 214–215
stacking, 212–214
vector fetch and update PC, 214
enumeration, 55–56
exception-related instructions, 141–142
exit sequence, 215
fetch and execute from return address, 215
unstacking of registers, 215
handler, 186
priority levels, 190–192
sequence
acceptance of exception request, 194
exception return instruction, 195–196
late arrival, 196–197
stacking and unstacking, 194–195
tail chaining, 196
types, 29–31
Executable attribute, 177
Execution from SRAM, 229–230
eXecute Never field (XN field), 177, 299
Execution program status register (EPSR), 93, 281
Extend ordering operations, 135–137
F
Fast Interrupt (FIQ), 644
response, 20
Fault exception, 279
Fault handling
accidental switching to ARM® state, 282
causes of fault, 279–280
comparison
in ARMv7-M architecture, 289
in Cortex-M processors, 290
fault analysis, 280–282
faults triggering HardFault exceptions, 280t
lockup, 286–288
program address identification, 281f
Ferroelectric Random Access Memory (FRAM), 165–166
Finite State Machine (FSM), 506
First-In-First-Out (FIFO), 182
Flash programming, 436, 444f
Floating Point Context Active (FPCA), 650
FLOW register, 126–127
FreeRTOS-MPU, 310–311
Freescale Freedom FRDM-KL25Z board, 334–335, 334f, 463, 532
low-power features, 532
clocking arrangement, 533–535
low-power modes on KL25Z, 533
measurement results, 540–542
multipurpose clock generator operating states, 536f
programming UART on, 482–484
Frequency Locked Loop (FLL), 534
G
General Purpose Input/Output modules (GPIO modules), 35
Generic assembly code for interrupt control, 624
enable and disable interrupts, 624–625
set and clear interrupt pending status, 625–626
setting up interrupt priority level, 626–627
Generic wait function, 590
GNU Compiler Collection (gcc), 45, 427, 493, 612
ARM® embedded processors
using CooCox CoIDE with GNU tools for, 445–457
using Keil® MDK-ARM™ with GNU tools for, 438–445
command line options, 433–434
compilation switches, 435t
development flow, 428–431, 429f
examples in, 427–428
IDE and debugger, 454–457
inline assembly, 615–616
project with CMSIS-CORE, 430f
retargeting with, 493
tool chains, 611–612
H
Halt mode, 321–324
Handlers, 186
mode, 90
HardFault exceptions, 188, 280t
HardFault handler, 279–280
assembly wrapper for, 284f
to report stacked register values, 285
Hardware behavior effect to programming, 180–183
access to invalid addresses, 181
data alignment, 180–181
using multiple load and store instructions, 181–182
wait states, 182–183
Heap memory, 71
HFNMIENA bit, 296
High code density, 20
I
IAR Embedded Workbench for ARM (IAR EWARM), 409–410, 410f, 612
Blinky Project creation, 412–420, 416f
hints and tips, 422–426
MTB instruction trace with, 421
program compilation flow, 410–412
project options, 420–421
project with CMSIS-CORE, 411f
retargeting with, 492–493
semihosting with, 494–495
ID registers, See Identification registers
Identification registers (ID registers), 87
Idiom recognitions, 632–633
IF-THEN instruction (IT instruction), 653
“If-then-else” function, 147–148
In-circuit debugger, 75–76
In-Circuit Emulator (ICE), See In-circuit debugger
In-System Programming (ISP), 186, 551
Inline assembly
ARM® tool chains, 613–615
Inputs and outputs (I/Os), 57–58
functions development
interfaces, 500–501
reinventing wheel, 495–500
scanf function, 501
Instruction list, 119–144
arithmetic operations, 127–131
exception-related instructions, 141–142
extend and reverse ordering operations, 135–137
logic operations, 131–132
memory accesses, 122–126
memory barrier instructions, 139–141
moving data within processor, 120–121
program flow control, 137–139
shift and rotate operations, 132–134
sleep mode feature-related instructions, 142–143
stack memory accesses, 126–127
Instruction set, 1–4, 109–110
ARM® and Thumb®, 110–113
assembly basics, 113–119
assembly syntax, 113–117
suffix, 117–118
instruction list, 119–144
pseudo instructions, 144–145
Instruction Set Architecture (ISA), 29
Instruction Synchronization Barrier instruction (ISB instruction), 254, 308
Instruction usage, 147
data accesses, 153–157
data processing, 158–164
data type conversion, 157–158
program control, 147–153
Instrumentation Trace Macrocell (ITM), 655
Integer divide, 159–161
Integrated Development Environment (IDE), 56, 329, 387–390, 409
and debugger, 454–457
Intellectual Properties (IP), 22
Inter-Integrated Circuit interface (I2C interface), 500
Internal Private Peripheral Bus (internal PPB), 169
Internet of Things (IoT), 292, 460
Interrupt Clear Enable Register (ICER), 87–89
Interrupt Clear Pending Register (ICPR), 89–90, 202–204
Interrupt Control State Register (ICSR), 222–223, 222t
Interrupt program status register (IPSR), 93, 167, 212, 281
Interrupt request (IRQ), 20, 34, 185–186, 258–259
Interrupt service routine (ISR), 20, 42, 258, 502
Interrupt Set Enable Register (ISER), 87
Interrupt Set Pending Register (ISPR), 89–97, 202–204
Interrupts, 102–103, 185–186, 185f, 189
See also Non-Maskable Interrupt
control functions, 502–504
driven applications, 60
handling, 502
inputs and pending behavior, 207–212
canceling of interrupt pending status, 209
clearing of pending status, 209
IRQ assertion for disabled interrupt, 211–212
IRQ pulse during ISR execution, 210
IRQ remains high, 210
multiple IRQ pulses, 210
simple interrupt process, 207–208
simple pulse interrupt handling, 208
latency, 20, 215–217, 251
masking, 105
priority
level, 204–206
registers, 90–96
Interthread communication, 573–574
Intrinsic functions, 631
IRQLATENCY signal, 217
IT instruction, See IF-THEN instruction
J
Joint Test Action Group (JTAG), 147, 317–319
protocol, 33
K
Keil® Microcontroller Development Kit (Keil MDK), 75, 329
advantages, 330–331
assembly options, 442f
C compiler options, 441f
clock setup, 391
CMSIS files, 391
compilation, 392–393
Configuration Wizard, 392f
debug session screen, 445f
execution in SRAM, 401–404
with GNU tools for ARM® embedded processors, 438–445
installation, 331
pack installer, 331f–332f
program compilation flow, 331–334, 332f
project environment customizations, 393–399
project option tabs, 346f, 358f, 370f, 382f
stack and heap setup, 391–392
update gcc installation path, 440f
using IDE and debugger, 387–390
breakpoint insertion, 389f
debug session screen, 388f
debug session tool bar, 389f
memory window, 390f
peripheral register display using CMSIS-SVD, 390f
using MTB for instruction trace, 404–407
using simulator, 400, 401f
Keil® RTX, 243–244
KL25Z128VL microcontroller, 533
L
Late arrival mechanism, 196–197
Learning microcontroller programming, 4
Legacy 20-pin IDC connector arrangement, 147–148
Link Register (LR), 92, 126
Little Endian support, 174–175
Lockup, 286
causes, 286–287
condition during exception sequences, 287f
prevention, 288–289
process during, 288
Logic operations, 131–132
Loop function, 148
Low power (LP), 20
device benchmarking
EEMBC Energy Monitor, 530f
ULPBench-CP, 528–531
ULPBench™, 528
process, 22
Low-power features, 230–231, 511
See also Ultralow-power
approaches to reducing power, 524–525
consume power in microcontroller, 522t
debug and, 527
event communication interface, 517–519
on Freescale KL25Z, 532
low-power design practices, 523–524
on LPC1114, 542–557
power going process, 521–523
PRIMASK use with sleep, 237f
Send-Event-on-Pend feature, 515–516
sleep modes, 231–232
with sleep entering methods, 232f
Sleep-On-Exit feature, 237–239, 238f, 514–515
wake-up conditions, 235–237
WFE instruction, 232–235, 233t, 513–514
WFI instruction, 232–235, 233t, 513–514
Low-voltage pins, 527
LP, See Low power
LPC1114, low-power features on
power modes in, 543t
programming UART on, 487–489
M
MAC instructions, See Multiply accumulate instructions
Magnetoresistive Random Access Memory (MRAM), 165–166
Mail queue, 585–588, 586f, 586t
Main Stack Pointer (MSP), 169, 193, 243, 252, 643, 668
activities with simple OS, 253f
CMSIS-CORE functions, 255t
mbed™ system, 459, 459f
advantages, 462–463
Blinky program creation, 465–467
hints and tips, 478
interrupts, 476–478
mbed project, 459
peripheral objects support, 467
using printf, 468–471
railway controller modeling, 471–476
setting up FRDM-KL25Z board, 463–465
web page–login, 464f
web-based IDE, 460
working process, 460–462
MemManage fault, See Memory Management Fault
Memory Access Permission, 177–180
Memory accesses, 122–126
Memory attributes, 177–180
management, 293
Memory barrier, 308–309, 674–677, 676t
instructions, 139–141
Memory Management Fault (MemManage fault), 312
Memory Management Unit (MMU), 6, 245, 559–560
Memory map, 167–168
code region, 168
device region, 169
internal PPB, 169
peripheral region, 169
RAM region, 169
reserved memory space, 170
SRAM region, 168–169
system level design, 170
Memory ordering, 674–677, 675f
Memory Pool Management, 588–590
Memory Protection Unit (MPU), 14, 30, 87, 99–100, 178, 219, 291–292, 559–560, 649, 670
aligning addresses, 302f
cache coherency in multiprocessor systems, 301f
comparison in Cortex®-M3/M4/M7 processors, 312–313, 312t
Control Register, 296, 296t
FreeRTOS-MPU, 310–311
memory attributes, 300f, 300t–301t
memory barrier and configuration, 308–309
Region Base Address Register, 297, 298t
Region Base Attribute and Size Register, 298–301, 298t
Region Number Register, 297, 297t
setting up, 302–308, 305f
SRD feature, 309–310
stack limit using, 670
Type register, 295, 295t
use cases, 292–293
Memory remapping, 170–173
Memory system, 97–98
bus systems in Cortex®-M0 and Cortex-M0+ processors, 166–167
hardware behavior effect to programming, 180–183
Little Endian and Big Endian support, 174–175
memory access permission, 177–180
memory attributes, 177–180
memory map, 167–170
in microcontrollers, 165–166
program memory, boot loader, and memory remapping, 170–173
Single Cycle I/O Interface, 99
Message queue, 583–585, 584f, 584t
μCLinux, 245
Micro Trace Buffer (MTB), 17, 31, 109, 118–119, 320
for instruction trace, 404–407
configuration via Configuration Wizard, 405f
enabling MTB trace, 406f
support, 324–327, 326f
Microcontroller development boards, 334
Freescale Freedom FRDM-KL25Z board, 334–335, 334f
NXP LPC1114FN28 microcontroller, 336–338, 337f
STMicroelectronics
STM32F0 Discovery, 336, 337f
STM32L0 Discovery, 335–336, 335f
Microcontroller Development Kit-ARM (MDK-ARM), 438
Microcontrollers, 1, 1f, 3, 19f, 45–46
memory systems in, 165–166
typical elements inside, 18–20, 19t
MicroController Unit (MCU), 165
MicroLIB, 70–71, 398
Microprocessor, 2–3
μVision® IDE, 338, 400
new project creation, 339f
project setup steps
for Freescale FRDM-KL25Z, 339–351
for NXP LPC1114FN28 microcontroller, 376–387
for STMicroelectronics STM32F0 Discovery, 362–376
for STMicroelectronics STM32L0 Discovery, 351–362
start screen, 338f
starting Keil MDK, 338–339
Mixed language projects, 617
calling assembly functions from C codes, 618–619
calling C functions from assembly codes, 617–618
Mixed signal microcontrollers, 46
MTB instruction trace with IAR EWARM, 421
Multiple load and store instructions, 181–182
Multiply accumulate instructions (MAC instructions), 9
Multipurpose Clock Generator (MCG), 534
Mutual Exclusive (Mutex), 578–580
N
Nested exception, 186
Nested function call, 152f
Nested interrupts, 186
support, 104
Nested Vectored Interrupt Controller (NVIC), 7, 30, 170, 186, 189–190, 219, 482, 624, 636, 675
control registers for interrupt control, 200
Interrupt CLRPEND, 202–204
interrupt enable and clear enable, 200–202
interrupt priority level, 204–206
Interrupt SETPEND, 202–204
flexible interrupt management, 104
interrupt masking, 105
nested interrupt support, 104
register, 87
ICER, 87–89
ICPR, 89–90
interrupt priority registers, 90–96
ISER, 87
ISPR, 89–97
vectored exception entry, 104
Non-Maskable Interrupt (NMI), 30, 94, 186–188, 221, 279, 294, 502
Non-Volatile Memory (NVM), 165
Nonexecutable attribute, 177
Normal memory, 178
Normal sleep modes, 30
NXP LPC1114FN28 microcontroller, 336–338, 337f
project setup steps, 376–387
Blinky. c for LPC1114FN28 on Breadboard, 379–381
CMSIS-CORE selection and device-specific startup, 377f
compilation, 384–387
debugger settings, 382–384
flash programming algorithm options, 384f
flash programming status output, 386f
LPC1114FN28/102 selection for DIP part, 376f
options for ULINK2/Cortex debug, 383f
project settings, 381
project with start-up code, 377f
ULINK2/ME Cortex Debugger selection, 383f
O
One shot mode, 327
Operating system (OS), 3, 13, 30, 173, 188, 243–244
See also Cortex-M processors
context switching, stack checking in, 670
support features, 21, 243
context switching in action, 267–277
multitasking and context switching, 244f
PendSV exception, 258–260, 265–266, 266f
process stack and PSP, 252–256
SVCall exception, 256–264
SysTick timer, 245–251
Operation modes and states, 89–90, 89f
Optimizations, 647–648
options, 396–398
P
Pack installer, 331f–332f
Packet format, MTB, 131–132
Pendable Service Call (PendSV Call), 188
PendSV exception, 30, 243, 258–266, 266f
Peripherals, 1
Personal Computer (PC), 3
Phase Locked Loop (PLL), 56, 522, 534
Polling, 58–59
Popping, 100
Power Management Controller (PMC), 534
Power Management IC (PMIC), 47
Power management unit (PMU), 239
Power on reset (POR), 534
Preemption, 104
PRIMASK register, 94, 502
masking register, 206–207
“printf” function handling, 490
mbed™ system using, 468–471
retargeting
with gcc, 493
with IAR EWARM, 492–493
with Keil® MDK, 491
semihosting
with CoIDE, 495
with IAR EWARM, 494–495
Private Peripheral Bus (PPB), 303
PRIVDEFENA bit, 296, 297f
Privileged Thread Mode, 90
Process Stack Pointer (PSP), 197, 243, 252
activities with simple OS, 253f
CMSIS-CORE functions, 255t
Processor core/CPU core, 2
Processors
ARM cortex-M processor series, 8–11
ARM Cortex®-M0 and Cortex-M0+ processors, 12–13
ARM processor families, 5–8, 6f
blurring boundaries, 8
Cortex®-M0 to Cortex-M0+ processors, 13–17, 15f
types, 4–5
Program compilation flow, 331–334, 332f
Program control, 137–139
branch instructions, 149t–150t
branch table, 151–153
function calls, 150–151
function returns, 150–151, 152f
“if-then-else” function, 147–148
loop function, 148
nested function call, 152f
push and pop of multiple registers in function, 152f
usage of branch conditions, 148–150
Program Counter (PC), 30, 92, 111, 151, 167, 185, 281
Program fetches, 16–17, 17f
Program Status Register (PSR), 93, 661
Programmer’s model, 649–650
ARMv6-M vs. ARMv7-M architectures, 650f
Programming
CMSIS-CORE versions, 508–510
controller for train modeling, 504–508
input and output functions development, 495–501
language choices, 63
Pseudo instructions, 144–145
Pulse width modulation (PWM), 467, 505–506
LED with PWM control, 467
Pushing, 100
R
Read-Only-Memory (ROM), 34
Real Time Clock (RTC), 522, 534
Real-Time eXecutive (RTX), 559, 569–573
application, 597–600
CMSIS-RTOS RTX options, 570t
configurations, 569
debugging applications with, 600
generic wait function, 590
interthread communication, 573–574
mail queue, 585–588, 586f, 586t
Memory Pool Management, 588–590
message queue, 583–585, 584f, 584t
Mutex, 578–580
osSignalWait function, 577f
osStatus enumeration definition, 573t
RTX_Config_CM. c customization, 604
semaphore, 580–583
signal event communication, 574–578, 575f, 575t
SVC services for unprivileged threads, 593–597
thread, 567–569
time-out value, 590
timer feature, 590–593, 591t
Real-Time Operating System (RTOS), 3, 61, 244, 559–560
Reduced Instruction Set Computing processor (RISC processor), 12
Reentrant interrupt service routine, 671–673
REGION SIZE field, 298, 299t
Reset, 55–56
sequence, 107
Reset Handler/Startup Code, 69–70
Retargeting, 490
with gcc, 493
with IAR EWARM, 492–493
with Keil® MDK, 491
Reverse ordering operations, 135–137
ROM table registers, 117–118
Rotate operations, 132–134
S
S field, See Shareable field
Saved registers, 213
“scanf” function, 501
SCB-Interrupt Control State Register (SCB-ICSR), 92
SD card interface, See Secure Digital card interface
SecurCore® series, 8
Secure Digital card interface (SD card interface), 170
Self-reset, 226–228
Semaphore, 580–583
implementation, 673–674
Semihosting, 490
with CoIDE, 495
with IAR EWARM, 494–495
Send Event instruction (SEV instruction), 143, 236, 519
Send-Event-On-Pend feature (SEVONPEND feature), 236, 515–516
problems in, 181
Sensors, 46
hubs, 47
Serial Peripheral Interface (SPI), 500
Serial Wire Debug Communication Protocol, 317–319
Serial Wire Debug protocol (SWD protocol), 105
Serial Wire protocol (SW protocol), 33, 358
SEV instruction, See Send Event instruction
SEVONPEND feature, See Send-Event-On-Pend feature
Shareable attribute, 178
Shareable field (S field), 299–300
Shift operations, 132–134
Signal event communication, 574–578, 575f, 575t
Signed divide instructions (SDIV), 653
Silicon technologies, 22
Simple OS
context switching in, 256f
task initialization in, 255f
Simple pulse interrupt handling, 208
Simulator, 400, 401f
Single Cycle I/O interface, 14, 99
64-bit/128-bit add, 158
64-bit/128-bit sub, 159
Sleep modes, 30
feature-related instructions, 142–143
Sleep-On-Exit feature, 30, 235, 237–239, 238f, 514–515
triggering sleep too early, 180–181
SLEEPDEEP bit field, 225, 231–232
Software development, 315–317
Software porting
from 8-bit/16-bit microcontrollers to ARM® Cortex®-M, 635
memory requirements, 637–638
migration from 8051 to ARM Cortex-M0/Cortex-M0+, 639–641
modifications, 635–637
nonapplicable optimizations for, 638–639
ARM7TDMI™ processor vs. Cortex®-M0/M0+ processor, 641–644
from ARM7TDMI™ to Cortex®-M0/Cortex-M0+ processors, 645
assembly code, 647
atomic access, 647
C program code, 646–647
interrupt, 645–646
optimizations, 647–648
start-up code, 645
vector table, 645
Cortex-M processors, 648–656
software modifications, 656
Cortex®-M0 processors, 635
between Cortex®-M0/M0+
and Cortex-M1 processors, 656
and Cortex-M3 processors, 657–659, 657f
and Cortex-M4/M7 processor, 659–660
Special Function Registers (SFRs), 636
Special registers, 90–96
Stack analysis
by tool chain, 669
by trial, 669–670
Stack checking, 670
Stack Frame, 213
layout, 31–34
Stack limit, 670
Stack memory, 71
accesses, 126–127
operations, 100–102
Stack overflow, 668–669
stack layout for, 670f–671f
Stack Pointer (SP), 29–31, 100, 212, 252, 639, 672–673
CMSIS-CORE functions, 255t
selection switching, 254f
separate memory ranges, 252f
SP-related addressing mode, 71
task initialization in simple OS, 255f
Start-up, 645
code in C, 663–668
sequence, 106–108
State Retention Power Gating (SRPG), 239, 240f
Static Random Access Memory (SRAM), 3, 34, 165
STM32F0 discovery, programming UART on, 486–487
STM32L0 discovery, programming UART on, 484–485
STMicroelectronics STM32F0 Discovery, 336, 337f
project setup steps, 362–376
Blinky. c for STM32F0 Discovery Board, 367–368
CMSIS-CORE selection and device-specific startup, 365f
compilation, 372–376
compile result for the blinky project, 374f
debugger session, 375f
debugger settings, 371–372
flash programming algorithm options, 373f
flash programming status output, 374f
frequently used buttons on tool bar, 373f
GPIO functions file, 368–369
options for ST-LINK, 372f
project settings, 370–371
project with start-up code, 365f
ST-LINK debug adaptor selection, 371f
STM32F051R8 selection, 364f
STMicroelectronics STM32L0 Discovery, 335–336, 335f
Blinky. c for STM32L0 Discovery board, 354–355
GPIO functions file, 356–357
project setup steps for, 351–362
CMSIS-CORE selection and device-specific startup, 352f
compilation, 360–362
compile result for blinky project, 361f
debugger session, 363f
debugger settings, 358–360
flash programming algorithm options, 360f
flash programming status output, 362f
options for ST-LINK, 359f
project settings, 357
project with start-up code, 352f
ST-LINK debug adaptor selection, 359f
STM32L053C8 selection, 351f
Strongly Ordered memory (SO memory), 178
Sub-Region Disable feature (SRD feature), 309
allowing efficient memory separation, 309–310
to control access right to separate peripherals, 311f
overlapped regions with, 310f
reducing total number of needed regions, 310
wasting of memory space without, 309f
Sub-Region Disable field, 298–299
Suffix, 117–118
SuperVisor Call (SVC), 141, 188, 259–261
exception, 243, 256, 259–266
instruction, 243, 256, 257f
services for unprivileged threads, 593–597
system exception types, 30
SVC instruction, See SuperVisor Call (SVC)
SVCall exception, See SuperVisor Call (SVC)
SW protocol, See Serial Wire protocol
SWD protocol, See Serial Wire Debug protocol
SYSRESETREQ bit, See System Reset Request bit
System Control Block (SCB), 80, 105, 200, 219, 258, 321, 657
AIRCR, 224, 224t
CPU ID Base Register, 220, 221t
priority level registers for programmable system exceptions, 221f
register, 693t
ICSR, 92
SCR, 94
SHR[0], 96
SHR[1], 96–97
inside SCB data structure, 220t
SCR, 225, 225t
SHCSR, 226, 226t
VTOR, 223, 223t
System Control Processor (SCP), 18
System Control Register (SCR), 94, 219–220, 225, 225t, 511
See also Low-power features
self-reset, 226–228
vector table relocation, 228–230
System Control Space (SCS), 104, 169, 200, 219, 219t, 246, 294, 569, 675
System Handler Control and State Register (SHCSR), 226, 226t
System Handler Priority Register 2 (SHR[0]), 96
System Handler Priority Register 3 (SHR[1]), 96–97
System Handler Priority Registers (SHPR), 221, 221t
System reliability, 293
System Reset Request bit (SYSRESETREQ bit), 186, 224, 227, 283, 382
System Tick timer (SysTick timer), 13, 30, 80, 188–189, 219, 243, 245–251
access functions, 57
calibration value register, 248t, 249, 250t
with polling, 249f
setting up SysTick, 248–250
in single shot mode, 251
SysTick handler, 672
execution, 721
SysTick registers, 246, 246f, 247t, 697t
calibration value register, 102–103
control and status register, 99
current value register, 100–102
reload value register, 99–100
for timing measurement, 250–251
System-on-a-Chip (SoC), 2
“SystemCoreClock” standardized software variable, 81, 250
SystemFrequency, 250
SysTick timer, See System Tick timer
SysTick_Config(uint32_t ticks) function, 248
T
Tail chaining, 196
Target options, 393–396
Technical Reference Manual (TRM), 113–114
10-pin Cortex® debug connector, 147, 151f
20-pin Cortex® debug + ETM connector, 147–153, 152f
Test (TST), 118
TEX field, See Type Extension field
Thread, 567–569
in CMSIS-RTOS, 568f
mode, 90
priority, 604
Thumb® state (T), 5, 90, 109
Tightly Coupled Memories, 7
Time-out value, 590
Timer feature, 590–593, 591t
Tool chain support, 21
Trouble shooting, 601
debug connection affect by I/O setting, 722
debug protocol selection/configuration, 723
device specific requirements, 723
using event output as pulse I/O, 723
incorrect SVC parameter passing method, 722
interrupt problem, 721–722
miscellaneous, 603
OS error reporting support, 603
OS feature configurations, 603
pitfalls in programming
breakpoints and inline, 728
data alignment, 725
function pointers, 726
interrupt disable, 726–728
interrupt priority levels, 723–724
missing volatile keyword, 726
read-modify-write, 726
stack overflow, 724
SystemInit function, 728
privileged level, 602–603
problem in Run/Start program, 165–166
program started, but enter HardFault, 169
sleep problems, 177–180
stack size requirements, 602
TrustZone®, 6
Type Extension field (TEX field), 299–300
U
ULPBench-Core Profile (ULPBench-CP), 528–531
Ultra Low Leakage (ULL), 41
Ultralow-power (ULP), 511
See also Low-power features
debug considerations, 527
low-power features, 511–519
microcontrollers, 45–46
Unaligned transfers, 180–181, 180f
Unified Assembler Language (UAL), 118–119, 647
Universal Asynchronous Receiver/Transmitter (UART), 264, 479, 620–621
communication, 479–481, 479f
configurations on microcontroller, 482
data transfer, 480f
programming
on FRDM-KL25Z, 482–484
on LPC1114FN28, 487–489
on STM32F0 discovery, 486–487
on STM32L0 discovery, 484–485
using RS-232 for, 481f
Universal Synchronous/Asynchronous Receiver/Transmitter (USART), 479
Unprivileged Thread Mode, 90
Unsigned divide instructions (UDIV), 653
Unsigned integer divide function, 160f
Unsigned integer square root, 161–162, 162f
Unstacking, 194–195, 195f
Upgrade path, 21
USB-JTAG adaptor, See In-circuit debugger
V
VECTCLRACTIVE bit, 224
VECTKEY field, 224
Vector catch, 279, 324
Vector Table, 69, 192–194, 639, 640t, 645
relocation, 14, 228–230
Vector Table Offset Register (VTOR), 92–93, 223, 223t, 228, 229f, 404, 658
Vectored exception entry, 104
W
Wait states, 182–183
Wait-for-Event instruction (WFE instruction), 30, 142, 232–235, 234f, 512, 607
comparison with WFI instruction, 237t
execution problem, 180–183
operation, 234f
sleep wake-up behavior, 236t
wake-up characteristics, 233t
WFI vs., 513–514
Wait-for-interrupt instruction (WFI instruction), 30, 142, 232–235, 512, 607
comparison with WFE instruction, 237t
operation, 235f
sleep wake-up behavior, 236t
wake-up characteristics, 233t
WFE vs., 513–514
Wake-up Interrupt Controller (WIC), 30, 230, 239–241, 240f, 516–517
WFE instruction, See Wait-for-Event instruction
WFI instruction, See Wait-for-interrupt instruction
Wireless communication microcontrollers, 46
Write Back Write Allocate behavior (WBWA behavior), 178
Write Through behavior (WT behavior), 178
X
XN field, See eXecute Never field
xPSR Combined Program Status Register, 93–94
Y
YIELD instruction, 144
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