Home Page Icon
Home Page
Table of Contents for
Cover image
Close
Cover image
by Joseph Yiu
The Definitive Guide to the ARM Cortex-M3, 2nd Edition
Cover image
Title page
Table of Contents
Copyright
Foreword
Foreword
Preface
Acknowledgments
Conventions
Terms and Abbreviations
CHAPTER 1. Introduction
Publisher Summary
1.1 What Is the ARM Cortex-M3 Processor?
1.2 Background of ARM and ARM Architecture
1.3 Instruction Set Development
1.4 The Thumb-2 Technology and Instruction Set Architecture
1.5 Cortex-M3 Processor Applications
1.6 Organization of This Book
1.7 Further Reading
CHAPTER 2. Overview of the Cortex-M3
Publisher Summary
2.1 Fundamentals
2.2 Registers
2.3 Operation Modes
2.4 The Built-In Nested Vectored Interrupt Controller
2.5 The Memory Map
2.6 The Bus Interface
2.7 The MPU
2.8 The Instruction Set
2.9 Interrupts and Exceptions
2.10 Debugging Support
2.11 Characteristics Summary
CHAPTER 3. Cortex-M3 Basics
Publisher Summary
3.1 Registers
3.2 Special Registers
3.3 Operation Mode
3.4 Exceptions and Interrupts
3.5 Vector Tables
3.6 Stack Memory Operations
3.7 Reset Sequence
CHAPTER 4. Instruction Sets
Publisher Summary
4.1 Assembly Basics
4.2 Instruction List
4.3 Instruction Descriptions
4.4 Several Useful Instructions In the Cortex-M3
CHAPTER 5. Memory Systems
Publisher Summary
5.1 Memory System Features Overview
5.2 Memory Maps
5.3 Memory Access Attributes
5.4 Default Memory Access Permissions
5.5 Bit-Band Operations
5.6 Unaligned Transfers
5.7 Exclusive Accesses
5.8 Endian Mode
CHAPTER 6. Cortex-M3 Implementation Overview
Publisher Summary
6.1 The Pipeline
6.2 A Detailed Block Diagram
6.3 Bus Interfaces on the Cortex-M3
6.4 Other Interfaces on the Cortex-M3
6.5 The External PPB
6.6 Typical Connections
6.7 Reset Types and Reset Signals
CHAPTER 7. Exceptions
Publisher Summary
7.1 Exception Types
7.2 Definitions of Priority
7.3 Vector Tables
7.4 Interrupt Inputs and Pending Behavior
7.5 Fault Exceptions
7.6 Supervisor Call and Pendable Service Call
CHAPTER 8. The Nested Vectored Interrupt Controller and Interrupt Control
Publisher Summary
8.1 Nested Vectored Interrupt Controller Overview
8.2 The Basic Interrupt Configuration
8.3 Example Procedures In Setting Up an Interrupt
8.4 Software Interrupts
8.5 The SYSTICK Timer
CHAPTER 9. Interrupt Behavior
Publisher Summary
9.1 Interrupt/Exception Sequences
9.2 Exception Exits
9.3 Nested Interrupts
9.4 Tail-Chaining Interrupts
9.5 Late Arrivals
9.6 More on the Exception Return Value
9.7 Interrupt Latency
9.8 Faults Related to Interrupts
CHAPTER 10. Cortex-M3 Programming
Publisher Summary
10.1 Overview
10.2 A Typical Development Flow
10.3 Using C
10.4 CMSIS
10.5 Using Assembly
10.6 Using Exclusive Access for Semaphores
10.7 Using Bit Band for Semaphores
10.8 Working with Bit Field Extract and Table Branch
CHAPTER 11. Exception Programming
Publisher Summary
11.1 Using Interrupts
11.2 Exception/Interrupt Handlers
11.3 Software Interrupts
11.4 Example of Vector Table Relocation
11.5 Using SVC
11.6 SVC Example: Use for Text Message Output Functions
11.7 Using SVC with C
CHAPTER 12. Advanced Programming Features and System Behavior
Publisher Summary
12.1 Running a System with Two Separate Stacks
12.2 Double-Word Stack Alignment
12.3 Nonbase Thread Enable
12.4 Performance Considerations
12.5 Lockup Situations
12.6 FAULTMASK
CHAPTER 13. The Memory Protection Unit
Publisher Summary
13.1 Overview
13.2 MPU Registers
13.3 Setting Up the MPU
13.4 Typical Setup
CHAPTER 14. Other Cortex-M3 Features
Publisher Summary
14.1 The Systick Timer
14.2 Power Management
14.3 Multiprocessor Communication
14.4 Self-Reset Control
CHAPTER 15. Debug Architecture
Publisher Summary
15.1 Debugging Features Overview
15.2 Coresight Overview
15.3 Debug Modes
15.4 Debugging Events
15.5 Breakpoint in the Cortex-M3
15.6 Accessing Register Content in Debug
15.7 Other Core Debugging Features
CHAPTER 16. Debugging Components
Publisher Summary
16.1 Introduction
16.2 Trace Components: DWT
16.3 Trace Components: ITM
16.4 Trace Components: ETM
16.5 Trace Components: TPIU
16.6 The Flash Patch and Breakpoint Unit
16.7 The Advanced High-Performance Bus Access Port
16.8 ROM Table
CHAPTER 17. Getting Started with the Cortex-M3 Processor
Publisher Summary
17.1 Choosing a Cortex-M3 Product
17.2 Development Tools
17.3 Differences between the Cortex-M3 Revision 0 and Revision 1
17.4 Differences between the Cortex-M3 Revision 1 and Revision 2
17.5 Benefits and Effects of the Revision 2 New Features
17.6 Differences between the Cortex-M3 and Cortex-M0
CHAPTER 18. Porting Applications from the ARM7 to the Cortex-M3
Publisher Summary
18.1 Overview
18.2 System Characteristics
18.3 Assembly Language Files
18.4 C Program Files
18.5 Precompiled Object Files
18.6 Optimization
CHAPTER 19. Starting Cortex-M3 Development Using the GNU Tool Chain
Publisher Summary
19.1 Background
19.2 Getting the GNU Tool Chain
19.3 Development Flow
19.4 Examples
19.5 Accessing Special Registers
19.6 Using Unsupported Instructions
19.7 Inline Assembler in the GNU C Compiler
CHAPTER 20. Getting Started with the Keil RealView Microcontroller Development Kit
Publisher Summary
20.1 Overview
20.2 Getting Started with μVision
20.3 Outputting the “Hello World” Message Via Universal Asynchronous Receiver/Transmitter
20.4 Testing the Software
20.5 Using the Debugger
20.6 The Instruction Set Simulator
20.7 Modifying the Vector Table
20.8 Stopwatch Example with Interrupts with CMSIS
20.9 Porting Existing Applications to Use CMSIS
CHAPTER 21. Programming the Cortex-M3 Microcontrollers in NI LabVIEW
Publisher Summary
21.1 Overview
21.2 What Is LabVIEW
21.3 Development Flow
21.4 Example of a LabVIEW Project
21.5 How It Works
21.6 Additional Features in LabVIEW
21.7 Porting to Another ARM Processor
APPENDIX A. The Cortex-M3 Instruction Set, Reference Material
A.1 Instruction Set Summary
A.2 About the Instruction Descriptions
A.3 Memory Access Instructions
A.4 General Data-Processing Instructions
A.5 Multiply and Divide Instructions
A.6 Saturating Instructions
A.7 Bitfield Instructions
A.8 Branch and Control Instructions
A.9 Miscellaneous Instructions
APPENDIX B. The 16-Bit Thumb Instructions and Architecture Versions
APPENDIX C. Cortex-M3 Exceptions Quick Reference
C.1 Exception Types and Enables
C.2 Stack Contents After Exception Stacking
APPENDIX D. Nested Vectored Interrupt Controller and System Control Block Registers Quick Reference
APPENDIX E. Cortex-M3 Troubleshooting Guide
E.1 Overview
E.2 Developing Fault Handlers
E.3 Understanding the Cause of the Fault
E.4 Other Possible Problems
APPENDIX F. Example Linker Script for CodeSourcery G++
F.1 Example Linker Script for Cortex-M3
APPENDIX G. CMSIS Core Access Functions Reference
G.1 Exception and Interrupt Numbers
G.2 NVIC Access Functions
G.3 System and SysTick Functions
G.4 Core Registers Access Functions
G.5 CMSIS Intrinsic Functions
G.6 Debug Message Output Function
APPENDIX H. Connectors for Debug and Tracers
H.1 Overview
H.2 The 20-Pin Cortex Debug + ETM Connector
H.3 The 10-Pin Cortex Debug Connector
H.4 Legacy 20-Pin IDC Connector
H.5 Legacy 38-Pin Mictor Connector
References
Index
Search in book...
Toggle Font Controls
Playlists
Add To
Create new playlist
Name your new playlist
Playlist description (optional)
Cancel
Create playlist
Sign In
Email address
Password
Forgot Password?
Create account
Login
or
Continue with Facebook
Continue with Google
Sign Up
Full Name
Email address
Confirm Email Address
Password
Login
Create account
or
Continue with Facebook
Continue with Google
Next
Next Chapter
Title page
Add Highlight
No Comment
..................Content has been hidden....................
You can't read the all page of ebook, please click
here
login for view all page.
Day Mode
Cloud Mode
Night Mode
Reset