10
Recent Advances in Functional 2D Materials for Field Effect Transistors and Nonvolatile Resistive Memories

Adnan Younis1, Jawad Alsaei1, Basma Al‐Najar1, Hacene Manaa1, Pranay Rajan2, El Hadi S. Sadki2, Aicha Loucif3, and Shama Sehar4

1University of Bahrain, College of Science, Department of Physics, Sakhir Campus, Sakhir, 32038, Kingdom of Bahrain

2UAE University, College of Science, Physics Department, Al Ain, 15551, UAE

3Qassim University, College of Science, Department of Physics, Buraidah, 51452, Saudi Arabia

4University of Bahrain, College of Science, Sakhir Campus, Sakhir, 32038, Kingdom of Bahrain

10.1 Introduction to 2D Materials

During the past decade, scientific community has devoted tremendous efforts to explore the strikingly and superior electrical, mechanical, and optical properties of 2D materials. The graphene discovery in 2004 [1], having an unmatched extraordinary physical and chemical property, offers potential in various sectors such as energy storage [2], sensors [3], membranes [4], and electronics [5, 6]. Following the success in the synthesis of graphene (via chemical and physical route), the scientific community explored various other existing crystalline, van der Waals (vdW) materials and succeeded in realizing several other 2D materials derived from their bulk counterpart and thus creates an exclusive new family of 2D materials. Some examples of the investigated materials are: boron nitride [7], metal dichalcogenides [8], black phosphorus (BP) (phosphorene) [9], MXenes [10], and 2D metal–organic frameworks (polymers) [11]. The preliminary reports on 2D materials have mainly focused on fundamental studies to explore their inherent properties, which later shifted toward application‐oriented investigations. For instance, it has been established now that 2D materials can be a potential component for functional electronics [12] and energy storage devices [13]. Therefore, in the coming era, 2D materials are expected to be key governing materials to revolutionize existing state‐of‐the‐art technologies, such as renewable energy, biomedical imaging, quantum computing, and water desalination, etc.

Typically, 2D materials are referred to as layered materials that have strong in‐plane covalent bonds and weak interlayer (out‐of‐plane) and layer to substrate bonding. In a layered structure, the interlayer bonding is due to the weak vdW forces [14]. Monolayer, bilayer, or thickness upto few atomic layers possess exceptional electronic, mechanical, and thermal properties, thus 2D materials are suitable candidate for array electronics. Moreover, the low‐cost, nontoxic, and environmentally friendly as well as the low‐temperature synthesis of 2D materials make them easy to fabricate and transfer to any substrate; thus, making the process of integration on the substrate cost‐effective and reducing the difficulties in array device fabrication [15, 16]. Moreover, having exceptional high mobility and bandgap, along with reduced short‐channel effects [17, 18], makes them superior in comparison to conventional materials.

A few decades ago, the electronic industry was heavily dependent on silicon. However, several classes of 2D materials have recently become potential contenders to revolutionize the electronics industry. Among many, carbon‐based 2D materials such as graphene, transition metal dichalcogenides (TMDCs), and transition metal oxides (such as molybdenum trioxide [MoO3]) have demonstrated excellent physical and chemical functionalities with great flexibility in shape‐controlled synthesis, modifiable surface‐to‐volume ratios, and tunable surface charge characters [19, 20]. Contrary to graphene, which has no bandgap, dichalcogenides and buckled nanomaterials possess sizeable bandgaps. Moreover, these materials may become semiconducting or metallic depending on the number of layers (for monolayer thickness, they possess direct bandgaps, while in the bulk phase, they express indirect bandgaps) [19, 20].

2D materials have been investigated for various electronics applications such as field effect transistors (FETs) [21, 22], solar cells [23, 24], light‐emitting diodes (LEDs) [25, 26], photodetectors [27, 28], and memory devices [29, 30], etc. However, it just marks the beginning and various unexplored applications are yet to be investigated. The research on atomistic thin monolayer, bilayer 2D materials is in its infancy, and numerous enormous efforts are made to integrate these 2D materials within other materials (composite or hybrid material) to upscale their performance and properties. This chapter provides an overview of the electronic band structures and transport properties of the 2D materials. Afterward, recent advancement in 2D materials‐related electronic device applications such as (i) transistors and (ii) nonvolatile computer memories are presented. Finally, conclusion and an outlook on 2D materials to develop next‐generation electronic devices are presented.

10.2 Electronic Band Structure in 2D Materials

The demand for miniaturization of electronic and optoelectronic components has grown rapidly in recent years. With the use of conventional materials (three‐dimensional materials), it is known that the performance of the devices can be hindered as one approaches the atomic level. This is attributed to the fact that the key properties of the underlying materials can be degraded at an atomistic scale. For example, it has been shown that the electron mobility at room temperature of ultrathin‐body silicon‐on‐insulator metal–oxide–semiconductor FET is suppressed due to large carrier scattering induced by surface roughness [31]. On the other hand, electronic band structure modulation in 2D materials is a key to develop next‐generation nanoelectronic devices [32].

Bandgap engineering is a known promising means for regulating the properties of bulk insulators and semiconductors and can be achieved by different means including strain engineering [33], temperature modulation [34], and doping [35]. However, 2D materials provide more freedom to tune the electronic band structures that were not previously available for the bulk materials. These include: layer‐dependent properties (i.e. the number of layers) [36, 37] and stacking order [38, 39]. For example, graphene, an atom‐thick hexagonal honeycomb arrangement of carbon atoms, is known to have zero bandgap. The electronic structure of graphene significantly changes when two or more layers of graphene are stacked [40, 41]. This leads to an overlap of energy levels around the Fermi level, thus changing the conductivity of graphene [40].

Xenes, such as BP, offer tunable optoelectronic properties as the number of layer changes from monolayer to bi‐ or trilayer [42]. Phosphorene (a monolayer sheet of BP) is a direct band‐gap semiconducting material having puckered honeycomb arrangement of atoms. Theoretical studies including tight‐binding models [43] and more sophisticated density functional theory (DFT)/GW simulations have reported a systematic decrease in the bandgap of phosphorene as the number of layers is increased, and it ranges from 0.3 to 2.0 eV [37]. BP has direct bandgap from bulk to monolayer, thus making it a promising material for optoelectronic applications [44, 45].

Similarly, the electronic properties of 2DTMDCs have shown rich behavior with layer thickness variations. TMDCs have MX2 structure, where M is a transition metal and X is a chalcogen. The M atoms are covalently bonded together to form a two‐dimensional plane that is sandwiched between two layers of the X atoms forming a three‐atom‐thick monolayer. The layered structure of bulk TMDCs is composed of these monolayers that are held together by vdW interactions. Similar to BP, a general trend of the inverse relationship between the energy bandgap and the number of layers is observed in TMDCs [36], which is attributed to quantum confinement and the weak interlayer vdW forces [46, 47]. Many TMDCs (such as MoX2 and WX2) can demonstrate a transition from indirect to direct bandgap by reducing their thickness down to a single layer, which is attributed to the inhomogeneity of the nearest‐neighbor interlayer interactions [48].

Owing to the layered nature and the weak interlayer interactions, the electronic structure of 2D materials can also be tuned by change in stacking order or even by designing different vdW heterostructures [49, 50]. For example, ABA‐ (Bernal) and ABC‐ (rhombohedral) stacked trilayer graphenes (TLGs) have shown quite different band structures. Contrary to ABA‐stacked TLG, which is semimetallic and has both linear and quadratic energy dispersion around the Dirac points, ABC‐stacked TLG has a bandgap of ∼6 meV at low temperatures with cubic dispersion of energy in the vicinity of the Dirac points [51]. Stacking adds an extra degree of freedom to tune electronic properties (e.g. by angular rotations [or twisting] of the two monolayer slabs of the material relative to each other) [52]. The electronic structure of bilayer graphene has shown interesting behavior at a critical twist angle of about 1.1°, where superconducting and correlated insulating behaviors are observed in association with the formation of low‐energy flat bands [53, 54].

In BP, three different types of stacking orders (namely AA‐, AB‐, and AC‐ stacking) have shown to have pronounced discrepancies in the corresponding bandgap that ranges between 0.78 and 1.04 eV [38]. This discrepancy has been attributed to the sensitivity of the conduction band minimum (CBM) to the stacking order. Similar behavior has also been observed in trilayer phosphorene where, ABA, AAB, and ACA stacking orders possess different bandgaps respectively [55]. The sensitivity of the electronic properties to stacking order has also been observed in bilayers of group‐IV monochalcogenides and TMDCs. The bandgap of SnSe, for example, ranges from 0.79 eV (indirect) for AA stacking to 1.23 eV (direct) for AC stacking [39]. Moreover, SnS has an indirect‐to‐direct bandgap transition for different stacking orders, although the corresponding change in the gap size is not as dramatic as that of SnSe. In twisted bilayer MoS2, the variation of interlayer spacing and the inversion symmetry breaking induced by the twist angle have considerable effects on the indirect gap [56, 57]. The emergence of flat bands at the valence band maximum has been observed for small twist angles [57].

In 2D materials, several other means such as external electric field, strain engineering, chemical functionalization, sphere diameter engineering, or by hybridization of these approaches can be adopted to tune their band structures. While there is no room to go through all of them in this brief review, interested readers are directed to go through more comprehensive reviews [58, 59].

10.3 Electronic Transport Properties of 2D Materials

High‐performance, miniaturized, and compatible nanoelectronic devices are the best examples of modern technology and have played a crucial role in validating Moore's law [60, 61]. The FETs with high carrier mobility, high on‐current to off‐current switching ratio (Ion/Ioff), and low contact resistance are one of the best devices using nanotechnology. Tremendous research has focused on investigating the electronic transport properties in 2D materials for potential applications in FETs. Carrier mobility, which mainly characterizes the electronic transport, has been extensively studied in 2D materials. Graphene is well known for its high carrier mobility (250 000 cm2/V s) at room temperature [62], which is about 2 orders of magnitudes larger than Si. However, the absence of an energy gap in graphene lowers the Ion/Ioff ratio and thus hinders the graphene‐based FETs' suitability for logic circuits, but are suitable for radio‐frequency devices [63]. Although there are existing methods to introduce a band gap in graphene, they usually come at the expense of low mobility.

The zero‐bandgap limitation in graphene has directed researchers to explore large‐bandgap semiconducting 2D materials with high carrier mobility. A promising candidate is phosphorene, which has a direct bandgap and high anisotropic electron mobility of ∼1100 cm2/V s along the armchair direction and ∼80 cm2/V s along the zigzag direction [64]. Phosphorene also shows an asymmetry between electron and hole mobilities, which is attributed to the difference in the deformation potential for each carrier. Less anisotropic values have been reported for few‐layer BP, where Hall mobilities of 1000 and 600 cm2/V s have been measured for holes along with the armchair and zigzag directions, respectively [65].

Another promising example is the monolayers of the TMDCs family, where many of them have significant bandgap allowing for high Ion/Ioff ratios, although their intrinsic carrier mobility cannot compete with graphene and BP. For instance, DFT calculations have predicted room‐temperature intrinsic electron mobility of 340–410 cm2/V s in MoS2 [66, 67] and 270 cm2/V s for hole mobility [68]. Other TMDCs have been predicted to own mobility ranging from 240 cm2/V s in MoSe2 upto 3500 cm2/V s in HfSe2 [67].

The values quoted earlier for carrier mobility are intrinsic or phonon‐limited. In practice, mobility can be highly affected by external environmental and device factors and can be severely suppressed by extrinsic scattering effects such as Coulomb scattering from charge impurities, scattering due to structural defects (such as vacancies and grain boundaries), and scattering due to remote interfacial phonons (RIP) [69]. These factors can result in large discrepancies between the calculated intrinsic mobilities and the measured ones, as well as for the measurements under different conditions. For example, mobility of graphene can be reduced down to 40 000 cm2/V s when placed on SiO2 substrate due to RIP scattering [70]. Additionally, diverse mobility values have been reported for MoS2 in different experimental conditions such as 150 cm2/V s [71], 80 cm2/V s [72], 71 cm2/V s [73], and 0.5–3 cm2/V s [74].

Carrier mobility is also sensitive to temperature (T) variations. In general, the temperature dependence obeys a power law in the form of μ∼T−γ, where the exponent “γ” is dependent on the choice of materials. For example, the calculated (γ) in MoS2 monolayer is 1.52 [66], while in few‐layer BP, it was calculated to be less than 0.5 for temperatures below 80 K, indicating a weak dependence on the temperature, and in the range between 0.6 and 1.5 for temperatures above 100 K [75]. Many attempts have been made to reduce the scattering effects and improve carrier mobilities of 2D materials in FETs. In graphene, mobilities higher than 200 000 cm2/V s have been achieved by suspending the graphene layer ∼150 nm above SiO2 surface [76]. Layer encapsulation is another approach to improve carrier mobility. For example, a sandwich structure of h‐BN/MoS2/graphene has shown very high mobility (34 000 cm2/V s) at low temperatures [77]. Several other approaches may also be adapted to tune the carrier mobility in 2D materials, such as strain engineering and the use of high‐κ dielectric substrates [78]. Furthermore, strategies such as 2D heterostructures and chemical doping could be effective in obtaining high carrier mobility. Despite all the limitations and narrow understanding of the fundamental properties of 2D materials, they are undoubtedly promising materials that can find their way to be adopted for high‐performance electronic devices soon.

10.4 Two‐Dimensional Materials in Field Effect Transistors

10.4.1 Field Effect Transistors

For a semiconducting material, the electric conductivity can be induced by employing heat, light, or external potential to overcome the barrier between valence and conduction bands. Particularly for FET, the semiconducting material should be activated by the means of an external electric field to turn it ON and OFF. A typical FET comprises a gate material, which acts as a channel medium between two metal electrodes usually referred as the source and drain electrodes, with a barrier layer that separates channel layer from the gate electrode as shown in Figure 10.1a. The operation of a conventional FET can be controlled by the channel conductivity (drain current) through the modulation of potential between gate and source electrodes (VGS). An important parameter to evaluate the performance of FETs is by analyzing it ON to OFF current ratios. A high‐performance FET usually refers to high Ion and low leakage power (low Ioff). Moreover, the rise of the gate potentials leads to higher Ion/Ioff ratio [79].

Schematic illustration of the cross-section of (a) n-type channel layered FET and (b) a top-gated graphene FET, (c) bottom gated FET and (d) a dual-gate FET.

Figure 10.1 Cross‐section of (a) n‐type channel layered FET and (b) a top‐gated graphene FET, (c) bottom gated FET and (d) a dual‐gate FET.

10.4.2 The Rise of 2D Materials Research in FETs

Silicon (Si) is by far extensively utilized semiconducting material for FETs applications. Conventional Si‐based FETs possess high Ion/Ioff ratios [79] due to high carrier mobilities. Moreover, Si‐based FETs have been reported for biological applications such as uncharged steroids detection [80] and physical detection such as plasmonic terahertz wave detection [81]. In addition, functional modification of Si can greatly improve the sensing, selectivity, specificity, device geometry, response, and recovery rates. However, there are some restrictions and limitations, such as reproducibility, stability, and error tolerance capacity in Si‐based devices, which hinder their wide implications in high‐performance device fabrication. Therefore, better and alternate materials were progressively explored, which may overcome the challenges by expressing the same or better performance standards.

In 2004, the 2D materials received significant attention, when University of Manchester group first published their pioneer work on graphene [1]. In the early stage of its development, it was believed that graphene could potentially be a perfect electronic material that may have all features to revolutionize existing semiconductor industry, which is mostly based on conventional semiconductors. Various research teams focused their shifts to develop graphene‐based transistors, and in 2007, M. C. Lemme et al. successfully demonstrated the first graphene‐based metal–oxide–semiconductor field effect transistor (MOSFET) [82]. However, this work could not gain the required attention from an electronics perspective and the main reason behind this was that graphene does not possess any electronic bandgap. Due to this, the graphene‐MOSFETs cannot be turned OFF, once switched to ON state. Hence, they are not suitable to replace digital complementary metal–oxide–semiconductor (CMOS) circuits, which are currently applied in almost 70% of the overall chip market. Furthermore, due to its gapless energy bands, its performance in radio‐frequency circuits significantly deteriorates. Despite all these efforts, the research on graphene transistors is still underway. The advances in graphene research have inspired researchers to explore further functional 2D materials beyond graphene and numerous other 2D materials that have been discovered so far. As many 2D materials have sizeable bandgaps and therefore have great potential in the semiconducting electronics industry. Although numerous 2D materials have shown promising results for transistors applications, due to limited space, we will review only some recent developments in graphene and TMDCs‐based transistors.

10.4.3 Graphene‐Based Field Effect Transistors

The fabrication routes such as photolithography, physical vapor deposition for device patterning, and evaporation techniques are generally implied to fabricate metal contacts for FETs. The graphene‐based channel layer can either be transferred to a patterned device from a chemical vapor deposition (CVD) synthesized graphene on a copper substrate or directly from mechanically exfoliated graphene [83]. On the other hand, plasma etching of a CVD‐deposited bulk layer of graphene can be used to fabricate graphene channel layer [84]. Typically, graphene‐based FETs are fabricated in three different configurations; (i) Top gate configuration: in this configuration, epitaxial graphene can be grown on top of an SiC layer. A top gate is formed by depositing a thin dielectric layer (usually Al2O3) on top of a graphene layer. (ii) Bottom gate configuration: a sequential deposition of dielectric and graphene layer on a highly doped silicon substrate, where the graphene layer acts as a channel layer. (iii) Dual‐gate configuration: in the dual‐gate mode, a dielectric layer is deposited on top of graphene layer to form another gate, thus providing more freedom to both gates for modulating free carrier concentration in the channel. It is noteworthy to mention here that the interfaces in all configurations are very critical and to realize high‐performance graphene‐based FET, excellent‐quality interfaces are needed. These three configurations are schematically shown in Figure 10.1b–d.

The early demonstration of graphene‐based FET comprised a bottom‐gate configured device [1]. A ∼300 nm thick SiO2 layer was used on the top of a doped silicon substrate. Although the demonstration of graphene FET device was successful, such device suffered from poor gate control and parasitic capacitance issues, mainly due to uncovered graphene surface. Afterward, an additional layer of SiO2 was used as the gate dielectric layer [85]. The carrier mobility extracted from these devices surpassed the mobility reported for silicon‐based devices and thus opened new avenues to further research for practical electronics applications. Thereafter, significant efforts have been made to achieve very high mobility values for monolayer graphene FETs by using either SiO2/Si or metal/HfO2 bottom‐gate configurations [86, 87]. However, the transport properties of graphene FETs are extremely sensitive to the local environment and device processing methods. For instance, the device exposure to the local environment and contaminants such as residues of resists, water, or any other metallic impurity during fabrication can severely degrade the device's performance [88].

To tackle these issues, several strategies have been adopted to improve the performance limits of graphene FETs. For instance, to reduce the effect of contact resistance and to lower the carrier scattering effects, a heterostructure comprising hexagonal boron nitride (h‐BN) and graphene has been formed, which expressed a very high mobility value in the order of 105 cm2/V s [89]. Similarly, Wang et al. used low‐pressure CVD conditions to modulate single crystals of monolayer h‐BN (∼20 µm) [90]. Moreover, the high‐temperature oxidation of h‐BN single crystals has been found to clean the h‐BN/graphene interface, which usually causes unnecessary device degradation during traditional poly(methyl methacrylate) (PMMA)‐assisted transfer method. Consequently, very high hole mobility on the cleaned h‐BN/graphene device was reported, almost sixfold higher than that of the untreated h‐BN/graphene device. The performance of graphene‐based FET devices has been also improved by replacing dielectric layer of SiO2 with h‐BN [91]. Due to the absence of dangling bonds or charge traps, h‐BN has higher surface phonon modes [91]. Therefore, superior performance in the h‐BN‐based FETs was achieved compared with SiO2.

It is well known that layers in the 2D layered structures are stacked due to strong in‐plane bonding and are coupled to each other by van der Waals forces. A heterostructure design of graphene with the 2D layered materials can potentially demonstrate exceptional device performance (e.g. charge transportation), better than their individual counterparts. One such effort was made by Khan et al. in which a vertical heterostructure comprising graphene/molybdenum disulfide (MoS2) has been fabricated [92]. To avoid the influence of impurity charges and for better conductivity, h‐BN was deposited on SiO2 substrate and titanium (Ti) top electrode was replaced by Mo metal. The subjected device exhibited a large Ion/Ioff ratio (∼106). Moreover, a strong current rectification behavior was also noted, which was attributed to the rearrangement of Schottky barrier heights at the graphene/MoS2 interface. In another work, similar adjustment in Schottky barrier height at graphene/MoS2 interface was recorded under mechanical strain [93]. The mechanical strain can influence the barrier height by shifting the Fermi level of graphene.

10.4.4 2D Transition Metal Dichalcogenides (TMDCs) in Transistors

Currently, MOSFETs are regarded as the main component of semiconducting logic devices. The materials that are selected to be used in a logic device should fulfill some basic requirements. For instance, device should be able to demonstrate a high mobility and very low conductance in its standby state for power‐efficient device. Moreover, it should possess very high Ion/Ioff ratio, typically of the order of 104–107. [94] TMDCs have attained tremendous attention in past, owing to their fascinating and novel characteristics making them applicable in a range of fields such as sensors, nanoelectronics, and nanophotonics [95]. Bandgap of MoS2 lies between 1.2 and 1.5 eV for bulk, few or a single‐layered material and thus has a great potential to be used in electronic devices. In the early investigation on TMDCs (MoS2)‐based transistor, first a single‐layered MoS2 as a channel layer device was fabricated, which demonstrated low mobility in the range of 0.1–10 cm2/V s [96]. Thereafter, an additional layer of 30 nm thick HfO2 was deposited on top of the monolayered MoS2 channel. The modified transistor with a top‐gate insulator expresses a current ON/OFF ratio higher than 108 with mobility boosted almost 20 times than the device without any gate insulator. This demonstration of the first TMDCs (MoS2)‐based transistor [96] sparked a strong resurgence to further investigate such materials for electronic device applications.

Doping in MoS2 has been utilized as an effective strategy to improve device performance. Recently, MoS2 showed p‐type conductivity when chemically doped with AuCl3 as compared with pristine MoS2, which is an intrinsic n‐type semiconducting material [97]. The AuCl3‐doped layer was assumed to have higher hole density than the pristine bottom layer and post‐annealing treatment may help the dopants to diffuse into the channel layer that enhanced the overall device conduction. It is noted that the doped FETs exhibit very high ON/OFF ratios, greater than 107, with a room‐temperature mobility of 72 cm2/V s, which is almost double than that of the undoped one. In yet another work, benzyl viologen (BV) was used as a dopant in a few layers thick MoS2 crystals [98]. According to their observations, a very stable electron transfer complex in ambient and vacuum can be generated by transferring of surface charges from BV molecule to MoS2. A very high carrier sheet density of ∼1.2 × 1013 cm−2 was obtained by using a reduced contact resistance of factor of ∼3, and excellent switching characteristics with a subthreshold swing of  ∼77 mV/decade were noted for BV‐doped MoS2 devices.

The effect of gate electrodes at the channel/metal gate interface is very critical and considered as a major bottleneck for the development of high‐performance MoS2‐based FET transistors. Seo et al. fabricated a MoS2 FET device with nitrogen‐doped graphene contacts to evaluate suitable electrode material for the Schottky barrier heights issues [99]. Usually, high contact resistance between channel and metal electrodes generates a large potential drop (even at zero gate bias), which significantly deteriorates the MoS2‐based FET performance. The nitrogen‐doped graphene electrodes were demonstrated to overcome the barrier obstacle by providing barrier‐free contacts at zero gate voltage in contrast to contacts made from undoped graphene. Moreover, the investigated device has expressed an excellent performance by showing low contact resistance, negative threshold voltage, almost 200 times higher ON current, and significant improvement in the field effect carrier mobility than the undoped devices. Recently, the effect of ferromagnetic contacts was investigated on the performance of directly grown MoS2 channel on SiO2/Si substrates [100]. The ferromagnetic contacts were made by 20 nm thick nickel–iron alloy (Ni80Fe20) with a work function of 4.83 eV [101]. The Schottky barrier height of MoS2 and the ferromagnetic electrode contacts at zero gate voltage were determined as 28.8 meV, which indicates ohmic contact. Thus, using ferromagnetic contacts to modulate barrier height could be an effective strategy to improve device performances for practical realization of MoS2‐based spintronic devices in near future.

The electronics research on 2D materials particularly for transistors is mainly focused on improving the charge carrier mobility, which is a critical parameter to express the stability and suitability of materials for FETs. However, several other parameters such increase in drain currents at low input gate voltages and contact resistance are some of the challenges in the FETs research. Furthermore, the precise control over phase formation, stability, and control over the number of layers need to be precisely addressed. These kinds of issues can be overcome by improving the understanding of enhanced and uniform growth of 2D materials using appropriate doping and suitable heterostructures.

10.5 Two‐Dimensional Materials as Nonvolatile Resistive Memories

In the modern and digital world, we are generating a massive amount of data in the form of bits, which is expanding relentlessly daily. The forecast, therefore, of data expansion for this year i.e. 2020 is about 44 ZB (i.e. 44 trillion gigabytes) [102]. To tackle such a huge amount of data, the memory technologies should be capable of offering exceptional storage capacity, speed, low cost, high data endurance and retention capabilities [103]. There are several excellent contenders in the race for future nonvolatile memories (NVM), which have potential to replace traditional silicon‐based flash memories such as resistive random‐access memories (RRAM) [60, 61, 104–107], phase‐change memories (PCMs) [108, 109], and magnetic random‐access memories (MRAMs) [110, 111]. The rapid progress in these technologies could play a vital role in developing cost‐effective data storage memories as well as high‐performance working memories such as static and dynamic RAMs. Researchers across the globe are putting enormous efforts for continuous development of fabrication processes by introducing novel device concepts as well as to discover new materials and nanoscale phenomenon for better understanding. Two‐dimensional materials are one such class of materials that have been extensively investigated for these applications over the past decade. The unique chemical and physical properties of 2D materials in addition to flexibility and transparency have made these materials potentially attractive candidates for developing information storage devices. In this section, a brief overview of the applications on the 2D materials such as graphene composites/heterostructures, TMDCs, and h‐BN for NVM is presented.

10.5.1 Nonvolatile Resistive Memories Based on Graphene and Its Derivatives

Resistive memories store digital information by switching the resistance of material during its operation [112]. A resistive switching (RS) device comprises a dielectric layer (typically made of binary oxides, etc.) that is sandwiched between two metal contacts. The biasing condition may change the device conduction state from high resistive to low resistive state [61, 107]. By applying a reverse potential, an opposite transition in the device conduction state can be achieved (generally referred to as bipolar RS devices). The fabrication and early demonstration of graphene‐based NVM were reported by Standley et al. [113]. The graphene sheets were subjected to electrical breakdown for creating nanoscale gaps, to bypass the need of any lithography tools usually required for metallic wires. By applying suitable potential pulses, the conductance states of the atomic gap can also be tuned between low and high states, and the device persistently retains this reliable and repeatable behavior for over several thousand of cycles. The reported high resistance to low resistance states ratio was ∼100 with the device switching speed of ∼100 µs. Tour and coworkers reported significant device performance improvement based on nanosized irregular graphite strips with controllable dimensions [114]. The memory device demonstrated high ON/OFF ratios (high resistance to low resistance ratios) of the order ∼107, switchable at 3–4 V, and with a switching speed of ∼1 µs.

The working mechanism for most of the graphene‐based memories is based on redox reactions (changes between sp2 and sp3 carbon), induced by the imposed electric field within the 2D sheets structures [115]. This stimulated investigations were performed on graphene oxide (GO), which usually considered as insulating material [116, 117] and reduced graphene oxides (rGOs, being relatively conducting) [118, 119] for nonvolatile RS memories. One of the early examples of GO adoption as a switching medium for flexible RS memories was reported by Jeong et al. [120]. The GO layer was sandwiched between two aluminum electrodes and an insulating layer of AlOx was identified to form in between top Al electrode and GO interface that acted as a reservoir for oxygen ions to trigger the switching phenomenon in the devices. X‐ray photoelectron spectroscopy (XPS) analysis also confirmed the partial oxidation of Al to Al3+ and reduction of GO layer at the interface, thus the microscopic origin of switching behavior was attributed to the formation and annihilation of conducting filaments originated at the amorphous AlOx‐interfacial layer between GO and top Al metal contact.

Various strategies have been opted to improve the performance of resistive memories based on graphene or its derivatives. For instance, by treating GO‐based RRAM with mild hydrogen plasma, the enhanced performance was achieved in terms of reduced threshold operating potential and higher ON/OFF ratios [121]. According to XPS measurements, mild plasma‐reduced GO is formed by OH− radicals on the basal planes and edges of the graphitic network, which lowers the insulating interfacial barrier at the metal/GO interface. This reduced interfacial barrier height improves the charge transportation and thus effectively reduced the threshold potential to trigger the RS in GO‐based RRAM devices. In another work, Zhuang et al. reported an exceptional RS performance in conjugated polymer‐modified GO layer [122]. The polymer used in this study was comprised of soluble triphenylamine‐based polyazomethine (TPAPAM) covalently jointed to GO. The RS device showed bipolar and nonvolatile memory behavior. The threshold potential was recorded as low as −1 V with an ON/OFF ratio greater than 103.

In another work, the random formation and annihilation of conducting filaments in Zr0.5Hf0.5O2 (ZHO) films were controlled by inserting a sandwiched layer of graphene oxide quantum dots (GOQDs) in the Ag/ZHO/GOQDs/ZHO/Pt stacked device [123]. The device performance was compared with a control device without having a sandwiched GOQDs layer. The quantum dots (QDs) sandwiched device expressed superior performance in terms of lower operating potentials, a uniform set and reset voltage distribution, fast switching response, and better retention capabilities than the control device. The QDs layer was presented as a supportive medium to facilitate the directional growth of conducting filaments and their annihilation to express excellent switching uniformity. Moreover, the presence of QDs facilitates the migration of Ag ions by shorting the effective distance between electrode and electrolyte that enhanced the local electric field, which in turn lowered the device threshold potentials as compared with the control device.

To further extend the effectiveness of GOQDs in the memristive characteristics, the bottom electrode modulation was adopted to expand its potential for up to neuromorphic devices [124]. The bottom platinum (Pt) electrode (used in previous work) was replaced with a reactive Ag electrode in the sandwiched device structure of Ag/Zr0.5Hf0.5O2GOQDs/Ag. First, by replacing Pt by Ag, the bipolar digital RS behavior was changed to analog behavior in which bidirectional progressive conductance tuning was observed. Additionally, the adjustments of applied potential pulses (by varying pulse numbers, amplitude, and duration) resulted in fine‐tuning of device conductance states. It was observed that a 30 ns long voltage pulse with an amplitude of 0.6 V is enough to modulate device conductance linearly. Finally, the coexistence of intrinsic (tunneling) and extrinsic effects (metal electrode dissolution) was identified as key moderators for regulating conductance for GOQDs‐based sandwiched memory device.

The implications of graphene and its derivatives are also used as electrode materials to tune the RS features. For instance, Jang et al. [125] reported flexible perovskites‐based resistive memory using multilayered graphene as the bottom layer. Asymmetric bipolar RS characteristics were observed with threshold potentials of 0.6 and −0.5 V. Furthermore, the device expressed excellent flexibility tolerance with over 1000 bending tests. In another work, Ott et al. [126] used single‐layer graphene as a top electrode material and obtained very high ON/OFF ratios with low power density. Moreover, their device expressed multilevel RS characteristics, which were absent in the devices with metallic electrodes. In a similar attempt, metallic electrodes were replaced by graphene electrodes in an Al2O3‐based RS device and the device threshold potentials and power losses were found to be significantly reduced [127]. Thus, graphene‐based electrodes are quite effective in regulating RS performance of the devices by providing an additional feature of transparent electrodes.

10.5.2 Resistive Switching Memories in 2D Materials “Beyond” Graphene

In addition to graphene and its derivatives, several other 2D materials have been explored for the applications of nonvolatile RS memories. These materials have a great potential to offer unique properties such as bandgap regulation, mobility modifications, and tunable oxidation states with surface chemistry effects. Such characteristics have made these materials excellent candidates for next‐generation NVM [128].

10.5.2.1 Solution‐Processed MoS2‐Based Resistive Memories

One of the earlier reports on the use of MoS2 mixed with polyvinylpyrrolidone (PVP) polymer as a RS layer was provided by Zhang's group [129]. The mechanically flexible RS device was comprised of ethanol dispersion of MoS2‐PVP film sandwiched between rGO and Al electrodes. Although the device performance was not exceptionally high in terms of ON/OFF ratio and is equivalent to ∼102 operated at threshold potentials of ∼±5 V. However, this report paves the path for further developments of such layered materials for memory applications. Another effort to achieve high‐performing MoS2‐based RS memory was reported by Bessonov et al [130]. A simple solution‐processed, fast, flexible, cost‐effective, and printable way to fabricate memory device were unique features of the reported device. Moreover, the device exhibited an unprecedentedly large (∼106, higher than other graphene and MoS2‐based memories) and tunable electrical resistance with ultralow operating potential of (±0.2 V).

Recently, the implications of MoS2 as an artificial synaptic device and for neuromorphic computing (analog memory) were also been explored by several groups. For instance, Li et al. [131] investigated the switching characteristics of mechanically printed a few layers thick (lateral/planar structured) MoS2‐based memory device. Their device exhibited two unique RS features (analog and quasi binary switching), which were highly dependent on programming sequences. By imposing time sequentially programmed pulses, an analog switching behavior was observed, whereas an abrupt/digital/quasi binary switching behavior was noted by imposing electrical stress pulse sequences. Such a transition in device switching behavior was attributed to electric‐field‐mediated agglomeration of ionic vacancies at electrode/electrolyte interface. In another report, Chen et al. [132] investigated the programmable plasticity behavior in MoS2‐based memristors, which is extremely important in neuromorphic computing. The investigated device successfully imitated long‐term plasticity (LTP) and short‐term plasticity (STP) behavior, which is analogous to the neural network of the human brain. Thus, resistive memories derived from MoS2 have great potential for digital and analog computing devices.

10.5.2.2 Solution‐Processed Black Phosphorous Nonvolatile Resistive Memories

BP is an emerging 2D material that possesses unique electronic properties, natural direct bandgap, and broad light absorption [133]. In particular, these materials gained enormous attention for their applications as NVM after their successful demonstration as FETs in 2014 [134]. A systematic and comprehensive investigation on BP‐based RRAM cells was reported by Han et al. [135] in which self‐assembled black phosphorus quantum dots (BPQDs) were used as an active RS layer. The BPQDs were sandwiched between two polymers layer and deposited on a flexible substrate intending to fabricate flexible memory device. The BP‐based RS device has exhibited extremely large ON/OFF ratio of 3.0 × 107, which is considered as one of the highest resistance ratios recorded for 2D materials‐based resistive memories so far. Moreover, the set potential and conductance states of the device were finely tuned by regulating BPQDs trap densities in conjunction with in situ control of data storage levels through current compliance modulations.

Recently, excellent memory performance with low leakage current has been reported in a memristive device comprising BP and self‐assembled phosphorous oxide [136]. The device expressed very high ON/OFF ratio higher than 107, data retention for more than 104 seconds with greater reliability, and showed promising potential for the flexible and wearable memory device. In yet another work, light illumination has been exploited to tune the memristive characteristics of BP‐based transparent devices [137]. BP nanosheets coated with polystyrene were used as transparent switching medium, which was sandwiched between two indium tin‐oxide electrodes to form a transparent memory device. The RS responses in the absence and presence of light (ranging from ultraviolet to near‐infrared regimes) were recorded. Light irradiation was found to alleviate the Schottky barrier heights, which lowered the threshold reset potentials and power consumption level for device operations. Single crystal of BP flakes passivated by hafnium oxide was also used as a RS layer [138]. The device demonstrated decent RS performance with a switching ratio of 102 for over 100 cycles.

10.5.2.3 Emerging NVM Based on Hexagonal Boron Nitride (h‐BN)

One of the earliest reports on the RS behavior in ultrathin films of chemical vapor deposited h‐BN was presented by Qian et al. [139]. The device was comprised of a simple sandwiched structure in which h‐BN was immersed between two Ag and Cu foil coated on a polyethylene terephthalate (PET) substrate. The resistive memory showed good behavior with ON/OFF ratio ∼102 with endurance and data retention of ∼550 cycles in ∼103 seconds, respectively. Furthermore, the mechanical flexibility of such devices was confirmed by demonstrating ∼750 bending endurance cycles. Recently, large‐area and high‐quality multilayers of h‐BN were reported as an effective RS medium by Lin et al. [140]. The investigated device exhibited excellent performance by showing low cycle‐to‐cycle variability and low operating potentials with high ON/OFF ratios. The smooth surface of h‐BN films with fewer grain boundaries was attributed as the main cause of enhanced device performance.

In another work, Banerjee and coworkers demonstrated multilayer h‐BN films fabrication on copper foils by the CVD method and then, using a transfer method, RS memory device with Ti/h‐BN/Au structure was fabricated [141]. The device demonstrated a very stable nonpolar RS behavior with over 103 manual switching cycles with an ON/OFF ratio over 5 orders of magnitude. The underlying switching mechanism was investigated by analyzing the reset process and they found that the filaments annihilation process was attributed to the joule heating effect.

Usually, for typical growth of h‐BN, CVD and molecular beam epitaxy (MBE) approaches are generally used, which requires an independent metallic substrate to sustain a very high film growth temperature (>850 °C). Thereafter, these devices are built by subsequent transferring of h‐BN sheets onto wafers. Such high temperature may damage the substrates due to the diffusion and de‐wetting process; thus, approaches that rely on direct growth of h‐BN on wafers are highly desirable. Recently Jing et al. have reported a transfer‐free strategy to directly grow h‐BN film on a metal‐coated substrate using a standard CVD system [142]. The direct growth of h‐BN has been realized by using a simple strategy of placing a SiO2/Si wafer on top of metal‐coated SiO2/Si wafer (substrate) to grow h‐BN film on bottom metallic coating layer (Ni). The upper SiO2/Si wafer assembly was found to block the surface of the Ni layer and restrict the amount of gas interacting to the surface of Ni to avoid severe diffusion and de‐wetting. Furthermore, they have also investigated the memory behavior of the h‐BN films, which showed a forming free RS behavior with operating potentials in the range of ∼±1 V. The RS mechanism in the underlying h‐BN film was attributed to the formation of a defective layer at the top electrode and h‐BN interface to form percolation paths across h‐BN stack layer.

10.6 Conclusions and Outlook

In this chapter, we briefly reviewed recent development and progress of emerging two‐dimensional materials in electronic devices, particularly in FETs and nonvolatile resistive memories. The in‐depth analysis of 2D materials revealed that these materials are excellent candidates for developing future electronic devices. However, it is too early to state that the 2D semiconducting materials will replace Si shortly without developing some basic electronics techniques. Moreover, there are yet many challenges to be overawed, open questions to answer, and many applications of 2D semiconducting materials to explore.

For transistor applications, the research on 2D materials is mainly focusing on achieving high mobility, which is usually considered as a key transistor performance evaluating parameter. However, parameters such as controlling the switching speed of FET transistor through gate potential modulation are more relevant to address the challenges in transistor research. On the other hand, the contact resistance should be reduced to ∼100 Ω‐µm to boost the device performance. In general, the stable and controllable doping in 2D materials is a challenging task that should be investigated to improve our understanding for developing n‐type/p‐type semiconducting FET devices.

Numerous 2D materials have been explored for nonvolatile resistive memories with the following aims: (i) to prove the concept of their suitability in NVM, (ii) to improve device performance, and (iii) to present added features of transparency, flexibility, and chemical stability for NVM applications. Despite tremendous progress, the main challenge of these materials is their direct integration with traditional dielectrics, as well as their compatibility with Si during the transfer process without compromising their inherent characteristics. For instance, graphene and h‐BN have been successfully grown on dielectric/metal surfaces, but it is still challenging to control their roughness, thickness, grain sizes, and orientation, which are fundamental requirements for an NVM cell.

Nevertheless, considering the performance of traditional transition metal oxides–based devices achieved over several decades, the 2D‐materials‐based electronic devices demonstrated a close level of performance in less than a decade of research. Though, we are in early stages of developing 2D material electronics, the future of 2D electronics cannot be underestimated, and by building strong collaboration between industrial and academic research, these objectives can be timely achieved.

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