Index

ACMs, 125, 126, 194

Aggressor, 154, 161, 180

Al-Ghazali, 2

Arbiter

busy ring, 231, 232, 234, 237

cascaded, 227, 228, 229

clocked, 199

daisy-chain, 203, 238

definition, 200

distributed, 203

dynamic priority, 235, 241, 247, 248

four-phase, 218

lazy ring, 232, 233

multiway, 58, 204, 224, 225, 227, 230

ordered, 238

priority, 235

RGD, 211, 212, 214, 221, 228, 229, 230

ring, 203, 230

static priority, 241

sync-based, 222, 223

synopsis, 201

tree, 176, 203, 227, 229, 230, 250

two-phase, 214, 217

two-way, 204, 209, 211, 223, 227

Asynchronous reset, 135

Avoiding conflicts, 114

Back edge, 9, 34, 36, 47, 95, 96, 101, 107, 135

Balance point, 23, 33, 35, 37, 59, 65, 66, 81, 84, 85, 86, 87, 88, 89, 93, 102, 140, 141

Baseline shift, 154

Basic MUTEX, 50

Bisection, 73, 74

Bit period, 155, 156, 157, 159, 161, 162

Bit rate, 172, 173, 179

Buridan, 2

Bus links, 145

Cgate, 184, 185, 186, 187, 192

Canonical structure of arbiters, 240

Channel, 126

Characteristic impedance, 160

Clock generators, 184

Clock recovery, 156, 159

Clock tree, 116, 150, 189, 190

Common mode noise, 160

Conflict detection, 114, 115, 200

Constant, 126

Cross-talk, 116, 153, 161, 164, 172, 180

Deep metastability, 9, 47, 83, 92, 93, 102

Delay insensitive, 157

Delay locked loop, 84, 89, 102

Differential link, 160

Digital oscilloscope, 21, 77, 83, 86

Disturbing metastability, 136

Dual rail, 241, 242

Dual-Rail, 157

Error function, 60

Event histogram, 78

Fairness, 201, 202, 203, 229, 238

FIFO, 107, 108, 109, 110, 115, 190, 191, 192, 194, 230

Flow control, 105, 108, 113, 115, 127, 181

Four slot mechanism, 131

Four-phase, 186, 187, 191, 210, 211, 212, 214, 215, 216, 219, 221, 222, 223, 227, 239

FPGA, 26, 51

GALS, 10, 183, 184, 191, 194

GALS wrapper, 191

Handshake, 10, 190, 191, 192, 200, 213, 219, 222, 232

Heterochronous, 9

Input port, 191, 192

Input time constant, 25

Input time distribution, 90, 91

Interconnect rise time, 151

Internal noise, 5, 50

Jamb latch, 9, 42, 43, 45, 46, 47, 48, 49, 53, 59, 61

Jitter, 60, 67, 115, 116, 142

Late transient detector, 78, 79, 80, 81, 102

Latency, 9, 106, 107, 109, 112, 115, 119, 120, 125, 139, 143, 190, 193, 194, 226, 229, 250, 253

LEDR, 158, 159, 161, 181

Level Encoded Dual Rail, 158

Level triggered latch, 34

Line driver, 160

Locally delayed latching, 116

Malicious input, 65, 67, 102

Manchester Code, 156

Master slave flip-flop, 14, 32, 38, 46

Merge block, 165, 166

Mesochronous, 8, 110, 113, 193

Metastability blocker, 138

Metastability filter, 40, 41, 49, 54

Metastability window T_w, 9, 25, 34, 35

Metastable events, 9, 19, 23, 26, 32, 79, 82, 83, 84, 123, 141

MTBF, 9, 25, 29, 37, 53, 66, 67, 83, 101, 106, 107, 122, 123

Multistable flip-flops, 55

Multi-way MUTEX, 211, 225, 227, 230

N out of m, 169

Network on chip, 145, 147, 164, 194

Node A, 43, 44, 45, 137

Node B, 43, 45, 46, 79

Non Return to Zero, 155

Non-deterministic, 59, 84, 200, 214

Non-return-to-zero, 210

NRZ, 155, 156, 159, 161, 167, 194, 210, 223, 224, 227, 228, 229, 230

NRZI, 155, 159, 161

Numerical integration, 73

One hot, 162, 167, 168

One of four, 162, 166, 167, 168

One-hot, 253

Oscillation, 26, 51

Output port, 192, 235

Output time, 4, 5, 9, 22, 27, 30, 36, 38, 45, 46, 59, 87, 88, 93, 95

Packet, 146, 164, 169, 171, 172, 199

Parallel serial, 181

Pausible clock, 183, 185, 187, 191

Petri nets, 10, 200, 203, 204, 205, 225, 253

Phase encoding, 156, 170, 171, 172, 173, 174

Plesiochronous, 9, 113, 193

Point to point links, 144

Pool, 126

Power supply variation, 52

Priority discipline, 203, 235, 248, 253

Process variation, 97, 161

Q-flop, 9, 49, 101, 121, 122, 123, 124

Recovery from failures, 119

Rent's Rule, 144

Resolution time constant, 9, 26, 39

Return to Zero, 155

Robust synchronizer, 52

Routing nodes, 146

Select block, 166

Serial link, 155, 157, 159, 180, 181

Signal Transition Graph, 205

Simulation, 44, 46, 47, 69, 70, 71, 72, 73, 95, 134

Skew, 162, 181

Small signal model, 22

Spacer, 157, 162, 163, 169, 170, 177, 239, 241, 249

Speed-independent, 10, 219, 225, 241, 247, 248, 253

Stoppable clocks, 183, 184

Symbol-dependent matrix, 173

Synchronizer

data, 139

edge triggered, 14

FIFO, 108

low latency, 9, 116, 193

multiple flop, 139

pipelined, 107

predictive, 113

redundant, 140

robust, 52, 54, 55

selection, 99

speculative, 120, 121, 123, 124

System on silicon, 143

TDC, 178

Three slot mechanism, 129

Throughput, 9, 31, 105, 106, 108, 109, 193, 230

Time encoding, 177

Time shift, 90, 141

Time to digital converter, 178

Transconductance, 43, 54, 58

Transient errors, 170

Transitions per bit, 155, 156, 157, 159, 168, 169, 170, 171, 178

Tristable flip-flop, 56

Two oscillator method, 83, 102

Two-phase, 191, 207, 210, 211, 212, 216, 221, 223, 227

Two-way MUTEX, 212, 224, 225, 227

Unsynchronized paths, 134

Victim, 154, 161

Wire area, 144, 147, 148, 149, 194

Workshop on Synchronizer failures, 5