14.3.1 High Mobility Channel Transistor

First, in order to attain higher I_on at constant I_off at lower V_dd, the mobility improvement of channel material is certainly necessary. The characteristics of a high mobility channel transistor are schematically shown in Figure 14.5a, comparing with a conventional silicon channel bulk transistor. Thanks to high mobility, a higher I_on can be obtained with a given overdrive voltage, or the same I_on can be obtained with reduced overdrive voltage, than with a conventional device.

Generally, III-V compound semiconductors, including GaAs, InP, InAs, InSb, and their ternary or quaternary alloy semiconductors, have much higher electron mobility than silicon, and they are promising materials for n-type FETs. On the other hand, Ge and SiGe have higher hole mobility than silicon and they are attractive for p-type FETs. High mobility transistors using III-V or Ge have been widely studied, and the integration of III-V nFETs and Ge pFETs in a chip has been also achieved at research level [4], as shown in Figure 14.6. Moreover, a Ge nFET, which has higher electron mobility than silicon, and a III-V pFET, whose hole mobility is enhanced by strain, are also being studied.

14.3.2 Multi-gate Transistor

Second, in order to attain lower V_th at constant I_off, the steep subthreshold slope is necessary. The subthreshold properties are generally characterized by the subthreshold gate voltage swing to achieve 10× drain current change (Subthreshold swing, SS). It is well known that the minimum SS is kT/q as long as the operation principle is based on conventional FET, where k is the Boltzmann constant, T the temperature, and q the elementary charge. The minimum SS at room temperature is 60 mV/dec. In conventional bulk transistors, the SS is degraded due to the short channel effect and the typical value of SS is approximately 100 mV/dec. The ideal subthreshold characteristics with SS = 60 mV/dec are schematically shown in Figure 14.5b, compared with conventional single-gate bulk transistors. A higher I_on can be obtained with a given I_off and V_dd, or the same I_on can be obtained with a reduced V_dd, than with conventional devices.

The subthreshold characteristics close to the ideal SS can be obtained by better electrostatic control by gate electrode, which can be achieved by changing the transistor structure. Figure 14.7 shows the evolution of transistor structure from single-gate structure to three-dimensional (3D) multi-gate structures. The FinFET is one of the double-gate structures. In a tri-gate transistor, three surfaces of the channel are surrounded by the gate electrodes. The ideal structure in terms of the electrostatic control by gate is the gate all around (GAA) nanowire structure [5].

The tri-gate transistor has been in production, where the short channel effect is well suppressed and SS of approximately 70 mV/dec has been attained in transistors with L_g as small as 30 nm [6], as shown in Figure 14.8. The data for a tri-gate transistor in the year 2011are also plotted in Figures 14.1–14.4. Thanks to better SS, V_dd can be reduced to 0.8 V, leading to an improvement of the energy, as shown in Figure 14.1b.

14.3.3 Intrinsic Channel Transistor

Third, in order to suppress the characteristic variability, intrinsic channel transistors should be realized. One of the main obstacles that prevent further device scaling and V_dd lowering is the random variability of transistor characteristics, which is not represented in Figures 14.1–14.4. It is known that the main origin of random variability in conventional bulk transistors is random dopant fluctuation (RDF) [7]. Since the number and the position of dopant atoms in the transistor channel are randomly distributed, V_th of each transistor also varies randomly. It is experimentally confirmed that V_th of bulk transistor follows a normal distribution up to ±5σ [8].

The only way to suppress the variability due to RDF is to eliminate dopant atoms from the transistor channel, which is impossible in conventional bulk planar transistors because a heavily doped channel is necessary to suppress the short channel effect. The intrinsic channel or very lightly doped channel, whose channel is fully depleted (FD), can be realized using a silicon on insulator (SOI) transistor or a 3D multi-gate transistor, where the short channel effect is well suppressed not by a heavily doped channel but by better gate electrostatic control.

Figure 14.9 compares measured characteristics variability in 1 k bulk transistors and 1 k intrinsic channel FD SOI transistors fabricated using 65 nm technology [9]. Compared to bulk transistors, the intrinsic channel FD SOI transistors have much smaller random Vth variability. On-current (I_on) variability at V_gs = V_ds = 1.2 V is also suppressed in the intrinsic channel transistors. The intrinsic channel is a very effective way to suppress random variability.

However, intrinsic channel transistors still have random variability, which may be caused by other origins than RDF, including random variations of gate work function. As the transistor size shrinks and the integration level increases, the variability problem becomes more severe. Any possible origins of variability should be strictly suppressed in nanometer and giga-scale transistors.

The variability problem will also arise in any of the new types of devices that will be introduced in the following sections. The origins of variability in devices with new operation principles may be different from conventional FETs. The variability problem should be primarily considered in the exploration of new types of devices for VLSI applications.

14.4.1 Energy Efficiency

Before discussing new types of devices as long-term solutions, the energy efficiency of CMOS logic circuits are reconsidered in this subsection. Figure 14.10 shows calculated delay, power, and energy of a CMOS logic circuit [10] as a function of V_dd, where parameters of the 65 nm technology generation are assumed, both active and static power dissipations are considered, and the energy is defined as the product of power and delay. As V_dd is reduced, the delay increases, while the power dissipation dramatically decreases. Here, we should pay attention to the energy, which has the optimum (minimum) value (E_opt) at a certain V_dd. The energy decreases as V_dd decreases due to the reduction of active energy, while the energy increases as V_dd is further reduced due to the increase in the static energy. V_opt is defined as V_dd at which the energy becomes optimum. Since the operation at V_opt can achieve the most energy efficiency, V_opt is the target supply voltage for ultra-low power and energy efficient applications [10].

Figure 14.11 shows energy versus V_dd assuming various subthreshold swings (SS). In the calculation, I_off at V_ds = V_dd is fixed. It should be noted that the energy dissipation strongly depends on SS, and both E_opt and V_opt drastically decreases as SS decreases. The ideal ultra-low energy circuits cannot be achieved by conventional CMOS devices whose SS is more than 60 mV/dec. This is a strong motivation for the invention of new types of FETs that have steeper subthreshold swing less than 60 mV/dec.

14.4.2 Impact-ionization MOS

One of the early attempts to pursue steep subthreshold device was impact-ionization MOS (I-MOS) [12]. The I-MOS is in the form of a gated p-i-n structure and uses a gain mechanism caused by the modulation of impact-ionization related breakdown voltage. Since the impact-ionization is an abrupt function of the electric field, the device has a subthreshold slope much lower than kT/q.

Figure 14.12a shows a schematic n-channel device structure [12]. The main differences between I-MOS and a conventional n-channel MOSFET are an n-type source and an offset between source and gate in I-MOS. Figure 14.12b shows experimental I-V characteristics of silicon-based p-channel I-MOS [12]. Extremely steep subthreshold swing (∼10 mV/dec) is achieved. One of the drawbacks of I-MOS is that the device inherently requires high drain voltage to give rise to the breakdown. The channel material should have a narrow bandgap to realize low voltage operation. Another concern of I-MOS is the delay associated with positive feedback that is intrinsic to impact ionization phenomena.

14.4.3 Tunnel FET

One of the most promising and most actively researched steep SS devices is the tunnel FET (TFET). TFETs make use of tunneling current instead of diffusion to avoid the limitation by kT/q in the subthreshold region. Figure 14.13 shows a schematic device structure and band diagram of an n-channel TFET that consists of p+ source, n+ drain, and gate [13]. When the gate voltage is 0 V, the channel is fully depleted and the device is in the OFF state (Figure 14.13b). When the positive gate voltage is applied, the device turns on by the Zener tunneling (Figure 14.13c). Since the Fermi tail is cutoff by the bandgap the subthreshold swing is not limited to kT/q and the off-current can be significantly below that of the conventional MOSFET [13]. Detailed operation principles of TFETs are found in review papers [13,14].

TFETs have been fabricated and a sub-60 mV/dec subthreshold slope has been observed in various channel materials including Si, Ge, and III-V semiconductors. Figure 14.14a shows an example of a silicon TFET [15]. The minimum SS of 36 mV/dec is obtained, although this small SS is achieved in only narrow Ids range (approximately one order) and at very small I_ds (I_ds ∼ 1 pA/μm). The average SS in three orders of magnitude of I_ds is 81 mV/dec, that is larger than the ideal SS in conventional MOSFETs.

Figure 14.14b shows another example of a TFET composed of heterojunction InGaAs, compared with a thin body InGaAs MOSFET at matched I_off = 200 pA, L_g = 150 nm, EOT = 1.15 nm, and V_ds = 0.3 V [16]. SS of the InGaAs TFET is smaller than 60 mV/dec in the range from 3 × 10⁻¹⁰ to 3 × 10⁻⁹ A. Due to the steeper SS, the InGaAs TFET shows gain over the InGaAs MOSFET at low overdrive, but Ion is much smaller at V_gs – V_th ∼ 0.6 V. The smaller I_on is a significant disadvantage of TFETs.

Figure 14.15a shows an example of sub-60 mV/dec characteristics of an InAs/Si heterojunction p-channel TFET [17]. Excellent SS of 21 mV/dec is achieved in a wide I_d range of four orders of magnitude. The on/off ratio reaches approximately 10⁶. However, this InAs/Si heterojunction p-channel TFET has another disadvantage. Figure 14.15b shows another example of an InAs/Si heterojunction p-channel TFET showing I-V characteristics with various drain voltage (V_ds) dependence [17]. It is found that V_th decreases as V_ds increases. In conventional MOSFETs, this phenomenon of V_ds dependence of V_th is known as drain induced barrier lowering (DIBL) and characterized by η = |ΔV_th/ΔV_ds|. Although the mechanism may be different in TFETs, some TFETs show very high η, especially heterojunction TFETs. η reaches as large as 0.74 in Figure 14.15b [17].

In order to investigate the effect of η in steep subthreshold devices, the energy dissipation is calculated at fixed SS of 30 mV/dec at various η, as shown in Figure 14.16 [11]. I_off at V_ds = V_dd is fixed in the calculation, and hence V_th increases as V_ds decreases in high η devices. As η increases, the energy as well as V_opt and E_opt increases. This is because delay increases due to increases V_th at low V_dd. This result indicated that the advantage of steep SS is offset by large η. Therefore, η (V_ds dependence of V_th) should be suppressed in steep subthreshold devices.

14.4.4 Negative Capacitance FET

SS is given by [18]

(14.1)

where V_g is the gate voltage, Ψ_s is the surface potential, C_s is the semiconductor capacitance, C_ins is the gate insulator capacitance, and I_d is the drain current. The term is the body factor and is often called the m-factor, while the term is called the n-factor. It is the n-factor that is limited by kT/q due to the carrier injection in the source. The I-MOS and tunnel FETs in the previous subsections achieve SS of less than 60 mV/dec by modifying the n-factor. If the m-factor can be less than unity, the device with less than 60 mV/dec is also achievable. The negative gate insulator capacitance makes it possible.

Figure 14.17 shows a schematic of a negative capacitance FET and equivalent gate capacitance circuit [18]. The gate stack has a thin ferroelectric layer, which can introduce a positive feedback on the charge that causes polarization and amplifies the gate voltage, resulting in an m-factor of less than unity. Figure 14.18 shows measured device characteristics at room temperature [19]. SS of less than 60 mV/dec is obtained in a wide range of drain currents.

However, the average SS obtained is not small enough and the on-current is still very low for practical use. The main challenge of the negative capacitance FET is the selection of gate stack materials that can provide much smaller average SS and higher on-current. The threshold voltage adjustments, integration of nFET and pFET, and the stability, reliability, and variability will be also critical issues.

14.4.5 MEMS Switch

Another approach to attain super steep subthreshold characteristics is to utilize a micro-electro-mechanical system (MEMS). The movement of a MEMS structure is affected by both elastic and electrostatic forces, and the structure suddenly moves when the balance between these forces is broken.

Figure 14.19 shows an example of a MOSFET with the MEMS structure. The device has a movable gate electrode that is fabricated by MEMS technology and suspended above the channel [20]. When the gate voltage (V_gs) is 0 V, the gate is located far above the gate and is not in contact with the gate oxide. Then, the inversion layer is not formed in the channel and hence, the device is in the OFF state (Figure 14.19a). When V_gs increases, a downward electrostatic force applied to the movable gate increases, and the movable gate is suddenly pulled down to the gate oxide at a certain voltage of V_gs, as shown in Figure 14.19b. This voltage is called the “pull-in” voltage (V_pull-in).

Figure 14.20 shows measured I-V characteristics of a MOSFET with a movable gate [20]. In this specific device, an additional lower gate electrode is formed in the vicinity of the channel to control V_pull-in of the device. When V_gs increases, drain current rapidly increases at a certain V_gs. This voltage is V_pull-in and the subthreshold slope is very steep. By changing the lower gate voltage (V_low), V_pull-in is successfully controlled. The minimum value of SS is approximately 2 mV/dec.

The drawback of the MOSFET with a movable gate is the leakage current from drain to source that is inevitable to the MOSFET structure. In order to completely shut down the leakage current, another type of MEMS switch has been also proposed and demonstrated [21,22]. Figure 14.21 shows schematics of a MEMS relay switch with zero standby power [22]. In this structure, the source and drain are suspended and its position is controlled by the gate. Since the source and drain are completely separated mechanically in the OFF state, no leakage current flows. At V_gs = 0 V, the source electrode is located above and the device is at the OFF state. At a certain voltage of V_gs, the “pull-in” takes place and the drain current suddenly increases with a very steep subthreshold slope. Figure 14.22 shows a circuit composed of MEMS relay switches [21]. An inverter operation as well as NAND and NOR operations have been successfully demonstrated.

14.4.6 Mott Transistor

It is well known that the abrupt resistance change by several orders of magnitude can be observed in the Mott metal–insulator transition. Mott field-effect transistor utilizes the electric field induced metal–insulator transition [23], in which the channel material shows both a metallic state and an insulating state controlled by the gate electrode. The Mott transistor could have a structure similar to conventional MOSFETs: the channel is composed of a correlated electron material, instead of semiconductor. Figure 14.23 shows schematics of the Mott metal-insulator transition and Mott transistor structure, where the channel material is VO₂ [24]. The insulating/metallic states of the channel are controlled by the gate electric field. The sharp channel resistance change by the gate voltage has been successfully demonstrated. Figure 14.24 shows measured data of a Mott transistor composed of VO₂ [24]. At low temperature, a large channel resistance change by a small change of gate voltage is observed.

Research on the Mott transistors is at a very early stage. The main challenges of the Mott transistors include a basic understanding of fundamental switching mechanisms, channel material selection, operating temperature, and stable transistor operation without hysteresis.

14.4.7 Bilayer Pseudo-spin Field-effect Transistor

In order to achieve ultimately energy-efficient information processing, a steep transition between the on state and off state in the 10 mV regime is necessary. BiSFET, bilayer pseudo-spin field-effect transistor, was recently proposed to enable the on/off transition at ultra-low voltage [25]. Figure 14.25a shows a schematic of the BiSFET structure that consists of an n-type and p-type graphene layer pair in close proximity, separated by a thin dielectric tunnel barrier. Both n-type and p-type grapheme layers have large and nearly equal carrier densities. Here, both electrons and holes are Fermions. However, under certain conditions, electrons in the n-type layer can pair with holes in the p-type layer, resulting in electron hole pairs/excitons which then condense even at room temperature in the case of the grapheme bilayer. Then, these are Bosons. This Bose–Einstein condensation alters the quantum wavefunctions in the bilayer qualitatively, resulting in a drastic reduction of the tunnel resistance between two layers for only a small interlayer bias. With a large bias, the condensation is destroyed leading to large resistance.

The device is called BiSFET because electron occupation of the top layer or bottom layer can be treated much like spin up or down, that is as a pseudospin, and the collective effects considered here are analogous to collective spin effects in a ferromagnet.

Figure 14.25b shows the circuit model and Figure 14.25c shows modeled current as a function of voltage between two grapheme layers of BiSFET [25]. A current peak appears in the I-V characteristics and then the current decreases at higher drain bias. Since the current change takes place at very low voltage (∼10 mV), very low voltage and low power operation may be possible. The simulations have shown that the energy consumption per clock cycle per BiSFET is 0.008 aJ at 100 GHz [25], while according to ITRS prediction MOSFET will consume 5 aJ per switching at 100 GHz in 2020 [1].

However, BiSFET is only a novel device concept. The main challenges include the fabrication of a perfect grapheme bilayer, a perfect gate stack with double gate structure, and an improved theory of the condensation.