13.3.1 Electrochemical Metallization Bridge

Electrochemical metallization bridge (EMB) memory is also referred to as conducting bridge RAM (CBRAM) and programmable metallization cell (PMC) technology. A key attribute of EMB memory is that Switching is based on the motion of cations. An EMB type ReRAM consists of an asymmetric metal/insulator/metal structure with a reactive electrode composed of either Ag or Cu (see Figure 13.2). The inert electrode is chosen such that it will not strongly react with the insulator; typical choices are Pt, Ni, Au, and W. The insulator is often a solid electrolyte such as GeSe, GeS, a binary oxide, or a Cu-doped binary oxide (which are mixed conductors) [13]. A comprehensive table of EMB insulators is provided in Reference [14].

EMB switching is typically bipolar, and hence requires an electric field. Unipolar operation is also possible, but requires higher current and energy and is therefore uncommon [15,16]. Prior to the commencement of switching, an electroforming process is required to create an initial filament. Switching occurs based on the formation and dissolution of an Ag or Cu filament under an electric field. The filament oxides are formed based on the oxidation reaction (using Ag as an example) [13]:

(13.1)

The SET process occurs as the cations oxidize under the electric field and deposit on the inert electrode where they are reduced and form a filament. The RESET process involves dissolution of the filament initiated by high Joule heating at the thinnest portion of the filament, re-oxidizing the Ag. Then, electrochemical motion of the Ag⁺ cations causes the filament to disperse into the insulator, returning the structure to a high resistance state. The specific details of the process are still the subject of some debate, and are comprehensively reviewed in References [13,14,17].

EMB ReRAM technology has achieved significant performance metrics. Endurance as high as 10¹⁰ with little degradation was demonstrated in GeSe cells (projected to well beyond 10¹¹ cycles) [18]. High temperature retention due to random diffusion of Ag or Cu atoms in the insulator has historically been considered a moderate weakness for EMB ReRAM. However, recent results show excellent retention, with states holding after 1000 h at 200 °C [19]. Scalability to dimensions of 20 nm has been demonstrated for a GeSe EMB cell [20]. A recent experiment demonstrating quantized conductance corresponding to the conductivity of a filament formed from a single chain of Ag atoms showed that scaling to atomic dimensions is possible [21].

Significant progress has been made in the development of EMB ReRAM macros and low density commercial products – which are important to foster advancement of an emerging technology [11]. In 2012, a 1 Mbit integrated EEPROM replacement chip with 0.18 μm technology was released [15]. Recently, a very low power prototype chip which switches at 600 mV and achieves a 1 pJ SET and 8 pJ RESET energy was demonstrated [22]. Also, a W/Al₂O₃/Ti/CuTe-based EMB cell realizing subnanosecond SET and RESET times was reported [16].

A fundamental research challenge of EMB is the understanding of subtle details of the switching process. Recent research in this area has elucidated many of the details of the switching physics, but the scientific community lacks complete agreement on the exact nature of the filament formation and dissolution process details. Another key research challenge for EMB ReRAM (and other filament-based ReRAM technologies) is random telegraph noise (RTN) [11]. This effect manifests itself as a variation in read current, especially in the high resistance state where the fluctuation of small numbers of atoms in the filament may vary to cause conductivity changes [23]. EMB ReRAM cells often employ a solid electrolyte switching layer (e.g., GeSe), which are not easy to integrate with a CMOS back end of line (BEOL) process and may be damaged by high temperatures. For this reason, commercial EMB products are generally integrated during later steps of the BOEL process, whereas it may be desirable for maximum performance to integrate the cell before the first metallization layer.

13.3.2 Metal Oxide: Bipolar Filamentary

The metal oxide bipolar filamentary (MO-BF) category of ReRAM is an asymmetric metal/insulator/metal structure, in which switching occurs due to the change of oxygen anion concentration in a filament (see Figure 13.2). This type of memory is often referred to as Valence Change Memory (VCM) in the literature due to the change of valence states of oxygen atoms during switching [12]. The switching material is typically a transition metal oxide; recently the most common materials are HfO_x and TaO_x due to CMOS compatibility, scalability, and performance. Other common switching oxides include TiO₂, WO_x, AlO_x, as well as nitrides (AlN [24]), and oxynitrides (AlO_xN_y [25]). In addition, bilayer structures are often used with either two stoichiometries of the same oxide (e.g., Ta₂O_5−x/TaO_2−x [26]), or with a second layer composed of a different oxide intended to enhance nonlinearity and act as a select device [27]. The ohmic electrode is typically fabricated from a material with high oxygen reactivity, such as Ta, Hf, or Ti. This electrode may serve as an oxygen reservoir. The inert electrode (which may also be referred to as the active electrode), is typically formed from a material that will not react significantly with the metal oxide, such as Pt, Ir, TiN, or TaN. Switching is thought to occur in the metal oxide region directly adjacent to the interface with this inert electrode.

As with other filamentary ReRAM, prior to the resistance switching process, an electroforming step is required. In the case of MO-BF ReRAM, the electroforming step does permanent damage [17], and has similarities to a “soft breakdown” of an oxide [11,28]. “Forming free” processes have been reported [29], although it is suggested that a filament forming process still occurs at a very low current [30]. Switching most likely occurs due to a change in concentration and configuration of charged oxygen anions (O²⁻) and oxygen vacancies (V_O^··) under an applied bias. The requirement of opposite polarities for SET and RESET switching are a clear indication that an electric field is involved. However, it is also probable that Joule heating plays a significant role in switching [31]. During SET switching, anions are removed from the switching filament near the inert electrode, creating a high concentration of V_O^·· and hence, the device enters a low resistance state. RESET switching involves the return of anions to this region, which lowers the V_O^·· concentration and raises the resistance. Details of the MO-BF switching process are not fully understood or agreed on in the scientific community. Chapter 8 and several recent reviews provide a thorough explanation of the most recent understanding [12,17,32,33].

MO-BF has achieved impressive performance at the single cell level. Endurances as high as 10¹² have been reported by several groups using versions of a TaO_x-based cell [26,29,34]. Sub-nanosecond switching speeds have been reported at the cell level [35], as well as a SET switching energy of 115 fJ and RESET energy of 13 pJ (for a R_OFF/R_ON ratio of 2) [36]. At VLSI 2013, a Ta/TaO_x/TiO₂/Ti-based ReRAM array combining an endurance of 10¹² cycles and 10 pJ write energy has been demonstrated [29]. A highly scaled HfO_x cell with 100 fJ SET energy has been demonstrated (RESET currents were not given, although it was stated that the energy was comparable to the SET energy) [37]. High endurance, speed, and low energy are important factors for a M-type SCM candidate as well as a potential future DRAM replacement.

A number of recent reports indicate potential for MO-BF to 10 nm and below. In 2011, a 10 × 10 nm HfO_x cell was demonstrated with an endurance of 5 × 10⁷ cycles, 10 year retention at 100 °C (extrapolated from a 30 h bake at 200 °C), while maintaining an R_OFF/R_ON ratio >50 [37]. More recently, an ∼8 nm HfO_x ReRAM structure was demonstrated with an endurance of 10⁸ cycles, R_OFF/R_ON of 100, and 10 year retention (extrapolated from a 30 h, 150 °C bake) [38]. Using carbon nanotubes as electrodes, a 5 × 5 nm proof of concept cell AlO_x was operated, demonstrating the smallest operational ReRAM structure at the time of this writing [39].

Excellent retention has been demonstrated for MO-BF ReRAM. HfO_x cells have been reported to have a 10 year retention at 105 °C (where the temperature depends on the compliance current used during RESET), extrapolated from Arrhenius behavior evaluated from 150 to 250 °C [40]. A detailed retention study on an Ir/TaO_x/TaN cell extrapolated 10 year retention at 85 °C from 1000 h at 150 °C [41].

In the past two years, there has also been very rapid progress in prototype ReRAM products integrated with CMOS. In 2012, an 8 Mb TaO_x-based ReRAM macro with a write throughput of 443 MB/s was reported [42]. In late 2013, the first commercial MO-BF ReRAM product was announced, which will be a TaO_x-based device integrated into an eight-bit microcontroller [7]. In early 2013, a bi-layer 32 Gb prototype chip was announced, which is nearing the capacity of modern NAND flash [9]. Device structure and material details were not given in this report.

As noted above, a key scientific research challenge continues to be the development of a complete physical understanding of electroforming, switching, and degradation mechanisms in metal oxides. The most pertinent technological challenges are variability and random telegraph noise. For example, Reference [11] points out that with a 1 MB MO-BF ReRAM-based test chip, the R_OFF varies over four orders of magnitude such that it overlaps with the R_ON spread, and hence causes bit errors in the range of 1000 ppm.

13.3.3 Metal Oxide: Unipolar Filamentary

The metal oxide unipolar filamentary (MO-UF) ReRAM consists of a metal/oxide/metal structure which typically employs a binary metal oxide switching layer. The electrodes are inert materials that are not highly reactive with the oxide, such as noble metals and TiN. MO-UF ReRAM was the first major transition metal oxide-based ReRAM to be demonstrated, and was originally named OxRRAM [43]. It is also often referred to as thermochemical memory, due to the thermal dominated switching mechanism [12]. Unlike other types of ReRAM, the MO-UF structure can be symmetric, although asymmetric structures may be used to tailor device properties. The earliest integrated MO-UF-based memory utilized a NiO cell [43]; subsequent cells have utilized HfO_x, TiO_x, and CuO.

As with other filamentary oxide ReRAM, MO-UF requires a soft breakdown of the oxide to form a switching filament [43]. This filament is thought to be formed of metal oxide of a reduced oxidation (i.e., more metallic) state than the surrounding oxide. SET switching uses a current compliance (cc), which causes a thermochemical reduction to occur. RESET switching results from the rupture of this filament from a higher current pulse (without cc). An in depth discussion of thermochemical switching mechanisms is provided in Reference [44].

Several demonstrations of SET/RESET endurance up to 10⁶ cycles have been reported [43,45], as well as 10¹² read cycles [43]. Notable results have been demonstrated starting in 2009 on a MO-BF variant known as “contact ReRAM” (CRRAM) [45]. CRRAM technology has been demonstrated scalable to 35 nm [46], 60 μA RESET current [46], and SET/RESET voltages of 2.0 and 1.5 V, respectively [47]. Endurance of 10⁶ cycles and retention of 1000 h at 150 °C (400 h at 150 °C for a 35 nm cell) were demonstrated for CRRAM [45,46].

The most pertinent challenge for MO-UF ReRAM are high write currents and low relative endurances resulting from a thermochemical dominated switching process. Initial prototypes required RESET currents as high as 2 mA, although recent results are as low as 60 μA (for the unipolar W/TiO_xN_y CRRAM) [46]. This is a significant factor which limits the maximum integration density [11]. This has led research in recent years to trend toward a focus on bipolar technologies. MO-UF technology has the same variability and random telegraph noise problems associated with other filamentary ReRAMs.

13.3.4 Metal Oxide: Bipolar Nonfilamentary

Metal oxide–bipolar nonfilamentary (MO-BN) ReRAM is an asymmetric metal/oxide/metal structure, which generally utilizes a bilayer oxide switching film. The oxide layers are typically comprised of a thin insulating (often binary) metal oxide (IMO), and a conductive metal oxide (CMO), which are often perovskites [48]. A more recent MO-BN device variant using two binary oxide layers [49]. MO-BN ReRAM is unique in that conduction does not occur through a switching filament, but over the majority of the device area. This leads to a strong dependence of virgin, high, and low state resistances, and switching currents on device electrode area [48,49]. Due to the large area over which the current is spread out, thermal effects are not considered to play a major role in switching [48]. Unlike the more common filamentary ReRAM technologies, MO-BN typically does not require an electroforming step, which eliminates a source of device to device variation.

As with other types of ReRAM, the exact physics responsible for switching are not completely understood. However, as with oxide-based (anionic) ReRAM, the predominant theory of switching is based on modulation of O²⁻ concentrations under an applied bias. In the case of MO-BN ReRAM, O²⁻ concentrations are modulated through the majority of the TMO area, rather than in a localized switching filament. Modulation of the O²⁻ most likely causes a raising and lower of the Schottky barrier height at the interface. The current through the device is exponentially sensitive on this barrier height.

Data on a MO-BN device technology was presented in 2009 demonstrating typical SET/RESET voltages of ±3 V with a 1–10 μs write time and ∼10⁶ cycle endurance [48]. In 2010, a 0.13 μm, 64 Mb test chip was presented. This was the largest ReRAM prototype at that time [10].

At IEDM 2013, a new version of MO-BN technology known as vacancy modulated conductive oxide resistive RAM (VMCO-RRAM) was presented [49]. This structure consists of two binary transition metal oxides (Al₂O₃ and TiO₂) and requires electroforming, unlike earlier MO-BN technology. The VMCO-RRAM has a predicted retention of 10 years extrapolated from measurements of 168 h at 125 °C. Switching as fast as 10 ns was demonstrated with SET/RESET voltages of ∼3.5 V. A minimum SET/RESET of ±2.0 V was possible using longer program times. Scaling down to 40 nm was demonstrated, and sub-nA switching current is predicted at sub-nm scales. Endurance has not yet been reported for VMCO-RRAM.

Between 2010 and late 2013, the significant progress was not reported for MO-BM technologies due to the single most important challenge for this ReRAM category: short retention. The VCMO-RRAM shows significant progress, with an estimated retention of greater than 10 years [49]. The other early research challenge for this technology is the need to improve CMOS processes compatibility, which has also been addressed by the VCMO-RRAM. Recent progress of MO-BN technology could make this a very attractive option.

13.4.1 Ferroelectric FET

The FeFET structure integrates a ferroelectric capacitor, similar to that in a FeRAM cell, into the gate of a MOSFET. A typical FeFET structure is shown in Figure 13.3 [54]. There are several different variations of this structure; it is possible to remove one or both buffer layers, or deposit the structure on a nonsilicon substrate. It was originally demonstrated in 1974 [55], although significant research progress was not made until roughly two decades later. Switching in the FeFET occurs due to the change of P_r in the gate ferroelectric, as described above. The change in polarization state is achieved by applying a positive or negative voltage pulse on the gate. When a positive pulse is applied, the resulting remnant polarization in the ferroelectric holds an electric field in the direction of the channel to the gate electrode, which raises the threshold voltage (V_T) of the MOSFET. This electric field can be thought of as subtracting a portion of the gate field, hence making it more difficult to turn the device on. Conversely, a negative gate pulse creates a remnant electric field which points from the gate to channel, and enhances the voltage applied by the gate. This field normally attracts electrons and creates an inversion layer in the n-FET, effectively creating a normally on device. For an in depth physical analysis and complete analytical model of the FeFET device physics, the reader is referred to Chapter 6 of this book and Reference [56].

The FeFET is the only FET-based memory described in this chapter, and hence it has a slightly different performance and reliability characterization methodology than other (e.g., resistive switching) nonvolatile memories. The retention is typically based on either the time dependent difference in V_T or difference in I_D of the SET and RESET states of the after a given time period. The slope from these V_T shifts following a few days to a few weeks are typically extrapolated to 10 years to provide a projected V_T window after this time.

Prior to around 2004, progress on developing a scaled FeFET with reasonable retention was relatively slow [57]. In 2004, a 10 μm device was demonstrated with 10¹² cycles of endurance which retained data for 12 days, maintaining an I_ON/I_OFF ratio of 10⁶ (although no long term endurance projection was made) [58]. In 2011, the first submicron FeFET with 10 year retention projected [59]. These devices utilized a Pt/SBT/Hf-Al-O/Si gate stack and had a minimum gate length 0.26 μm, and gave an endurance of 10⁸ cycles. In this work, utilizing 20 μs writing pulses of −4 V and +6 V, an initial voltage window of 500 mV was obtained, and an estimated voltage window of ∼250 mV is extracted from a one week retention measurement [59]. In 2012, the same group demonstrated a 64 kbit FeFET array based on the Pt/SBT/Hf-Al-O/Si gate stack [60]. This array requires 10 μs ±7.5 V SET/RESET pulses, and achieves 10⁸ cycle endurance. An initial window of 350 mV was demonstrated and a 10 year V_T window of 200 mV was predicted (extrapolated from a 48 h measurement).

Recent demonstrations of ferroelectric silicon doped HfO₂ (Si: HfO₂) show some of best performance, reliability, and scaling data to date [53,61]. At IEDM 2011, HfSiO FeFETs were demonstrated which required 1 s programming with voltages of −3 V and +4 V and achieve an initial V_T window of 1000 mV, which is predicted to be 650 mV after 10 years [53]. In 2012, a similar Si:HfO₂ FeFET with a gate length of 28 nm was demonstrated, by integrating the ferroelectric HfO₂ into the gate stack of a HKMG CMOS process [61]. This FeFET required 20 ns, ±5 V SET/RESET pulses and produced an initial V_T window of 1000 mV. It was estimated that these devices would maintain a 600 mV window after 10 years (extrapolated from a 30 h measurement). Endurance on this highly scaled device was only 10⁴ cycles due to significant charge injection.

Retention remains a key issue for the FeFET. All 10 year retention extrapolations are made from actual measurement lasting 12 days or less. Poor retention is due to two issues inherent in integrating a ferroelectric capacitor in a MOSFET gate stack: (a) the depolarization field and (b) charge trapping at the ferroelectric buffer- or ferroelectric-semiconductor interface [57]. The depolarization field occurs as a consequence of integrating a ferroelectric capacitor with a semiconductor. It is not possible for the ferroelectric to have the polarization charge compensated charge on the semiconductor side (even with a buffer layer) due to the capacitance of the semiconductor. The second issue, charge trapping at the interface of the ferroelectric and semiconductor, is caused by the remnant polarization field acting on this interface [53,57]. This charge eventually compensates the field created by the remnant polarization of the ferroelectric and effectively cancels the threshold voltage shift. Charge injection appears to be especially deleterious on highly scaled devices [61].

The FeFET is also difficult to integrate with CMOS, especially versions which rely on SBT or PZT. Doped HfO₂ offers an improved method of CMOS integration, but additional research is still needed to understand the origins of ferroelectricity in this material. In addition, the FeFET always requires an FET structure, and hence is not easy to integrate as a back end of line (BEOL) memory, as with metal/insulator/metal structures like ReRAM and the ferroelectric tunnel junction. However, if the extremely high endurance of the FeFET could be combined with high speed, low energy switching, it could serve as a strong M-class SCM or DRAM replacement candidate.

13.4.2 Ferroelectric Tunnel Junction

The ferroelectric tunnel junction (FTJ), also referred to as ferroelectric polarization reversal memory, is an asymmetric, metal/insulator/metal or metal/insulator/semiconductor resistive switching memory device. The insulator is a thin ferroelectric film which causes the resistance measured through the electrodes vary significantly based on the polarization direction due to the giant tunnel electroresistance (TER) effect. The theoretical concept of giant TER was first proposed as a polar switch by Leo Esaki in 1971, although experimental demonstration was not achieved until the early twenty first century [62]. Typical ferroelectric insulators are perovskites, such as BaTiO₃ (BTO) and Pb(Zr,Ti)O₃ (PZT). One electrode is often a metal such as Pt or Au. The other (e.g., bottom) electrode is typically a conducting perovskite, such as La_xSr_yMnO [63] or SrRuO₃ [64]. Recently, improved tunnel electroresistance was found by using a semiconducting bottom electrode, Nb:SrTiO3 [65].

The SET, RESET, and read procedures are similar to bipolar ReRAM, but the physical mechanism is markedly different. The resistance switching in an FTJ can be explained with the aid of Figure 13.4. The device is set to a low resistance state (LRS) by applying a positive voltage pulse to the top electrode (2–5 V, and 10 ns to 100 μs are typical experimental values) [63,65]. This voltage pulse causes the electric field in the ferroelectric layer to polarize in the direction of the bottom to top electrode, as illustrated in Figure 13.4a. In this state, the electron tunnel barrier, ϕ, is low compared to the opposite polarization (the average barrier for the LRS is denoted ϕ₀ in Figure 13.4). A negative voltage pulse of roughly equal time and magnitude causes a reversal of the polarization, and the barrier rises to an average height of ϕ_L. The cell is read by measuring the current at a voltage low enough to avoid disturbing the polarization, typically on the order of 100 mV.

FTJ memory was realized for the first time in the past several years, and hence only a handful of proof of concept studies of memory cell characteristics have been performed. In 2012, a 50 nm FTJ memory was demonstrated [63], with an estimated potential to scale to 10 nm, based on the ferroelectric domain size [5]. This device had the very low write energy of 10 fJ/bit. The highest published endurance and retention values are given in Reference [67] for a Co/BiFeO₃/Ca_0.96Ce_0.04MnO₃ FTJ of 4 × 10⁶ cycles and 10 years, respectively. Reference [65] elucidates a common, but important tradeoff between retention, endurance, and write voltage can be found. If a write voltage of 3.5 V is used, R_OFF/R_ON values of 10⁴ are possible (which will increase retention), but endurance is limited to tens of cycles. In the opposite extreme, if a write voltage of 2.2 V is used the R_OFF/R_ON drops to about 40, which increases the endurance but reduces the retention times and decreases read margins in an array.

FTJ memory shows promise as a scalable, ultra-low switching energy technology, but is relatively new and has many research challenges that must be overcome before being considered as a viable NAND flash, SCM, or DRAM replacement candidate. One of the key research areas is to prove that a single FTJ can have an endurance greater than 10⁶, while maintaining reasonable retention. Scaling down to 10 nm or less must also be proven. Furthermore, it will be technologically important to develop an FTJ using CMOS compatible materials; one possibility is to take advantage of ferroelectricity discovered recently in doped HfO [52]. Another important step will be to develop FTJ memory arrays and explore the cell to cell variation and yields.

13.7.1 Amorphous Carbon and Diamond-like Carbon

An amorphous carbon (a-C) or diamond-like carbon (DLC)-based resistive switch consists of an electrode/x/electrode structure similar to other ReRAM cells, where x is an a-C or DLC layer. Resistive switching in amorphous carbon is reported to result from numerous different physical mechanisms. In several reports, unipolar switching in a-C [85,87] and DLC [88] is thought to occur due to the formation and rupture of a sp³ filament in the material. This case is analogous to metal oxide-unipolar filamentary ReRAM, as the SET and RESET mechanism are both thermochemical.

In another case, when the structure includes a Cu or Ag electrode, and bipolar switching occurs, it is reasonable to propose that the electrochemical formation and dissolution of a metal filament cause switching. This has been observed in both Cu/a-C/electrode and Ag/a-C/electrode structures [89]. In this case, the memory is an EMB ReRAM cell (as discussed above), where the insulating layer is composed of amorphous carbon rather than the more traditional EMB materials such as chalcogenides and metal oxides.

13.7.2 Graphene and Graphene Oxide

Graphene-based memories have been reported by multiple groups [90–93]. A resistive switching structure is typically comprised of a graphene strip contacted on both sides by electrodes (i.e., Pt [90] or Cr/Au [92]). One proposed mechanism of switching in graphene is the nanoelectromechanical breaking and reattaching of the strip [90]. Bipolar resistive switching in a graphene strip has also been explained by charging effects [90].

Bipolar switching has also been reported in metal/graphene oxide (GO)/metal structures. In the case where one of the electrodes is Cu, it is likely an electrochemical metallization bridging effect occurs, similar to the EMB ReRAM. A Cu/GO/Pt structure with bipolar switching at ∼1 V, with a R_OFF/R_ON ratio of 20 and retention of 10⁴ s has also been reported [90]. A flexible Al/GO/Al structure was demonstrated with bipolar switching at about 3.5 V, suggesting a valence change mechanism similar to that in MO-BF ReRAM.

13.7.3 Carbon Nanotubes

Carbon nanotube memory originally attracted significant attention in the year 2000, after the concept of a highly scaled memory array with each cell was defined by the cross-section of two carbon nanotubes was presented [94]. The proposed mechanism for switching in such an array was the electrostatic repulsion and attraction of the two crossing nanotubes. More recently, a full prototype memory chip IC was demonstrated based on lithographically defined carbon nanotube resistance switching layers [95]. The proposed switching mechanism is fundamentally the same electrostatic resistance switching mechanism reported in reference [94]. However, it was hypothesized in the lithographically defined nanotube layers that the connection and repulsion of many nanotubes in concert is responsible for the observed resistance change [95]. The 4 Mb test chip based on 22 nm carbon nanotube layer memory cells has a typical SET operation requiring a 5 V pulse for 500 ns, with a typical current of 1 μA. The RESET operation requires a 50 ns, 4.5 V pulse resulting in a typical current of 15 μA. Assuming both currents give are averages, the SET and RESET switching energies are 2.5 pJ and 3.4 pJ respectively. An endurance of 10⁴ cycles and retention of 24 h at 125 °C are reported for this prototype. For this carbon nanotube layer-based NVM technology, few fundamental studies have been published, and hence it is difficult to verify the switching mechanism.

13.7.4 Research Challenges

Carbon memories present interesting features, such as high temperature operation, flexible arrays, and simple processes. However, carbon memory is a relatively young field with many research challenges. Foremost is the understanding of switching mechanisms in different materials. Resistive switching in amorphous carbon and graphene oxide appear to have similarities to redox memory; if this is verified it would be appropriate to consider them a member of the ReRAM family. More fundamental work is needed to understand and verify the proposed switching mechanisms in each category of emerging carbon memory.

13.9.1 Scaling

The scalability of an emerging memory technology is a key factor for it to be considered a strong candidate to replace traditional data storage technologies. Although NAND flash has been scaled to a 2D density of 16 nm, a density of roughly 9 × 10¹⁰ bits/cm² (or ∼11 GB/cm²), these ultra-scaled devices have suffered severely degraded retention, endurance, and yield [5]. DRAM also has “no known solutions” for scaling challenges below the 20 nm half pitch, occurring in 2017 [5]. The maximum density a memory technology can reach is defined by the minimum feature size F and cell area, in terms of F. The maximum density of a layer is plotted in Figure 13.5 for a given feature size using a cell area of 4, 6, and 8 F².

Scalability is one of the categories evaluated in both the qualitative and quantitative sections of the ERD chapter. Scalability below 10 nm is predicted for all emerging memories, although it has only been demonstrated for BF-MO ReRAM (see Table 13.3). This matches the qualitative opinion reflected in the expert survey that ReRAM has the highest potential scalability (Table 13.4). It is reasonable to conclude that other emerging memories that rely on filamentary switching, such as certain types of carbon and macromolecular memory, will scale to the same dimensions as standard filamentary ReRAM. The high scalability of ReRAM makes it especially attractive as a NAND flash replacement for S-type SCM technology.

In certain memory categories listed in Table 13.1, such as M-type SCM and DRAM replacement, scaling is less important than performance factors, such as endurance, write speed, and energy. For example, while it is possible that the FeFET may not scale as well as ReRAM, but the high endurance may still make it a strong DRAM replacement candidate.

13.9.2 Performance

Emerging memory performance is assessed quantitatively in Tables 13.2 and 13.3 by write/erase speed, energy, and voltage. Performance is assessed qualitatively from survey results in Table 13.4, as an assessment of speed, energy efficiency, and ON/OFF ratio. Demonstrated SET/RESET speeds are 20 ns or less for all technologies except molecular memory and MO-BN ReRAM. Where available, all technologies had demonstrated switching energies of less than 10 pJ, and in many cases less than 1 pJ. Interestingly, the qualitative assessments of speed and energy efficiency are lowest for macromolecular memory, even though there are very competitive values reported in the literature for this technology. Differences in performance records reported in the literature and the opinion conveyed by the survey of experts might reflect significant recent improvement in performance, or the anticipation of difficulty achieving record performances on production devices. As described in Chapter 3, array and architectural considerations will ultimately determine the system level speed and energy requirements of each of these memories. For example, a DRAM cell only requires about 10 fJ at the cell level but at the system level requires ∼50 pJ.

13.9.3 Reliability

Write cycles (endurance) and retention data are the main quantitative measures of reliability provided in Tables 13.2 and 13.3, although other factors, such as device to device variability and random telegraph noise (RTN) are also important reliability considerations in memory device reliability. Variability and RTN are somewhat difficult to assess in a quantitative comparison table, but are expected to influence the expert survey opinions of “operational reliability” provided in Table 13.4.

The minimum endurance required for an emerging memory to enter any of the application markets described in Table 13.1 is about 10⁶ SET/RESET cycles. This endurance has been demonstrated in all categories of ReRAM, ferroelectric, and carbon memory (except graphene memories). If a memory technology has an endurance of less than 10⁶, it is likely that workarounds such as error correction code (ECC) and garbage collection routines will be needed (as with modern NAND-flash memory). Mott, molecular, and macromolecular memory have not yet met this requirement (although macromolecular has achieved 10⁵ cycles), and hence achieving this endurance should be a key research in those technologies.

For M-type SCM and DRAM replacement applications, higher endurance is required. M-type SCM requires one billion cycles, whereas straightforward DRAM replacement would require 10¹⁶ SET/RESET cycles. The requirement of a billion cycles has been met by the FeFET, as well as EMB and MO-BF ReRAM. This high endurance, along with excellent performance makes these technologies potential M-type SCM and DRAM replacements. In the case of the FeFET, the low retention is not an impediment for these technologies.

The retention required for the traditional NVM applications of embedded EEPROM and NAND-flash, as well as S-type SCM is 10 years (typically retaining data at a temperature of 85 °C). Since it is difficult to make a measurement over 10 years, retention is typically projected from accelerated measurements [41], but there is not a standardized method of reporting these projections in an emerging memory device [105]. ReRAM (except for non-filamentary) are projected to meet this 10 year requirement from relatively detailed retention studies that derived from thorough arhennius studies. Ten year retention is also predicted for the FeFET and FTJ, although the longest demonstrated periods are about three days for each, and hence additional data is needed to verify this claim. For a DRAM replacement and M-type SCM memory retention is much less important (whereas endurance is key), and hence the FeFET and FTJ are still a strong contenders.

Qualitatively, all emerging memories scored low in the “operational reliability” category. This can be presumably attributed to several factors, especially variability in the SET and RESET states between devices and lack of long term reliability data. This illustrates the general fact that after basic functionality of an emerging memory technology is demonstrated, research and development efforts must prove reliability before being accepted in any of the markets listed in Table 13.1. Perhaps finding a niche, low consequence market which allows the memory product to demonstrate reliable operation of high quantities of parts is the best approach to gain widespread use of an emerging memory technology [11].

The scores for macromolecular and molecular memories were the lowest at 1.3 and 1.1, respectively. This indicates a strong need for these technologies to focus research efforts on proving that reliable operation is possible, otherwise commercial adaptation of these technologies is unlikely.

13.9.4 CMOS Compatibility and Cost

CMOS compatibility and cost are, perhaps, the most subjective requirements for emerging memory technology, although they are also often the greatest factors which determine commercial success in any market. All emerging memories discussed except for the FeFET employ back end of line (BEOL) processing, and hence their CMOS compatibility should be assessed with regard to BEOL materials and temperatures. ReRAM received the highest score on CMOS compatibility, which likely reflects that at least for certain ReRAM devices, there are no special materials required and that this technology can survive typical BEOL CMOS temperatures (which are typically a maximum of 400 °C). The lowest scores were given to macromolecular and molecular memories, and can be attributed to two problems. First, both of these technologies require special materials not typically found in fabrication, (such as polymers). Second, it is not clear that many of these polymers or molecules can survive BEOL temperatures and process conditions.

Another important factor in CMOS compatibility is the maximum voltage require in the SET or RESET operation. EMB ReRAM has the lowest demonstrated switching voltages (0.6 V has been demonstrated), which provides an advantage in the integration with advanced CMOS nodes without the need for a separate high voltage transistor.

13.9.5 Tradeoffs

One of the greatest shortcomings of Tables 13.2 and 13.3 is that they present record performance and reliability metrics for different devices of a particular technology column. For example, in the MO-BF ReRAM different devices were used to demonstrate scaling to 5 × 5 nm, sub-ns switching, 10¹² cycle endurance, and 10 year retention at >100 °C. A single device with all of these characteristics has not been demonstrated. It should also be noted that these parameters come from array demonstrations when possible, but are often from single devices. More mature technologies like EMB ReRAM have metrics taken from sophisticated test chips which closely resemble future commercial products, whereas the least developed technologies generally have parameters available at the research device level. As discussed in Chapter 3, array parasitics and peripheral circuitry can significantly increase the write energy. Power considerations of passive resistive memory arrays have been modeled in reference [106]; and array level energetics of these arrays is an important area of future work.

Hence, it may not be possible to obtain a device or an array in a given emerging memory technology that has all of the characteristics of a column in Tables 13.2 and 13.3. This methodology is intended only to provide the most optimistic characteristics of emerging memory technology with a single data set.

It is therefore worthwhile to consider the tradeoffs that prevent the simultaneous achievement of every parameter for a column of Tables 13.2 or 13.3. One common example of this type of tradeoff is that between switching current (which is reflected in switching energy) and retention of a ReRAM cell. An example of this is provided in Reference [40], whereas the compliance current used during switching is the key factor which determines retention. When the compliance current of 100 μA is used to SET the device, a wider, more robust filament is formed compared to when 10 μA is used. Hence, the temperature at which 10 year retention is possible is 105 °C for a 100 μA cc but only 95 °C for a 10 μA cc. This demonstrates that it is possible to increase the retention of a ReRAM cell if one is willing to pay the price in switching current (and therefore switching power). Fundamental energy–space–time tradeoffs for ReRAM are discussed in detail in Reference [107].