18.1.1 Addressing the CMOS Power Crisis

For about four decades, increasing transistor density (thereby increasing chip functionality and lowering cost per function) has been carried out following a set of relatively simple transistor scaling rules [1–3]. These “constant field” device scaling guidelines were purposefully designed so that active power consumption would scale with area, hence keeping the power density constant. However, scaling the supply voltage V_DD with no penalty in terms of circuit speed requires the ability to maintain a sufficient gate overdrive (V_DD–V_T, defining the on-state resistance of a transistor). Unfortunately, there is a fundamental limit on how much the threshold voltage V_T can be reduced without causing an exponential increase in leakage current, and therefore passive power density. This limit is a direct consequence of a MOSFETs subthreshold current–voltage relationship (Figure 18.1).

With V_T pinned, the gate overdrive had to be reduced and performance sacrificed in order to keep the active power density under control. Although system throughput can be recovered through the use of parallel design (e.g., multi-core processors), a lower bound in total energy per operation is eventually reached when transistors function in the subthreshold regime [6]. Alternative field-effect transistor architectures designed to overcome the subthreshold swing limit of 60 mV/decade at room temperature have been proposed, including the impact ionization MOSFET [7], the tunnel FET [8], the negative-capacitance FET [9] (see Chapter 15). However these solid-state switches still exhibit nonzero leakage currents, hence a subsisting fundamental lower limit in energy efficiency. In contrast, a mechanical relay operating by closing and opening an air gap to switch signal on and off such as illustrated in Figure 18.2, would offer the combined advantages of zero leakage current and extremely abrupt switching behavior.

As one might expect from such an intuitive representation of an ideal switch, the use of mechanical relays for computing is not exactly a new idea, and dates back to the late 1930s [10]. Konrad Zuse completed in 1941 the Z3, the world's first functional programmable, fully automated electromechanical computer, switching 2000 relays at frequencies of 5–10 Hz [11]. Almost immediately abandoned in favor of vacuum tubes and solid-state switches, it took several decades worth of technological advances in planar processing, and in particular surface micromachining, to make mechanical computing once again relevant in terms of scalability [12]. This continued progress combined to the emergence of the CMOS power crisis has recently triggered renewed interest in Micro and Nano-ElectroMechanical Systems (M/NEMS) for ultra low power integrated circuits [13,14].

18.1.2 Throughput and Area Efficiency

Various options are available to mechanically open or short an electrical connection between two electrodes, and the constraints associated to fabrication processes may vary according to the type of NEMS switch transduction. Each actuation mechanism also features distinctive advantages and limitations in terms of time and energy required for a switching event. Thus, it is useful to define rough goals in terms of energy–delay trade-off prior to assessing the adequacy of various NEMS relay families for digital logic, which will be the object of Section 18.2.

Today, the intrinsic delay of a single MOS transistor should be on the order of a picosecond. As a rule of thumb, this is three orders of magnitude smaller than what can be expected in terms of mechanical delay due to, for example, an electrostatically actuated relay. This may however not be a showstopper. In CMOS digital ICs, the delay is set by the electrical time constant: stacking devices comes with a quadratic delay penalty, leading circuit designers to buffer and distribute the logical effort over many stages. This is not the case for NEMS relays, for which mechanical inertia dominates over RC delay. In consequence, logic can be implemented using larger, more complex gates where all relays actuate at the same time (single mechanical delay) with in some cases little to no area penalty as device count is reduced [14,15]. Projections suggest that this relay logic could compete with CMOS at the nanoscale [16–18], with typically lower operational frequency but lower energy (Figure 18.3).

Once again, a lower throughput can be compensated by resorting to massive parallelism. But this is eventually detrimental to area efficiency and therefore cost per operation. Although the manufacturing cost of a NEM switch can arguably be predicted to be lower than, for example, a state of the art FinFET; concluding at this point that NEMS can entirely supplant CMOS for digital logic would be premature. A NEMS-only integration scheme would obviously be the least constrained in terms of process sequence, thermal budget and material selection, but at the risk of confinement to low density, moderate speed applications such as Field-Programmable Gate Arrays (FPGA). Considering the above, trying to keep the NEMS switch technology CMOS-compatible may be more prudent for high-speed digital logic. Because not all transistors in a microprocessor operate at the maximum clock frequency, a NEMS/CMOS co-integration scheme could enable saving energy using relays in the low throughput sub-blocks, while maintaining high-performance where needed.

Monolithic co-integration offers the advantage of reduced interconnect parasitics over a “system in package” approach [20]. MEMS-first integration has considerable handicaps in terms of device scalability and foundry compatibility due to the extensive preprocessing required and resulting increased wafer cost. A MEMS-last process, in which the MEMS fabrication steps are performed after completion of the CMOS back end of line, seems the most attractive. It is however critical that the underlying electronics can withstand the thermal budget of MEMS processing. Transistor characteristics must remain unaffected (avoiding dopant diffusion, equivalent oxide thickness variations), and the metal interconnects should be preserved from via resistance failure and electromigration which may arise from thermal stress and annealing effects. It was shown for example that the thermal budget limit for a 0.25 μm CMOS process was 425 °C for 10 h [21]. This significantly restricts the choice of structural materials available for NEMS fabrication (low temperature oxides, amorphous Silicon, polycrystalline SiGe, etc.).

18.2.1 Electromagnetic

Electromagnetic relays convert a magnetic field into mechanical displacement based on either the Lorentz force or the magnetostrictive effect. Essentially, an inductor and a soft magnetic actuator are required, although the addition of hard magnetic films (permanent magnets) to improve energy efficiency seems unavoidable at the micro and nanoscales (Figure 18.4).

Generating a magnetic field can be achieved by flowing current across an inductor such as a Cu coil. For ease of fabrication, planar coils are preferred over their three-dimensional, multi-layered counterparts, in spite of being particularly area consuming. In addition to this, coils do not fare particularly well in terms of energy efficiency at the microscale, so that integrating auxiliary permanent magnets (PM) may be necessary to add a “background” preactuation magnetic field and hence decrease power consumption during switching. As an indicator of how poorly they scale, it can be shown that a tremendous 10⁴ A/mm² current density is needed for a 100 μm micro-coil to generate the same magnetic moment as a 1 T magnet of same dimensions, with every size reduction by a factor of 10 resulting in an 10-fold increase of the required current density [23]. The most suitable permanent magnet materials include thin film CoPt, FePt, or rare earth-based thick film Nd₂Fe₁₄B, SmCo₅ [24]. CoPt and FePt processing requires relatively high post deposition annealing temperatures (500–700 °C) for obtaining high coercivity values, which is a major disadvantage for CMOS co-integration. On the other hand, the use of rare earth-based alloys comes with problems of easy oxidation, etching process compatibility and adhesion to Si as well as potential contamination issues.

The most straightforward way to emulate a switch is to subject a soft magnetic film to the Lorentz force. Permalloy (NiFe) cantilevers can be used [22,25] with the following advantages: well-developed technology for deposition and micromachining (owing to the longstanding use of permalloy magnetic heads in the recording industry), high saturation flux density and low hysteresis. Besides, permalloys are immune to the reverse magnetostrictive effect, which causes a change of magnetic properties under mechanical stress. Displacement can also be obtained by taking advantage of the direct magnetostrictive effect, which results in the deformation of some ferromagnetic films upon magnetization. This type of transduction can be used to provoke strain mismatch-induced deflection of a bimorph membrane or cantilever coated by magnetostrictive films [26]. Suitable candidates for such coatings in terms of sensitivity include rare earth TbFe, SmFe thin films or TbFe/FeCo multilayers [26,27].

Without specifically targeting digital logic, magnetic microrelays demonstrators have so far exhibited switching power consumption of the order of 10–100 mW, sub-kHz operating frequency and single device area measured in mm² [22,25]. To this day, electromagnetic switches do not seem particularly adequate for computing applications because of inherent issues related to area consumption, unconventional processing and insufficient energy efficiency.

18.2.2 Electrothermal

Thermal expansion is the driving phenomenon for electrothermal switches actuation. Two terminals are dedicated to providing power to the actuator through dissipated heat. This can simply be achieved with Joule heating caused by current flowing across a resistive actuating cantilever or beam. Specifically engineered geometry such as a V-beam [28], or thermal expansion coefficient mismatch within a bimorph structure [29,30] causes them to buckle when heated (closing a gap and making contact between two other terminals), and return to their original position once the power is turned off (breaking contact). Thermally actuated relays have been reportedly investigated for a wide range of applications which so far did not include computational logic: switched inductors [29], contact test structures [31], RF MEMS [28] and CMOS power gating for zero standby power [30].

Commonly cited advantages of such devices are high contact forces, large possible displacements and IC-compatible low actuation voltages [28]. High contact forces are typically associated to low contact resistance and therefore low insertion loss which is indeed a significant advantage for RF switches. For logic circuits however, as discussed in Section 18.1.2, the RC delay is typically orders of magnitude lower than the mechanical delay so that lowering the contact resistance is far less critical. This is especially true if its root cause is plastic deformation occurring in the contact regions, which raises additional concerns in terms of reliability (cycling, hysteresis). Large displacements can also be problematic for endurance, due to accelerated structural fatigue. Besides, because actuation is slow (hundreds of microseconds) and high currents are needed to generate sufficient heat, sub-1 V actuation voltages do not prevent thermal micro-relays from consuming around 10 mW for a single switching event [30]. Finally, from the perspective of potential for large-scale integration, the scalability of such switches seems once again fundamentally limited by the transduction mechanism.

Electrothermal NEMS relays do not appear as strong contenders for beyond CMOS computing. They are in some regards comparable to electromagnetic switches, albeit with the undeniable advantage of more conventional material processing.

18.2.3 Piezoelectric

Piezoelectric materials have the ability to charge in response to mechanical stress (this is the direct piezoelectric effect), and reciprocally to deform in response to an electric field (this is the reverse piezoelectric effect). While the former is most useful in resonators for acceleration, pressure or mass sensing [32,33], the latter is exploited in micro-actuators [34]. Because of their use for a particularly broad range of MEMS applications, and even some IC applications such as FeRAM [35], piezoelectric materials process technology has been relatively well developed. Piezoelectricity is also linear (which in itself is interesting for resonators, but of little relevance to logic switches operation) and bi-directional, meaning that displacement on both sides of the equilibrium position is possible depending on the polarity. This last property is very interesting in that it enables active turn-off of a relay, a feature which will be discussed later in Section 18.3.3, and facilitates the implementation of complementary logic.

The most commonly used piezoelectric materials for MEMS are PbZr_xTi_1−xO₃ (PZT), aluminum nitride (AlN) and zinc oxide (ZnO). PZT is known to yield the most efficient transduction, but high quality material availability is limited (need for stoichiometry control with x = 0.53 for maximal efficiency), and it is lead-based, which makes it incompatible with CMOS foundries [36]. AlN-based microrelays have been proposed in particular by researchers at the University of Pennsylvania, first for use as RF switches [37,38] and later for complementary logic [36,39]. These recent studies show variations of the dual beam design illustrated in Figure 18.5 featuring numerous advantages: active turn-off, complementarity, threshold adjustment via body-biasing, immunity to stress-induced out of plane bending, and an actuation mechanism (based on buckling of bimorph beams) which allows overcoming the typically small displacements generated by the reverse piezoelectric effect.

A Pt/AlN/Pt/AlN/Pt (200 nm/1 μm/200 nm/1 μm/200 nm) sandwich serves in this case as the structural stack. A gold contact is patterned on top of one of the beams, separated from the top Pt layer of the other beam by a contact air gap defined by a 200 nm amorphous Si sacrificial layer release-etched in vapor phase XeF₂. In one of the two opposing beams, the bottom AlN layer is made to longitudinally expand (respectively, contract) through reverse piezoelectric effect, while the top layer is made to contract (respectively, expand), causing the beam to buckle upward (respectively, downward). An Au/Pt contact is made as the two beams meet, transmitting the signal. The beams can be moved apart by changing biasing polarities in the Pt layers (active turn-off). With these switches, sub-1 V operation has been demonstrated thanks to body-biasing (V_B = 14 V), with 220 ns switching time, and endurance up to 10⁷ cycles with low contact resistance (<500 Ω) [39]. A complementary relay inverter was also demonstrated at 100 Hz. Remaining challenges include scaling down the vertical and lateral dimensions (the current footprint being around 200 × 200 μm² per switch), which would improve area efficiency and reduce parasitic capacitances limiting high frequency operation. A different Au-free contacting metal should be implemented to render processing CMOS-compatible, which may change the deal in terms of contact resistance value and stability.

Piezoelectric relays show promise for mechanical computing applications in terms of speed and energy efficiency. CMOS process compatibility and technology scalability are the next roadblocks to address. Encouragingly, recent works on resonators for gravimetric detection have led to demonstrating 50 nm thick AlN films with excellent piezoelectric properties [33].

18.2.4 Piezoresistive

The piezoresistive effect is a change of electrical resistivity in semiconductors upon application of mechanical stress. This property is widely used in strain-enhancement techniques for high-mobility CMOS. Piezoresistive elements can be incorporated in mechanical relays to generate an abrupt switching behavior when combined in series with a supplementary transducer converting an electrical signal into mechanical stress (e.g., piezoelectric, electrostatic, etc.). The appeal of such an approach with added complexity is that it circumvents the obstacle of contact adhesion forces, which may cause hysteretic characteristics or even functional failure in most air gap-based mechanical switches.

Polymers doped with carbon black or metal nanoparticles can also emulate piezoresistivity and although the fundamental mechanism is different, sharp stress-conductivity characteristics can be obtained. MIT researchers introduced a three-terminal mechanical relay consisting of a patterned polydimethylsiloxane (PDMS) pillar containing Ni nanoparticles, and becoming conductive when squeezed by an electrostatically actuated Al membrane, hence the moniker “squitch” [40]. When a sufficient pressure is applied to the nanocomposite, a conduction path is created between the conductive metallic particles and the relay turns on with a theoretical 10⁻⁷ R_on/R_off ratio. This architecture faces many practical problems, such as sensitivity to creep, possibility of inter-particle adhesion causing reliability issues upon cycling, and more obviously process integration and scalability.

IBMs PET concept (PiezoElectronic Transistor) relies on the inverse piezoelectric effect to transmit stress to a piezoresistive “channel” [41]. For the stress transfer to be efficient, a yoke made of a high yield material such as SiN should be preventing mechanical displacement of the free boundary of the PR film (Figure 18.6).

The best candidates for optimal transduction are believed to be PZN-PT {(1 − x)[Pb(Zn_1/3Nb_2/3)O₃] − x[PbTiO₃]} or PMN-PT {(1 − x)[Pb(Mg_1/3Nb_2/3)O₃] − x[PbTiO₃]} for the piezoelectric element, and SmSe, TmTe, Eu-doped SmS or Cr-doped V₂O₃ for the piezoresistive element [41]. In a best case scenario, an analysis of the device's dynamic response indicated an outstanding projected operating frequency of 20 GHz at V_DD = 0.1 V. Nevertheless, these numbers rely on many assumptions such as: (i) negligible three-dimensional effects, (ii) lossless stress transfer, and most of all that (iii) these lead-based and rare earth chalcogenide materials can be integrated down to thicknesses of a few nanometers while conserving their sensitivity. Moreover, static analysis shows a 10⁻⁴ R_on/R_off ratio for a gate-common bias of 0.18 V, which translates into an equivalent less than ideal subthreshold swing of 45 mV/dec.

Pending further experimental work, it is unclear at this point whether the energy efficiency benefits of piezoresistive switches can eventually be worth the implementation of an extremely disruptive technology with uncertain scalability.

18.2.5 Electrostatic

M/NEM relays utilizing electrostatic actuation may now appear excessively simple in comparison. Although not the most popular for RF switching applications due to relatively low contact forces and high contact resistance [42], these characteristics are not critical for computational purposes, as previously discussed in Section 18.1.2. These switches are essentially based on two conductive layers forming a capacitor: one being fixed and the other movable (e.g., cantilever, clamped–clamped beam, membrane, nanowire). They are therefore generally easy to fabricate with conventional planar processing techniques and conventional, inexpensive, MOS-compatible materials which do not lose their transducing properties at the nanoscale. As the capacitor charges upon applying a potential difference, the attractive electrostatic force (regardless of polarity) deflects and accelerates the movable electrode towards the fixed one. When the actuating bias disappears, the switch can be passively turned off as the spring restoring force causes the movable membrane to return to its original position, breaking the contact. Let us consider the simple model in Figure 18.7, where the top electrode of a parallel-plate capacitor of area A is suspended by a spring of elastic constant k and is separated from a fixed bottom electrode by a distance g.

Under a bias V, the electrostatic force F_elec and spring force F_spring exerted on the top electrode are [43]:

(18.1)

As the deflection increases, F_elec increases superlinearly, whereas the F_spring increase is only linear. Beyond a critical displacement which can be easily derived as g = g₀/3, the system becomes unstable, F_elec is always superior to F_spring and the switch closes abruptly: this phenomenon is called pull-in. The pull-in voltage V_pi is thus:

(18.2)

In order to keep V_pi low and the switching energy minimal, the spring should be relatively compliant, but it also should be sufficiently stiff to overcome contact adhesion forces. Contact dimples are commonly used in order to minimize the contact area and alleviate this constraint. In this case, it is useful to distinguish between the actuation gap g₀ and the contact dimple gap g_d. If g_d is larger than g₀/3, the switch is operating in pull-in mode. A characteristic of pull-in mode is that although the actuated plate does not collapse onto the fixed electrode, the abrupt increase in capacitance when V > V_pi causes an intrinsically hysteretic current–voltage characteristic. In nonpull-in mode (g_d < g₀/3), the adhesion forces alone may contribute to the hysteresis. It should be noted that there are ways to avoid pull-in instability beyond the g₀/3 displacement limit, such as leveraged bending [44] or dynamic charge control (by adding a capacitor in series) [45].

From a dynamic point of view, neglecting contact bouncing and ringing upon contact break, the mechanical delay can be approximated [16] as a function of the fundamental resonant period [2π(m/k)^1/2], the dimple to actuation gap ratio (g_d/g₀), and the “gate overdrive” (V_DD/V_pi):

(18.3)

α, β and γ can be numerically derived by solving Newton's second law of motion; their values primarily depend on the quality factor Q of the system and thus on the damping ratio for its first mode of oscillation. χ is an adjustment variable accounting for the dramatic increase of t_delay when V_DD/V_pi is very close to 1. Equation 18.3 gives us a sense that to minimize the delay for a given overdrive and gap aspect ratio, the structural material of the actuated electrode should be stiff (high Young's modulus) and light (low density). This is why speed is one of the driving arguments for investigating carbon-based electrostatic switches (Carbon Nano Tubes [46–50], graphene [51], SiC [52,53]). Increased stiffness comes however at the cost of larger V_pi (18.2) and therefore higher switching energy.

If the system is underdamped (Q > 1/2), the oscillations of the movable plate after breaking contact could interfere with the off-state electrical characteristics and therefore set an effective t_delay larger than the previous pull-in-based expression. A cut-off distance g_c = 2 nm is generally considered large enough to avoid undesirable tunneling current between electrodes during off-state. Avoiding tunneling after release translates into a condition on the logarithmic decrement of the damped oscillations, which should be larger than ln(g_d/g_d − g_c). Expressed in terms of Q:

(18.4)

Substituting g_c = 2 nm, the inequality above results in a surprisingly simple but reasonably accurate rule of thumb stating that the quality factor should be designed to be smaller than the dimple gap g_d expressed in nm.

Obviously though, not all of these electrostatic relays can be modeled as parallel plate capacitors, and each design has its specific energy–delay trade-off. The next section is dedicated to the many design variations available to date in the literature for electrostatically actuated NEM relays, their assets and drawbacks.

18.3.1 (N > 3)-Terminal Switches

Many different switch designs are reported in the literature, which can be classified by number of terminals typically ranging from two [54] to eight [55]. The majority of them are three-terminal (3-T) relays, which can probably be explained by a natural tendency to mimic the transistor configuration of a control gate allowing signal propagation between two “Source” and “Drain” terminals. However, we have already evoked (Section 18.1.2) the risks of confining NEMS relay applications to CMOS-like logic: this path should probably be avoided unless each relay can switch (mechanical and RC delay) as fast as a transistor, and its individual footprint is comparable to that of a MOSFET.

Pass-gate logic, on the other hand, comes with a reduced device count (compensating for larger individual footprint) and enables switching one complex logic gate with a single mechanical delay. Single MOS transistors are notoriously imperfect devices for pass-gate logic. This is due to their intrinsic inability to “swing full rail” at the output, that is, having the ability to propagate both a logic “0” (V_S = 0 V) and a logic “1” (V_S = V_DD). Because V_GS has to be larger than the threshold voltage V_T, an nMOSFET can only pass V_S from 0 V to V_DD-V_T (and conversely, a pMOSFET from V_T to V_DD). The fundamental issue is that the control condition is coupled to the signal to transmit. The same principle applies to 3-T electrostatic switches, but an even more basic argument is that there is no such thing as a 3-T n- or p-relay, because electrostatic actuation is ambipolar. Adding a fourth “Body” electrode permits us to:

• Differentiate “pull-down” and “pull-up” relays.
• Lower the threshold voltage by preactuating the device.
• Decouple control and signal.

An example of a 4-T electrostatic switch with insulated channel attached to the movable electrode [56] is shown in Figure 18.8.

One can note that based on the design in Figure 18.8, the number of Source and Drain outputs can easily be increased by attaching more channels to the movable plate, as long as it serves circuit design efficiency and the total equivalent parasitic gate–channels capacitance remains negligible. A 6-T variation [57] with single Gate and a double pair of Source and Drain is the most straightforward implementation, further reducing device count and reducing the area required to implement a complex logic gate by up to a factor of two [58]. Only two of these 6-T devices connected can be used to deliver simultaneously an inverted and noninverted buffered signal (input on the tied gates). The number of gate inputs can also be multiplied to implement (depending on the biasing scheme) AND, OR [59–61] or MAJORITY (2n + 1 inputs, n > 1) [55] gates with a single relay; and each of the above plus their complementary with two relays [61] (Figure 18.9).

18.3.2 In-Plane versus Out-of-Plane Actuation

Considering the substrate as the plane of reference, we have focused so far on out-of-plane deflected switches. There are nonetheless many instances of in-plane-actuated electrostatic NEM relays: [62–67]. For such devices, the gaps are defined by lithography, as opposed to a deposited sacrificial layer thickness. In terms of layout and for a given processing sequence, it means that a broad range of V_pi can be targeted by simply varying the gap width, which has a much lesser impact on device footprint than adjusting the actuation area.

Yet, this supposed ease of design stands under the condition that the structural material of the movable electrode (typically metal, if co-patterned with all other electrodes) can be etched vertically with good anisotropy for a high aspect ratio. This may unfortunately not always be true, and in case of a limited membrane thickness, this loss of actuation area should be recovered by designing very long beams. This would introduce nonlinear spring effects making the pull-in behavior far less predictable (compared to a parallel-plate capacitor model and Equation 18.2) and, ultimately, switch dimensioning more difficult.

Another argument to consider is that while the in-plane actuated switch approach is relatively 3-T friendly, fabricating 4-T relays (for decoupled control and signal, cf. Section 18.3.1) can prove to be more challenging. It can be achieved through the use of less trivial processing steps such as spacer definition of the insulated channel, followed by localized stringer removal to suppress shorts [67].

18.3.3 Active Turn-Off Devices

In the first section of this chapter, a premise was that relays would allow overcoming the fundamental energy limit in CMOS circuits set by subthreshold leakage. However, a legitimate concern in electrostatic NEMS relay design is that hysteretic switching behavior (coupled to the fact that the switch should turn off at 0 V) is also setting a switching energy limit. Even considering an architecture with contact dimples, operating in nonpull-in mode (g_d < g₀/3), counting on a passive release to break the contact means that the spring restoring force for a displacement g_d should be large enough to overcome the contact adhesion force:

(18.5)

Unfortunately, the higher the spring constant k, the higher V_pi becomes (Equation 18.2). We have seen in Section 18.2.4 that piezoresistive relays could circumvent contact adhesion force issues by escaping from the conventional “physical contact make/break” scheme, but were not necessarily infinitely abrupt, zero-leakage (and depending on the choice of the piezoresistive material, not always hysteresis-free) switches.

A single-pole double-throw (SPDT) configuration is fairly common for in-plane actuated relays, because the design is straightforward. One actuating fixed electrode can be laid out on each side of the pole, and each can be used to break a contact occurring on the other side [50,63,66,67]. A notable out-of-plane SPDT variation called torsion microactuator or see-saw relay was initially designed for low voltage RF switches used for instance in passive phase shifters [68–71]. The motivation was the same as stated above: reducing the losses (power consumption) through using beams of lesser stiffness which would otherwise remain stuck down by adhesion forces.

A movable electrode is anchored along one of its coplanar symmetry axes. A fixed electrode is placed on each side of this axis under each half of the movable plate, so that it can swing on either side of the torsional axis depending on fixed electrode biasing scheme. The pull-in behavior of such devices can be predicted analytically with good accuracy [72,73]. What makes them particularly interesting for logic circuits is their built-in switching complementarity. Besides, it is possible to demonstrate switching symmetry about V_DD/2, which is advantageous for symmetric noise margins [74]. An example of a 7-T design with two insulated channels [75] is shown in Figure 18.10.

Pointing out that active turn-off consumes power is a tautology; at best this feature can help to lower the energy limit set by adhesion force. Compared to a spring-driven passive release, a see-saw relay is energy-efficient in cases where the contact adhesion energy on one side is larger than the amount required for pulling the other side down. Regarding the latter, see-saws have the handicap of showing a larger gap before actuation than the nominally defined gap (as-deposited sacrificial layer thickness), because this side is deflected upward when the other is touching down. This implies that minimal excursion of the movable plate should be targeted when toggling between on and off states, with extremely scaled contact dimple gaps.

18.4.1 Contact Stability

Even though mechanical delay is predominant in relay switching dynamics, the electromechanical (EM) contact resistance remains an important figure of merit for circuit design, because it determines how many simultaneously switched stages can be cascaded with no speed penalty. It is therefore critical that its value should remain stable upon cycling. This is true as well for the contact surface topology: plastic deformation of asperities following repeated impacts can modify the adhesion force, potentially leading to permanent stiction failure. This particular failure mode may also be caused by micro welding depending on the current density when the relay is in the on-state. The reliability requirements are largely dependent on the type of application. For example, it can be estimated that the on-state contact resistance of a switch should be kept below 100 kΩ for over 10¹⁴ cycles so that a relay-based microcontroller for embedded sensor applications could operate reliably for 10 years at up to 100 MHz with a transition probability of 1% [17].

It is essential to properly understand the physics of electromechanical contacts at the nanometer scale in order to select the appropriate materials, design and surface treatments needed to meet the performance and stability specifications. In practice, the contacting electrodes are almost never ideally flat, and the effective contact area A_a between two conductive rough surfaces is only a fraction of the apparent dimensions (e.g., as drawn on a lithographic mask). Physical contact is only made at some asperities, each having its own associated load (p_i), local area (a_i) and local current (i_i; Figure 18.11).

The constriction resistance R_c at each microcontact (arising from the convergence and divergence of the current flow) can be described by a size-dependent expression [76]:

(18.6)

ρ₁ and ρ₂ are the specific resistivities of the contacting surfaces 1 and 2, λ = (λ₁ + λ₂)/2 is the average electron mean free path, r is the radius of the microcontact of area a. When r < λ, the expression reduces to Sharvin's point-contact model [77]: electrons are assumed to ballistically travel across the contact without being subjected to scattering and R_S ≈ λ(ρ₁ + ρ₂)/2a. If r > λ, Equation 18.6 approaches the other limit case, Holm's resistance [78], for which the constriction resistance is dominated by scattering R_H ≈ (ρ₁ + ρ₂)/4r.

As the contact force is increased asperities can be deformed, causing the real contact area to increase, which in turn lowers the total EM contact resistance. This might seem beneficial at first glance but it should be noted that the flattening of asperities has some undesirable side-effects: increased real contact area and reduced separation of the noncontacting regions (which contribute to adhesion via van der Waals forces). As a consequence, hysteretic behavior is aggravated, possibly to the point of permanent stiction. Besides, for a fixed bias between the two contacting electrodes; a decreasing resistance leads to an increase in dissipated power (P = V²/R), heating the contact as a result, which accelerates its deformation and makes it prone to micro-welding.

In order to prevent permanent mechanical wear, the contact load should be sufficiently low (typically < 100 μN) to avoid causing plastic deformation of the electrode material. Selecting a contacting material of high Mohs hardness (>6) can also be useful. The stronger metallic bonds typically associated to hard materials [79] should not be detrimental to adhesion at this scale, because van der Waals interactions are believed to remain dominant (contacting small asperities in the elastic regime). Unlike for RF switching, the contact resistance does not have to be very low for digital logic applications, so the fact that the real contact area remains small is not a critical concern either. Iridium (Ir), rhodium (Rh), ruthenium (Ru), and tungsten (W), being hard metals, are therefore suitable candidates from a strictly electromechanical point of view.

However, extrinsic environmental contamination effects can be another important source of contact resistance instability. Late transition metals (Ir, Rh, Ru) are active catalysts and have been observed to cause the formation of friction polymers on and around the contacting surfaces [80] even in a reasonably clean, packaged environment [81]. This shows that extreme attention should be paid to removing any residual process-induced hydrocarbon contaminants (such as photoresist, or plasma etch byproduct). Tungsten has been shown to be significantly prone to oxidation, limiting the contact lifetime even under high vacuum [82].

Surface passivation techniques can be used to remedy these contamination issues. A few monolayers of conductive metal oxides such as TiO₂ can be deposited via Atomic Layer Deposition to coat W contacting electrodes after sacrificial layer release, thus improving reliability. This implies trading off some of the nominal contact resistance, but thanks to a moderate potential barrier for electrons at the W/TiO₂ interface, R_c may still fall within the 100 kΩ specifications [19]. Some other metals such as ruthenium or iridium can naturally grow a conductive oxide (RuO₂, IrO₂) when annealed in oxygen, which has the advantage of being localized as opposed to a nonselective ALD which may affect surface leakage. 2 nm RuO₂ can be thermally grown on pure sputtered Ru following a 2 h low temperature thermal oxidation at 420 °C [83]. The Ru/RuO₂ system seems promising so far for enhancing contact stability, although a practical implementation of this relatively unusual metal raises various process integration considerations such as ease of deposition onto other layers, film adhesion, ease of etching, stress compatibility, and of course overall cost of fabrication.

18.4.2 Process Scalability and Perspectives

We have seen in Section 18.2 that electrostatically-actuated NEMS relays were arguably among the most scalable switches. Later (Section 18.3), basic operating principles of the simplified parallel-plate actuator model showed that the ultimate limits in terms of energy efficiency and delay can be attributed to inter-related parameters:

1. The system's spring constant – low k for low V_pi, high k and low mass for small delay.
2. The actuation and contact gap – small excursion for low V_pi, large excursion for larger F_spring.
3. The contact properties – low but stable contact resistance with adhesion force smaller than F_spring.

One possible route for balancing trade-offs (i) and (ii) can consist of simultaneously opting for high spring constant and small contact gap. This is the strategy motivating the use of low density, high Young's modulus, ultimately thin structural materials such as Carbon nanotubes or graphene [84,85]. Nevertheless, it should be stressed that fabricating CNT or graphene-based nanorelays with insulated control (“Gate”) and transmitting electrodes (“Source and Drain”) appears extremely challenging, which could be a handicap in terms of circuit design optimization. An alternative solution may be using extremely thin amorphous metal films (e.g., deposited by ALD), the associated issue being residual stress management. In the case of out-of-plane actuated switches, residual stress can cause the movable electrode to buckle, altering the nominal gap value. This can be addressed by resorting to multi-layer structural stacks for stress compensation, or scaling the lateral dimensions to prevent out-of-plane deflection from building up [57], at the respective costs of increased mass (hence t_delay) and reduced capacitance (thus higher V_pi).

Releasing nanometer-scale gaps is not trivial. One of the most common configurations is sacrificial SiO₂ selectively etched in HF. Water is a byproduct (and catalyst) of this reaction, which may cause stiction upon release due to capillarity forces. By using a critical point dryer, 15 nm gaps could be released, undercutting relatively short TiN cantilevers [86]. Anhydrous HF release at reduced pressure (75 Torr) has led to the same results on poly-SiGe membranes with lateral dimensions of several microns [88]. Although process controllability has yet to be demonstrated, some design tricks can enable to release tiny contact gaps as small as 4 nm [54]. Volume-shrinkage induced gap formation processes based on silicidation are also a promising novel alternative for high aspect-ratio structure releases [88].

Item (iii) has been addressed in the previous subsection. Yet, it is worth pointing out that the multiple-asperity-based constriction resistance model might no longer stand for ultimately scaled contact dimensions [89]. Hard contacting electrodes would still be desirable for their resistance to plastic deformation in a “single-asperity” configuration, but the adhesion force would become dominated by metallic bonding (instead of van der Waals interactions). Since hard materials are usually characterized by high metallic bonding energies, surface treatment schemes (hydrogen passivation, controlled oxidation, ALD coating, use of self-assembled monolayers) to decrease the adhesion force are likely to be required at this scale.

Considering the tremendous progress accomplished recently in the fields of material sciences and technological processes for M/NEMS fabrication dedicated to advances in device and circuit design, the odds of an emergence of nanoscale mechanical computing to alleviate the CMOS power crisis are better than ever.