5.3.1 Electrical and Phase Transformation Properties

The electrical resistivity contrast between the crystalline and amorphous (as-deposited) state in phase change materials can be up to five orders of magnitude [10]. Figure 5.4 shows the resistivity change with temperature for different class of phase change materials. It can be seen that there is a sudden drop in the resistivity at a particular temperature and this temperature is commonly referred to as crystallization temperature (T_crys). Materials need to be chosen such that the T_crys is high enough to ensure proper retention of the amorphous state for 10 years at the operating temperature of the PCM cells, that is, 85 °C for embedded memory applications and 150 °C for automotive applications. In contrast to the above requirement, the materials must undergo phase transformation in the nano-second regime to meet the memory application requirements. These are very conflicting requirements and a number of different alloy compositions and doping techniques [11] have been studied to identify the desired material composition that meets the specifications of both the retention and speed for nonvolatile memory applications. Recently, a N-doped GST alloy [12] achieved retention at 120 °C for 10 years that meets the requirements for industrial and some automotive applications.

5.3.1.1 Conduction Mechanism and Threshold Switching

The electrical conductivity in the amorphous phase can be described by thermally activated hopping transport [13] as shown in Figure 5.5. A Poole–Frenkel (PF) transport of carriers through traps leads to a current which is linear with voltage for very small voltages and exponential for high voltages. The trap energies are randomly distributed in the band gap of the amorphous material and the PF conduction happens through preferred filamentary paths that have the least overall activation energy [14]. At a certain material-dependent threshold field on the order of 10–100 V μm⁻¹ [15] the resistivity of the amorphous phase change material suddenly decreases by orders of magnitude, negative differential resistance is observed, and so-called threshold switching occurs (Figure 5.2). The mechanism behind threshold switching is still not fully understood and several models have been proposed as a possible mechanism. The Joule Heating model [16] attributes the threshold switching to thermal runaway within the chalcogenide layer. This model is based on a simple observation that the current through the phase change material increases exponentially due to the temperature-dependent conductivity of the phase change material as temperature increases. However, since the speed of switching is faster than the thermal time constant, electronic mechanisms are favored over purely thermal mechanisms [17]. In the Impact Ionization model, for higher electric fields the current rises exponentially due to secondary carrier generation in the amorphous region. The electrons get trapped in the donor-like traps. But as the field increases, all the trap states are filled and the free carrier density increases. The impact ionization overcomes the carrier recombination process, the traps are filled and the voltage snap back occurs. As a result, higher current can flow through the device at a lower voltage and the impact ionization process still happens but with a lower multiplication rate [18–20]. In another electronic model, threshold switching is attributed to energy gain of electrons in a high electric field leading to a voltage–current instability [6]. In the field-induced nucleation model [21], threshold switching is explained based on the electric field assisted formation of crystalline nuclei across the programming region. These crystalline nuclei disappear if the electric field is removed prematurely and would go back to its original amorphous form. There is no experimental demonstration as to which of the above models correctly explains the physics behind the threshold switching. The dominant switching mechanism may depend on the material system and more than one mechanism might be required to explain the experimental observations at different operating conditions or device dimensions. The electrical conduction in the crystalline phase of the phase change material can be described straightforwardly with the drift diffusion behavior of a doped semiconductor resulting in Ohmic behavior at low voltages [18]. NonOhmic behavior of PCM cells for higher voltages can be attributed to Joule heating by the current causing the temperature-dependent resistance to change.

5.3.1.2 Resistance Drift

The phase transformation to the amorphous state is achieved either by ion implantation [22] or by melt-quenching with an electrical/optical pulse. The amorphous state resistance of a PCM cell, measured at a given read voltage is determined by the nature and volume of the amorphous region formed during the reset programming. The amorphous resistance does not remain constant but rather drifts logarithmically with time to a higher value immediately after the reset pulse is removed following the power law R = R₀ × (t/t₀)^ν where R and R₀ are the present and initial resistances, t and t₀ the present and initial times, and ν the drift exponent [23]. This phenomenon is called resistance drift. Figure 5.6 shows the change in the amorphous resistance of a PCM cell over time for different reading temperatures immediately after reset programming [24]. The drift is also a strong function of the temperature [25] and the volume of the amorphous region [26]. Higher temperatures and larger amorphous volumes have larger drift coefficient. The threshold voltage also shows a similar behavior with time [27]. While resistance drift to higher values increases the on/off ratio for two-level memory, it is a major problem for the multi-level PCM implementation [28] because the different resistance levels overlap as time progresses and is no more distinguishable from each other. There is currently no consensus on what causes drift, but there are two major theories that explain as to why drift occurs in PCM. According to the Structural Relaxation (SR) model, drift is explained as a reduction in the number of structural defects (distorted bonds, wrong bonds, vacancies, etc.) that causes an increase in the band gap and of the activation energy for conduction [23,24]. In other words, the density of traps decreases with time due to reduction of the structural defects, causing the trap spacing to increase, which in turn raises the barrier for PF conduction through the trap states. Alternatively, resistance drift is explained as the relaxation of the compressive stress developed in the amorphous phase at solidification [29]. In fact, the density of the amorphous phase is 6.5% lower than the crystalline phase, thus possibly causing a compressive stress after reset programming in PCM cells where the amorphous region is surrounded by a crystalline region. Experimental results on nanowire PCM devices indicate that the drift coefficient decreases with the size of the phase change nanowire [29]. The results also show that the drift exponent is higher for nanowires encapsulated with nitride or oxide, presumably due to the enhancement of the local stress by mechanical confinement. However, a recent study on PCM thin films and devices subjected to external mechanical stress [30] suggests that the resistance drift is primarily due to structural relaxation and not by any mechanical stress relaxation. There is still a lack of proper systematic study explaining the direct impact of mechanical stress on PCM devices and whether there is any correlation between the two theories.

5.3.1.3 Mechanism of Crystallization

When the electric pulse is applied for a sufficient amount of time after the threshold-switching event, the amorphous region is transformed into its crystalline phase provided the temperature reaches above the crystallization temperature, but below the melting temperature; this process is called crystallization. The nucleation and growth processes govern the crystallization kinetics of PC materials. Nucleation involves the formation of small crystalline nuclei in the amorphous matrix, and growth involves the subsequent expansion of the phase front separating the amorphous and crystalline regions. The driving force for crystallization is the gain in free energy below the melting temperature. While similar in bonding structure, common phase change materials are traditionally divided into two categories based on their crystallization kinetics: growth-dominated materials and nucleation-dominated materials [31]. (Figure 5.7) Growth dominated materials are generally related to the family of AgIn doped Sb₂Te (AIST) materials, and are characterized by slow nucleation, but fast growth of crystalline domains. In contrast, the prototypical nucleation dominated material is Ge₂Sb₂Te₅ (GST) where nucleation events happen quickly during crystallization. Nucleation-dominated materials generally fall on the tie-line between GeTe and Sb₂Te₃ whereas growth-dominated materials contain much more antimony. (Figure 5.3) In case of the growth dominated materials, the time it takes for crystallization (t_crys) depends on the size of the amorphous region, while it is independent in case of nucleation dominated materials [31]. It has been shown that, in the case of highly scaled PCM devices, the growth dominated phase change materials enable faster crystallization times because of the smaller amorphous volume [33]. The dynamics of crystallization (phase change) in GST and related systems have been fairly well interpreted in terms of the classical nucleation and growth model developed by Kolmogorov, Johnson and Mehl, and Avrami (KJMA model) [32]. The KJMA model gives the macroscopic evolution of the transformed phase under isothermal annealing condition and has been extended to analyzing transformations under a constant heating rate. Recently [34], a modification involving the introduction of fractal geometry and the Meyer–Neldel rule [132] for thermally activated processes was introduced into the KJMA theory to account for the deviations in the measured physical parameters like Avrami exponent (n) and frequency factor (ν). Further a number of other crystallization models [35,36] have been proposed that considers the effect of percolation effects and local temperature effects in practical PCM devices. For the same target resistance, the type of the programming scheme used can also result in different crystallization times due to the variations in the nature of the amorphous volume formed during the programming [37]. Furthermore, fast crystallization times can be correlated to the structural properties of the phase change materials. Fast switching materials often show a simple cubic or rocksalt structure with random atomic distributions that require little atomic movement to change from the amorphous to the crystalline state [38]. In addition it was found that resonance bonding [39] plays an important role for fast switching of phase change materials [40]. A low degree of ionicity and low tendency towards hybridization is typical of fast switching phase change materials [41]. Recently, it was shown that a small incubation electric field could be used to produce rapid crystallization within a few hundred ps, up to an order of magnitude faster than the conventional crystallization times of >10 ns [42]. This electrical controllability of the crystallization speed is attributed to the temperature rise due to the small incubation field which is sufficient to cause a prestructural ordering of the local cluster of atoms, but still small to start the crystallization process. Recent studies [43] also show that decreasing the grain size of the deposited phase change material can significantly reduce the crystallization time of the cell because of the presence of a large number of broken or loosely bonded atomic structures at the grain boundaries. The process of crystallization has also been studied in different phase change materials [44,45] using density functional simulations to understand different bonding reconfigurations that happens at the atomic level. Hence, understanding the crystallization process and related parameters can guide us to explore novel materials with improved retention and switching characteristics.

5.3.2 Thermal and Mechanical Properties

The programming of PCM is achieved by Joule heating of the phase change layer to temperatures above the melting temperature. The current required to achieve this temperature depends strongly on the thermal properties of the various materials that form the PCM device namely the phase change layer, heater electrode, top electrode and the surrounding dielectrics. The thermal resistance arising from carrier energy scattering in the bulk of the material and the thermal boundary resistance (TBR) arising from scattering in the interface region are the two main mechanisms that contribute to the overall thermal network of the PCM cell [49]. Hence, understanding thermal conduction in thin film phase change materials, thin film electrode materials, and at their interfaces is essential for reducing the programming energy.

The most common thin film thermal conductivity measurement techniques for phase change materials are the 3ω method [50], nanosecond transient thermoreflectance (TTR) [51], and picosecond time domain thermoreflectance [52,53]. Measurements on the common phase change material GST show thermal conductivities at room temperature in ranges of 0.14–0.29, 0.28–0.55, and 0.83–1.76 W m⁻¹ K⁻¹ in the amorphous, rocksalt, and hexagonal phases, respectively [54]. The rocksalt phase thermal conductivity exhibits a slow increase with temperature consistent with other highly defective crystalline materials [52,53]. Recently, high density nanostructured materials have exhibited thermal conductivities as low as 0.05 W m⁻¹ K⁻¹ [55]. Nanostructured phase change regions [40,43] have the potential to offer dramatically reduced programming currents through exceptionally low thermal conductivities. Another key challenge is extending thermal conductivity measurements to the melting temperature, which is notoriously difficult due to the volatility of many phase change materials at high temperatures. These measurements will shed light on the relative electron and phonon contributions in conduction at device operating conditions, informing better material selection. There have been many studies [51,53] of the thermal conductivity normal to GST films (k_normal), but the in-plane thermal conductivity (k_lateral) or the conductivity anisotropy can also be an important factor that determines the programming current. Thermal conductivity anisotropy in thin films can be due to electron or phonon scattering on film interfaces, partially oriented grains or inhomogeneous material quality [56]. Lateral thermal conduction in GST films can also negatively affect the thermal cross talk in high density cells and the programming current of PCM devices, the latter being more pronounced for novel lateral designs. The anisotropy ratio (k_lateral/k_normal) depends on the annealing time and temperature of the deposited phase change films [57] and can reduce the programming current by up to 40% [56].

Much of the heat generated during GST cell switching occurs in the GST bulk and at the bottom electrode interface [58,59]. Coupled electrical–thermal simulations revealed that the programming current of a PCM device decreases by as much as 30% for GST-electrode TBR values of 50 m² K GW⁻¹ [59]. In many PCM designs, significant heat loss occurs through the electrode [60–62] due to the large thermal conductivity of the heater material such as TiN ∼8 W mK⁻¹ compared to the GST ∼0.4 WmK⁻¹ (Figure 5.8). This problem can be alleviated by introducing alternative electrode materials such as C and W-WN_x [62] or by inserting low thermal conductivity TaN electrodes within a TiN electrode [63]. Engineering the electrode to have acceptable electrical conductivity and very low thermal conductivity is a key step toward reducing programming current. Composite electrodes may leverage TBR to increase the device effective thermal resistance.

The large current density and temperature excursion exceeding 600 °C in the phase change layer gives rise to a more pronounced effect of the thermoelectric properties such as the Seebeck effect on the programming properties of a PCM cell. Recent measurements provided evidence of thermoelectric transport in PCM cells through observation of a modification in the amorphous region [64] and the programming condition [65] with the bias polarity. The Seebeck coefficient of Ge₂Sb₂Te₅ films shows strong dependence on temperature and temperature history as governed by the phase purity. It scales with film thickness due to varying degrees of crystallization and phase purity in crystalline GST films [66]. Recent electrothermal simulations indicated nearly a 45% increase and 16% decrease in the peak temperature and programming current, respectively, if thermo-electric effects are considered [67].

From this discussion it is clear that the search for the best phase change material is a multi-parameter optimization process with some seemingly contradictory requirements such as high stability of the amorphous phase at operating temperature, but very fast crystallization of the amorphous phase at switching temperature. Many material parameters will also change with size of the phase change material when devices are scaled to nanoscale dimensions. Much research is still required to understand the fundamental relationship between material composition and structure, and phase change properties for a physics/chemistry-based design of new phase change materials.

5.4.1 Materials Scaling Properties

Nanomaterials have properties that are different from bulk materials of the same composition because surface and interface atoms play an increasingly important role in determining the different material properties. It is important to know how phase change material properties change with size in order to be able to evaluate the scalability of PCM technology. It is predicted that as the volume of phase change material gets smaller, the phase stability characteristics will change. Since PCM relies on the bi-stability of the amorphous and crystalline phases, the technology will only be reliable as long as both states are distinct. It is conceivable that there is a limit to the minimum number of atoms required for the two phases to be distinct, and that there is a minimum size at which both phases are stable under the conditions required for commercial applications.

Scaling studies of phase change materials have been done on thin films, nanowires, nanoparticles, and PCM devices (see [68–70] for overviews). It was found that many properties of the phase change materials do depend on size, in particular below the 10 nm range. These changing properties include crystallization temperatures and times, related activation energies for crystallization, melting temperatures, resistances, and optical and thermal properties. Crystallization temperatures can vary up to 200 °C and can be increased or decreased for very thin phase change films depending on the interface material [71,73] which in turn also significantly affects the crystallization time of the material [73]. Melting temperatures are reduced for thinner films [69], hence potentially reducing the power to melt-quench the material. Electrical resistances on the other hand are increased as film thickness is reduced [72].

While these dependencies increase the complexity of materials optimization they also enable us to tune interfacial properties in such a way that desirable switching properties are obtained. Nanostructured materials such as the multi-layered superlattice-like (SLL) structures have switching properties that are significantly different from the bulk materials [74]. In PCM, higher heterogeneous crystallization rates can be achieved in the nanostructured phase change materials due to their high surface area to volume ratios [75]. Nanoscale active device regions or volume of phase change materials can also have lower phase-transition temperatures than the bulk materials due to greater phonon softening effects [76,77]. Materials with SLL structures have lower thermal conductivities than the bulk materials with the same composition [78]. They also have favorable thermal confinement properties due to the phonon scattering effects at the interfaces [79]. Phase change materials with SLL structures can be formed by alternating layers of Sb₂Te₃ and GeTe, which have fast switching speed and good data retention, respectively [78,80].

Recently, a superlattice-like structure of GeTe/Sb₂Te₃ of thicknesses between 5 Å and 40 Å was used to fabricate a PCM cell called Interfacial PCM (IPCM) [40], (Figure 5.9) that shows excellent endurance properties and requires an order of magnitude lower switching energy than the conventional single layer GST cells. These excellent switching and endurance properties of IPCM is due to confinement of the atomic movements to a single dimension, that is, the interface between GeTe and Sb₂Te₃ controls the local atomic switching of Ge atoms resulting in a phase transition with substantially reduced entropic losses. The ultrathin, uniform stratum of Sb₂Te₃ and GeTe lowers the entropy of the covalent amorphous state by restricting the number of atomic configurations that can exist. For the SET operation, IPCM-based devices use only 12% of the energy required by similar GST-based devices. This increase in efficiency means less energy is dissipated during the phase transition, which in turn leads to more than an order of magnitude improvement in the SET–RESET cyclability. Reducing the entropic losses has further ramification of producing highly repeatable device characteristics. Indeed, the resistance of the IPCM during the SET–RESET cycle is identical over a million cycles.

Engineering the grain-size of the as-deposited phase change material can also result in improvements in switching speed and reduced switching energy. GST with small grain sizes have high interface area to volume ratios, which can promote hetero-crystallization (interfacial growth) at the grain interfaces or boundaries [81]. These can alter the phase change mechanism of GST from a nucleation-dominated mechanism to a growth-dominated mechanism, enabling faster crystallization. The increased number of grain boundaries also decreases the thermal conductivity of GST [56]. This increases the thermal confinement in cells, thus reducing the power needed for RESET. The large surface to volume ratio in these materials also facilitates stress relaxation after RESET and hence results in a lower resistance drift compared to the bulk GST. Overall, the scaling properties of nanostructured phase change materials are promising for the development of the fastest and the most efficient phase change memory devices that will be required to meet the demands of the future technology.

Phase change nanoparticles offer another intriguing way of understanding the scaling properties of many chalcogenide materials. A number of techniques have been used to synthesize nanoparticles, including pulsed laser ablation [82,83], electron-beam lithography [10], selfassembly-based lithography techniques using sputter deposition [84,85] or spin-on phase change materials [86], and solution-based chemistry [87]. Large nanoparticles show properties similar to bulk, but the small nanoparticles below 10 nm show size-dependent properties such as higher crystallization temperature and reduced melting temperature. Both are beneficial for PCM applications and illustrate the favorable scaling properties of phase change materials. GeTe nanoparticles can be synthesized in the amorphous phase and can be crystallized by heating them over their crystallization temperature (remarkably increased compared to bulk) for nanoparticle sizes as small as 1.8 nm [87]. As such, GeTe nanoparticle is a convenient material for exploring the ultimate size limit of PCM. Figure 5.10 shows transmission electron microscope images of these GeTe nanoparticles of various sizes. Down to these small sizes, phase change materials still show phase transformation. These nanoparticles are as small as about two to three times the lattice constant, so this will be close to the ultimate scaling limit of phase change technology as far as the phase change materials themselves are concerned.

The future challenges for the material scientists from the technological standpoint will include exploring phase change materials that do not exhibit void formation or elemental segregation, tailoring the increasingly important interfaces that support high cyclability, good data retention, and fast switching, and continuing the study of scaling properties of phase change materials as dimensions shrink to the few-nanometer length scale.

5.4.2 Device Scaling Properties

While it has been established that phase change materials (e.g., GeTe) can exist in two stable phases, it is still necessary to explore how the memory device characteristics may behave when PCM are scaled to nanometer size. The active device area of the phase change memory needs to be scaled every year in order to meet the demands of the increasing device density. Furthermore, device scaling has the advantage of reduced programming power. Table 5.1 summarizes the scaling rules for both isotropic and aggressive scaling. There are two major device properties that are significantly affected by the scaling of the active device, namely the threshold switching voltage and the reset current. Several device structures and methodologies have been used to understand how scaling affects these device parameters and will be discussed below.

5.4.2.1 Threshold Voltage Scaling

The present models for threshold switching are based on the inter-trap distance [13] or the minimum distance that the carriers have to travel to cause impact ionization [18]. It is not clear how threshold switching properties will change when the film thickness becomes comparable to either of these distances. A number of device structures ranging from phase change bridge cells to electrodes of carbon nanotubes have been used to study how the threshold voltage scales as the size of the active programming region decreases. In [88], an additional top electrode was introduced in the GST layer at a specific height from the bottom electrode of the PCM cell to confine the programming volume to a specified thickness. It has been shown that the threshold switching voltage linearly increases with GST layer thickness with a nonzero offset. In the case of nanowire PCM devices [75,89] the threshold switching voltage scaling changed from constant field to constant voltage scaling with the length of the amorphous region below 10 nm. The phase change bridge (PCB) device is another cell design uniquely suited to study the electrical scaling characteristics of phase change materials [90]. It comprises a narrow line of thin phase change material bridging two underlying electrodes. The PCB structure is ideally suited for a variety of characterization experiments [15,91]. For instance, in Figure 5.11 the critical field necessary for threshold switching for different materials has been obtained by plotting the measured threshold voltage of the PCB device as a function of the device length. The threshold fields for Ge₁₅Sb₈₅, Ag- and In-doped Sb₂Te, Ge₂Sb₂Te₅ and 4 nm thick Sb devices are 8.1, 19, 56, and 94 V μm⁻¹, respectively. Recently, carbon nanotubes (CNTs) with diameters of ∼1 to 6 nm were used as electrodes to reversibly induce phase change in nanoscale GST bits [92]. The study also demonstrates reversible switching with programming currents from 0.5 to 8 μA, two orders of magnitude lower than state of the art PCM devices. The active device area is the small nanoscale gap formed in the middle of the CNTs through electrical breakdown [133]. By controlling the breakdown voltage, gaps ranging from 20 to 300 nm was formed. Threshold voltages scale proportionally to the size of the nanogap, at an average field of ∼100 V μm⁻¹ for GST material.

5.4.2.2 Reset Current Scaling

The large programming current is still a key issue that limits the adoption of PCM in many applications. Furthermore, a large programming current in PCM imposes a stringent requirement on the current delivered by the memory cell selector integrated in series with the PCM. In order to provide the current required to switch the states of PCM, the area of the memory cell selector may not be scaled down as fast as the memory cell itself, thus the size of the cell selection device becomes the limiting factor for device density and annihilates the small size advantage of PCM technology. Therefore, reducing the programming current is necessary for achieving both high density and low power consumption of PCM.

To decrease the reset current, one way is to increase the heater thermal resistance by reducing the contact area [4]. The feature size of the conventional mushroom structure (Figure 5.1) of PCM is limited by lithography and process capability. This was recognized early on and many innovative device structures have been explored to reduce the effective bottom electrode contact (BEC)/GST interface to the sub-lithographic regime. Figure 5.12 shows the reset current reduction as a function of the equivalent diameter of a circular contact and the effective contact area for different cell structures, such as conventional mushroom type [93], edge contact type [94], μTrench [95], cross-spacer PCM [96], “wall” structure [97], “pore” structure [98], ring type contact [99], and dash-type confined cell [100]. We can clearly see that the reset current scales with the effective contact area of the PCM and that a constant current density ∼40 MA cm⁻² is required to program an average PCM cell. Those with carefully engineered cell structures and materials can be programmed using ∼10 MA cm⁻². Recent demonstrations of PCM devices using CNT as the electrodes [92,101] show extreme scalability of the reset current down to 1 μA range. These PCM devices have an active area of only a few nm² because CNT diameters are only about 1–2 nm. They demonstrate typical electrical switching characteristics that are observed in larger devices. This shows that, the scalability of the phase change material properties can also be observed in practical device configurations [101] and hence providing for a viable technology that can extend the semiconductor memory device scaling for several generations.

5.5.1 Multiple Bits per Element

Multilevel cell (MLC) storage is essential for reducing the cost per bit of PCM technology and for increasing its potential for market acceptance. The large resistivity contrast between the crystalline and the amorphous state of the phase change materials and the ability to access the intermediate states in a reliable way have made possible the realization of multi-level implementation in PCM. Some of the earlier methods of MLC implementation are based on engineering the properties of the chalcogenide layer by doping [102,103] or by stacking multiple layers with differing electro-thermal properties as the storage medium [104–106] or by using parallel combination of multiple resistances [107,108]. These demonstrations thus depended on precisely engineering the cell structure to achieve the intermediate resistance states. However, even conventional cell structures such as the common “mushroom” phase change element could be programmed to store multi-bit data by altering the size of the amorphous region in a continuous manner to achieve different resistance levels. The size changes as a function of the amplitude of the write pulse, as quantified by the cell's programming curve shown in Figure 5.13a. However, process and material variations give rise to resistance levels with broad distributions when single programming pulses are applied. A common solution is to employ iterative programming schemes, in which a sequence of write and verify steps is used in a feedback loop to minimize the error between the programmed and a specified target resistance level. A basic iterative scheme is shown in Figure 5.13b. It was shown that by varying the amplitude or slope of the trailing edge of the programming pulses to control the evolution of temperature in the cell, up to 16 intermediate levels could be programmed in a cell, thus demonstrating a four-bit cell [109]. These programming techniques are based on the fact that the cell resistance R_cell can be increased by applying programming pulses of larger amplitudes that result in melting of larger volumes of the amorphous region (partial RESET), or can be decreased by applying pulses of lower amplitude (partial SET), or sequences of annealing pulses of appropriate magnitude to crystallize and shrink the size of the amorphous volume [110]. A novel iterative programming scheme that uses both partial-SET and partial-RESET pulses is depicted in [111]. Operation starts from the partial-SET regime and either terminates there if the target resistance is reached, or switches to the partial-RESET regime if the programmed resistance drops below the target level. This hybrid method combines the low energy dissipation of the partial-SET regime with the flexibility of achieving higher or lower resistance level using the partial-RESET regime.

Regardless of how much efficient the MLC scheme can be in producing tight and dense resistance distributions, the resistance drift adversely affects the reliability of MLC storage in PCM, because the distance between adjacent levels is small and stochastic fluctuations of the resistance are more likely to cause level overlap over time than in binary storage. Currently there is no known material solution to mitigate the effect of drift, as the physics of drift in itself is not well understood. However, a novel drift-resilient MLC PCM state metric has been proposed for MLC programming that is largely robust to the impact of drift [112]. Traditionally, the low field resistance is used as a metric to define the different MLC levels. This resistance value is a strong function of the activation energy (E_a) and suffers a large change as E_a changes with time during the drift phenomenon [28]. Instead, what is required for drift-tolerant MLC is a cell state metric that has minimal dependence on the activation energy, but has a linear relationship to the amorphous thickness. To achieve this, the read voltage is progressively increased until a certain predefined current level I_R, is reached. This current level is chosen to be a safe value much below the current needed for threshold switching to occur. The time needed to reach I_R can be considered as a measure, M of the programmed state. It is shown that M is proportional to the effective amorphous thickness [112], yet it is a weak function of the activation energy (nearly linear as opposed to exponential), suggestive of a significant tolerance to drift. Experimental results suggest that the new metric has an order of magnitude smaller drift coefficient than the standard resistance metric. In another approach, the effect of drift on the selected cells was predicted by using reference cells that have similar thermal history and undergo same drift behavior [113]. Another way of mitigating the impact of drift on the resistance levels is by using an additional annealing pulse to accelerate the drift immediately after the reset programming [114,138]. This additional pulse quickly anneals out many defects (that are responsible for the drift) and provide a drift-free period that enlarges the read window. This technique not only reduces the read latency but also enables a more reliable read window for multi-level applications.

5.5.2 3D Stackable Memory

A vision for high density memory is the cross-point architecture with a memory cell integrated with a cell selector within a 4F² footprint that can be stacked in the third dimension Figure 5.14. To realize this, the selector should have a 4F² footprint that can be scaled with the bitline/wordline pitch [134,135], a small off current, and an on-state current that is sufficient for programming the memory (the reset current for the case of PCM). Furthermore, the fabrication process should be compatible (e.g., material and process temperature) with CMOS BEOL and the memory cell. The trend for the reset current in Figure 5.12 shows an average of 40 MA/cm² with the lower bound of about 10 MA/cm². This large current is fairly difficult to achieve even for single crystal silicon diodes. A number of recent efforts have been made to integrate a memory cell selector with a phase change memory cell. Sasago et al. [93], used a low-thermal budget process to fabricate a 4F² poly-Si diode with a drive current capability in excess of 8 MA cm⁻² and on-off ratio more than 10⁴. Kau et al. [115] used a stackable cross-point phase change memory utilizing the Ovonic threshold switching (OTS) property of chalcogenide materials to make the memory cell selector. Since both the memory device and the selector exhibit threshold switching behavior, the programming voltage conditions have to be carefully chosen to avoid disturbing the state of the cells in the un-selected bit and word lines. Gopalakrishana et al. [116], proposed an access device based on Cu ion motion in novel Cu containing Mixed Ionic Electronic Conduction (MIEC) materials. These MIEC-based devices can be fabricated at <400 °C, are scalable, and can conduct very high current densities (up to 50 MA/cm²) – making them suitable for stacking of multilayer PCM arrays in the BEOL. Sasago et al. [117] proposed another stackable access device structure in which the phase change layer is directly deposited on top of the channel poly-Si layer (Figure 15.5a). This contactless, simple memory-cell configuration enables a poly-Si MOS-driven 4F² stackable memory array with low fabrication cost and smaller programming current. In an effort to demonstrate a true 3D PCM memory, Kinoshita et al. [120], showed a scalable 3D vertical chain cell type phase change memory (VCCPCM) with 4F² poly-silicon diode, as shown in Figure 5.15b. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. Each memory cell consists of a poly-silicon transistor and a phase change layer connected in parallel. The memory cells are connected serially in the vertical direction. The excellent scalability of the new phase change material used in VCCPCM while retaining a reasonable crystallization temperature makes it possible to reduce the cell size beyond the scaling limit of flash memory.

5.6.1 PCM as a Storage Class Memory

Historically, device scaling has resulted in the benefit of both cost reduction and performance improvement for the computing systems and hence the unrelenting focus on the processor performance and logic device scaling was justified. However, due to power constraints in the processor and the diminishing returns of the performance advantage of logic device scaling, it is important to seek other areas of improvement through which we can continue to enhance the overall system performance. Of these, the most important one is the memory storage hierarchy. The major bottleneck today is the large gap in the access time between the magnetic HDD and the DRAM main memory [121,122]. There are no major technologies on track to improve the access times of the HDD in the near future. Because critical computing applications are becoming more data-centric than computer-centric, a high-performance, high-density, and low-cost nonvolatile memory technology whose access time falls between that of an HDD and the dynamic memory located near the processor would significantly improve the overall system performance while keeping the cost low. This class of memories is referred to as the Storage Class Memories (SCM) [121]. Figure 5.16 shows the different memory hierarchies that form a part of the computing system. The SCMs can fit in the memory hierarchy between the main memory and the HDD.

Of all the other emerging technologies, PCM is in the most advanced stages of meeting all the requirements for the SCM that companies are considering to include it in the memory hierarchy to improve the performance of their high-end systems [123]. The access time, endurance and retention properties of the PCM [124] are well within the requirements of the SCM. As compared to Flash, PCM can do in-place updates (it is bit-alterable) and there is no need to first erase a whole block before one can write new data. Instead of 10⁵ (or even lower) write endurance cycles, PCM has more than 10⁹ write endurance cycles. All these add up to reducing a lot of the overhead in the memory controller to keep track of where the written bits are, doing garbage collection, and wear leveling that is required for Flash. A prototype high-performance solid state drive using PCM [136] is shown to be 72–120% faster than Flash for small write and for all reads and incurs 20–51% less CPU overhead per IOP (Input Output Processor) for small requests. In another hybrid main memory system using phase change memory in conjunction with a small DRAM buffer [137] it was found that for a 16-core 8 GB DRAM baseline system, this hybrid PCM design reduces page faults by 5× and speeds up the system by 3×.

In addition, the major issues of having a 4F² access device and reducing the programming current are also being addressed. Recently, there were demonstrations of several large scale Gb array demonstrations of PCM using 4F² poly-Si diode [118,119]. If this trend in the technology improvement of PCM continues, then in the next few years we may be able to see commercial computing and mobile systems that contain PCM chips as a part of their memory hierarchy.

5.6.2 PCM as an Electronic Synapse

The ability to gradually program the cell into its SET or RESET state or in other words the ability to change the conductance of the device gradually makes PCM an excellent candidate to mimic the synaptic elements in the brain. Human brain predominantly consists of two main units, namely the neurons and the synapses that connect these neurons (Figure 5.17a). These synaptic elements have a certain behavior called Spike Timing Dependent Plasticity (STDP) wherein the conductance of the synaptic element changes based on the difference in the arrival time of the pulses or spikes from the post- and presynaptic neurons; that is, the conductance of the synapse increases when the prespike occurs before the post-spike and the conductance decreases when vice versa, as shown in Figure 5.17b. This particular behavior of the synapse is found to be one of the major factors that help in the process of learning and perception in brain [125]. PCM devices can be programmed in such a way that the pre- and postspike arriving at the two opposite terminals of the device can modulate the conductance of the device [126–128]. Thus PCM can act as an electronic synapse that connects neuron circuit elements (built with CMOS for instance) in a system architecture that closely resembles the brain. One implementation is to use a crossbar-like architecture that connects the different synaptic elements to the neuron circuits, with the top and bottom metal lines providing the pre- and postspike. Kuzum et al. [126] proposed a specific spiking scheme to translate the spike arriving timing relationship into PCM programming pulses. This enables the PCM to mimic the synaptic STDP behavior. The spiking scheme and the TEM cross-section of the nanoelectronic synapse used are shown in Figure 5.17c,d. Another pulsing scheme was also proposed in [127], where single pulses are used as opposed to multiple pulses as in Figure 5.17c to reduce complexity of neuron circuits and potentially energy consumption. The eventual goal is to build an array of synapses and neurons to emulate different learning functions. Another application example of PCM in cognitive computing was shown by Suri et al. [128]. A 2-PCM configuration was used in which the depression of the synapse is emulated by gradual SET of one cell, and potentiation is implemented by gradual SET in the other cell. Hence the energy consumption on the system level can be reduced since the RESET pulses are replaced by SET pulses, which consume less energy. Besides, this can be used when RESET process is abrupt due to device design or material composition required, given that gradual SET can be performed. However, this configuration occupies larger area than a one-cell synapse and requires a separate control to RESET both cells regularly while keeping the synaptic weight. Besides single synaptic device level experimental demonstrations, array level brain-like associative learning has also been experimentally implemented with phase change memory devices [129]. It was shown that for cognitive computing applications, resistance variations can be tolerated at the expense of energy consumption [130].

PCM technology has the promise to build human-scale intelligent systems which has not been possible so far due to lack of energy and area efficient hardware. Energy efficient artificial neural networks that can perform complex tasks with large amounts of inputs and variables can be made possible due to low energy consumption and nano-scale feature sizes of PCM technology. In a possible implementation, PCM devices can be deposited on top of CMOS neuron circuits. Several challenges such as process integration, RC delay, thermal disturbances and architectural problems should be addressed for such a configuration. Device models suitable for neuromorphic architectures are still needed for application-specific performance evaluations of these systems.