21.2.1 An “In-Plane” Device Architecture

NML processes information via coupling between neighboring, nano-scale magnets. Most work with NML has focused on devices that couple in-plane (denoted iNML, see schematic in Figure 21.2a). (Recent work has also employed devices with out-of-plane, perpendicular magnetic anisotropy (PMA); this device architecture will be discussed in Section 21.2.2.).

Since 2010, experimental progress (driven in part by our research group at the University of Notre Dame, as well as other groups at UC-Berkeley [23], VCU [24], South Florida [25], Minnesota (UMN) [26], and so on who are now studying NML) suggests that it is possible to move beyond isolated line and gate structures (e.g., the majority gate as shown in Figure 21.2b [19]), and toward more functional, circuit-level structures. Notably, fanout structures [20,21], a 1-bit full adder [27], and so on have been experimentally demonstrated and successfully re-evaluated with new inputs. Both field-coupled [28] and spin transfer torque (STT) [26,29,30] electrical inputs have been realized. For electrical output, multiple NML-magnetic tunnel junction hybrids [31–33] have been proposed and simulated.

Externally supplied switching energy is needed to re-evaluate (or clock) a magnet ensemble with new inputs. To modulate the energy barriers of iNML device ensembles “on-chip,” [34] proposed using hard axis directed magnetic fields from current driven wires. Ensembles of magnets could be grouped in clocking zones. Figure 21.2c illustrates the effects of the clocking field. From the initial state in Figure 21.2c,i, magnets in clocking zones N and N + 1 are put into a metastable logic state (i.e., along the hard/short axis) against the preferred shape anisotropy (Figure 21.2c,ii). If a driving neighbor (i.e., in zone N − 1) provides a y-directed biasing field, the driven magnet's magnetization rotates toward a preferred easy (long) axis. When the clock is removed, magnets should relax to a new, low energy ground state (Figure 21.2c,iii) in order. Clock energy could be amortized over hundreds of thousands of devices as a single clock line could control many parallel ensembles. Fringing fields from devices themselves also help with the transition to the 0/metastable state in Figure 21.2c,ii. As such, the magnitude of the required clock field (and current) need not be excessively high [34,35], and this approach to clocking could lead to performance “wins” at the application level [35–37]. Notably, proposals for line clock structures [34] were experimentally realized and used to flip the state of single magnets [38], as well as to re-evaluate lines and gates [22]. Moreover, recent experimental results [37,39,40] suggest that materials-based solutions could allow for further reductions in clock wire current.

iNML devices should also be amenable to voltage-controlled clocking, and multiferroics [41] and magnetostriction [24], have also been proposed as potential iNML clocks. Multiferroic materials (e.g., BFO) could allow for electric field control of magnetism [41]. uses multiferroic materials to demonstrate the switching of an in-plane ferromagnetic component (i.e., a nanomagnetic island). Also, [24] considers how the magnetization state of a multiferroic nanomagnet can be rotated via the coupling between a magnetostrictive layer and a piezoelectric layer. This work suggests that only 10 s of millivolts are needed to induce a rotation of 90° into a metastable state, and that stress-based clocking would lead to clock energy dissipation of just ∼200 kT per device.

If voltage-controlled clocking becomes feasible, it would almost certainly be the preferred approach for iNML clocking. When looking toward circuits and systems, potential advantages include reductions in clock energy [24], and more fine-grained control of an NML ensemble (useful architecturally as discussed in [42], and Section 21.3.1.4 of this document). That said, many of the architectural ideas discussed here are by in large amenable to current or voltage-controlled clocks – particularly as both clocking approaches place devices in metastable states for re-evaluation (a potential source of error that will be considered in Section 21.5).

21.2.2 An “Out-of-Plane” Device Architecture

A pNML device schematic is shown in Figure 21.3a. Thin PMA nanomagnets switch through nucleation and domain wall propagation [43,44]. Irradiation or ion milling could be used to define a “soft spot,” where a domain wall may nucleate. The nucleated wall subsequently propagates through the dot, fully reversing it. The coercivity of the magnet is determined by the coercivity of its highest-irradiated region. This reversal behavior is markedly different from in-plane permalloy nanomagnets, which remain nearly single-domain during switching and rotate coherently (through a 0/metastable state as described above).

Both computational [45] and experimental [46] results suggest that appropriately irradiated pNML structures can be controlled by a uniform, homogeneous, oscillating, global clock field. Consider the antiferromagnetically (AF) ordered line schematic in Figure 21.3b. Here, we (i) refer to the period of the sinusoidal, out-of-plane field as T_pulse with peak amplitude of H_pulse, and (ii) assume that dots are FIB irradiated on their left edges, so information will flow from left to right. After the first application of H_pulse (in the +z direction), the dot immediately adjacent to the flipped input will change state after 0.5 T_pulse. Switching occurs as H_pulse is of sufficient magnitude to eliminate parallel alignment in the dot pair at the input, but not of sufficiently high magnitude to alter the state of other dots in the line. (Again, irradiation location determines which dot will switch.) With successive applications of the time varying field, multiple bits of information can move through an AF-line segment simultaneously, and an inherent pipeline is created. Notably, majority gates [47], AF-lines [46], and full adders [48] comprised of multi-layered pNML devices have all been experimentally demonstrated.

When considering experimental realizations of “on-chip” clocks, large arrays of pNML devices could be controlled with on-chip inductor structures [49] that could be coupled with a capacitance in an LC oscillator – which opens the door to adiabatic energy recycling. pNML devices are also amenable to voltage-controlled clocking. Recent experiments suggest that it should be possible to change the easy axis of patterned CoFeB layers with PMA from out-of-plane to in-plane with modest voltages [50]. As such, a pNML device would transition through a metastable state with this clocking approach.

21.3.1 Boolean Logic

Here, we consider the prospects for the NML device architecture when using NML devices to realize random, combinational logic blocks – for example, that might be used in a general-purpose microprocessor. We begin by discussing the pros and cons of the iNML and pNML device architectures (Sections 21.3.1.1–21.3.1.4), and conclude with an effort to quantitatively benchmark NML logic against CMOS equivalents. In Section 21.3.1, we will use an adder as a running case study.

21.3.1.1 Less Complex Signal Routing

When considering the layout of an iNML circuit, assuming a Cartesian grid, data will propagate through AF-ordered interconnect when moving in the ±x direction, and ferromagnetically (F)-ordered interconnect when moving in the ±y direction. As such, the x dimension (i.e., the width) of every device must essentially be fixed in order to allow for transitions between AF-ordered and F-ordered lines. Theoretically, this construct could be relaxed. As per Figure 21.4a, a line comprised of five devices that are each 60 nm wide, with 10 nm spacing between devices will have the same length as a line of seven devices that are 40 nm wide with 10 nm between devices. However, varying the size/aspect ratio of devices is difficult as: (i) clock field requirements can change significantly [51], (ii) very precise lithography would be required, (iii) variations to width are also limited in that we need to ensure devices remain single domain, and (iv) fringing fields from a smaller device may be insufficient to “drive” a larger device.

Assuming iNML devices of constant size, transitions between F-ordered and AF-ordered interconnect can prove to be problematic when considering concatenated gate structures. As an example, consider a majority gate-based, one-bit full adder (see schematic in Figure 21.4b). Note that in this design, the carry input signal is fed to gates M1 and M3, while the complement of the carry signal is fed to gate M2. Also, the complement of M1 is required as an input to M3. Given the combination of AF- and F-ordered interconnect, obtaining the proper signal value at the desired gate input is difficult to achieve.

As a representative example, consider an iNML-based schematic of the 1-bit adder shown in Figure 21.4c. To better illustrate potential routing issues, we have made explicit copies of the A, B, and C inputs at each gate. If a single copy of the C input were to fan out to gates M1, M2, and M3, M1 and M2 would receive the wrong value. Using M2 as an example, the C input to gate M2 should have a negative y component of magnetization, but instead would have a positive y component of magnetization via F-ordered interconnect. While carry signal routing might be addressed by eliminating one magnet from the middle C input, the input to M3 would then be affected. One solution to this problem could be to create a staggered transition between AF- and F-ordered interconnect (see Figure 21.4c inset), and physical-level simulations suggest that such a structure may function properly, but this idea is unproven experimentally.

That said, this problem is much easier to address with pNML given that: (i) both x- and y-directed interconnect are AF-ordered, and (ii) that it is possible to vary the size of a given device. A potential pNML-based schematic of an adder appears in Figure 21.4d. By changing the size of the device that serves as the M1 and M2 input to M3, desired signal values can easily be routed to a given gate. While larger device sizes could impact the required length of T_pulse, ensembles with mixed dot sizes have been experimentally demonstrated [52], and thus no new constructs are required. Notably, magnets could be on the order of one micron long [53].

21.3.1.2 Data Races

Upon closer examination of Figure 21.4d, one might wonder whether or not “data races” could occur. Consider the input paths to M3. There is essentially just one (albeit larger) device between the output of gate M1 and the decision device in M3, there are two devices between the carry input and the decision magnet of M3, and there are two devices between the output of M2 and M3's decision magnet. (This does not even account for critical path differences given the initial evaluations of M1 and M2.) Thus, at issue is whether or not different signal arrival times will impact logical correctness.

For iNML, this is a potential concern. The success or failure of a gate is largely a function of clocking – for example, whether or not devices switch in a soliton-like fashion or devices switch in the presence of an applied clock field. With soliton-based switching, all devices in a circuit ensemble are placed into a 0°, metastable (MS) state – for example, by a clocking field. The external field is removed, and each device in the ensemble is expected to remain in a hard-axis-biased state until set by an appropriate neighbor. (While this is an unstable state of the system, dipole fields from neighboring magnets do help to preserve it [23].) All inputs to the ensemble are set, and easy axis directed fringing fields from said inputs cause neighboring devices to switch. Fringing fields from these devices then set the state of the next neighbor, and so on.

In [23], the authors noted that thermal noise could induce premature, random, and unwanted switching. To combat this problem [23], suggested fabricating magnetic islands with a magnetocrystalline biaxial anisotropy – that is, such that U(θ) becomes K_u cos²(θ) + ¼K₁ sin²(2θ), where K₁ is the biaxial anisotropy constant. The biaxial anisotropy term introduces a local minimum in the energy landscape of an individual magnetic island at 0° – which should further promote the hard axis stability of the ensemble. Given the effects of thermal noise at T = 300 K [23], reports that a line of hard-axis biased devices with a biaxial term remained in a 0°/MS state until a device was set by an appropriate neighbor, when a device without the biaxial term did not.

In [54], Spedalieri et al. extended the work of [23] and considered the switching behavior of a suite of majority gates with biaxial anisotropy. The clocking scheme assumed in [54] was similar to the approach used in [23] (and explained above). Notably, assuming gates comprised of 30 × 15 × 6 nm magnets, the gate error rate can exceed 15%. The most common errors observed were: (i) premature switching in randomized islands due to thermal noise and (ii) gates where devices essentially remained hard-axis biased (due to a biaxial constant/biaxial anisotropy that was too large).

It was also shown that sufficiently strong coupling fields in the case of pNML [68] or sufficiently small clocking zones in the case of iNML [69] reduce error rates to an acceptable level, where circuit-level solutions can be used for eliminating errors.

Alternatively, magnets can also be driven to a new, logically correct state before a clocking field is removed. [55] reports gate simulations where inputs do not arrive at a decision magnet simultaneously, but the gate still functions correctly. The clock field is applied until all signals arrive at the compute magnet, and it has time to respond. (The clock field prevents a decision magnet from relaxing prematurely.) While this approach to switching may prevent race conditions, it will also: (i) result in an increase in clock energy and (ii) make successive devices in a group weaker drivers, eventually limiting the width of a clock line.

As with signal routing, managing potential data races can be much easier with FIB-irradiated pNML. To illustrate, consider the majority gate (with some initial state) shown in Figure 21.5. As before, we will assume an out-of-plane, sinusoidal field as shown in Figure 21.3b. Now, assume that the top and middle inputs to this gate change state (see Figure 21.5b). The time evolution of the gate is shown in Figure 21.5c–j. Even though the output of the gate changes state after the new, middle input arrives (Figure 21.5f), it changes back to the logically correct state after the new, top input arrives (Figure 21.5i). As the middle input is unchanged, no metastabilities in the second input arm appear, and the compute device is allowed to react to all inputs.

Finally, consider an NML ensemble where multiple levels of logic are connected together. Using the above gate as an example, if we define T_clock to be NT_pulse (Figure 21.5j), where N is defined by the longest critical path through a bit slice, we can synchronize the application of new inputs in successive bit slices to ensure that a well-timed circuit (and logically correct output) is achieved.

21.3.1.3 Pipeline Depth

For iNML, a multi-phase clock is required to define dataflow directionality through a magnet ensemble (Figure 21.2c). However, controlling an iNML ensemble with multiple clock lines – for example, an extended AF-line segment like that shown in Figure 21.6a – results in an inherent pipeline, which will improve circuit throughput. More specifically, every time data propagates completely through a clock group, a new input can begin to traverse the same group. Essentially, a new value can be written into or read out of our AF-line/shift register every time the last wire cycles through all ϕ phases (where ϕ would equal three for a three-phase clock). The magnets overlaid on top of N wires (where N is the number of clock phases) represent a bit of information (see Figure 21.6a).

Assuming a line clock, the number of magnets per pipe stage will ultimately be limited by the width of a given line (see Figure 21.6b). Practically, this cannot be arbitrarily small as narrow clock wires will: (i) have a much higher resistance which will adversely affect clock energy and (ii) making very narrow, clad lines (i.e., less than 100 nm wide) with good field confinement will obviously become prohibitive. This is not to say that a bit of information could not traverse multiple gates within a given group, but only one bit could be stored per AF-ordered line that traverses a given group (Figure 21.6a).

We reiterate that other approaches for clocking iNML are also being studied. As noted earlier, potential advantages to electric field-based clocking include additional energy reductions, and more fine-grained control of an ensemble – which could lead to deeper pipelines. (It should be noted that a potential disadvantage of the aforementioned clocks is that every device may need to be contacted individually, which would increase fabrication complexity.) That said, in a pNML ensemble, pipe depth could be completely independent of clock feature size, and devices do not need to be contacted individually (i.e., assuming domain wall switching modes). Regarding fabrication and throughput, this would obviously be advantageous.

21.3.1.5 Benchmarking

Here, we briefly discuss energy and performance metrics for iNML and pNML adder designs. We begin by considering recent results from the NRI's architectural-level benchmarking efforts led by Nikonov and Young – where multiple devices were evaluated assuming a common set of fabrication parameters and circuit-level benchmarks (see [56] for more detail). Note that as only the iNML device architecture was rigorously vetted through the NRI, only results that project the energy, delay, and throughput of iNML current and voltage-controlled 32-bit adders are discussed below. (The adder design used in [56] is based on the design in Figure 21.4c.) That said, we do conclude this subsection by briefly comparing and contrasting the iNML and pNML adder designs in Figure 21.4c and d.

We particularly wish to highlight the impact of inherent pipelining on an iNML-based adder's performance/energy/throughput. Notably, the NRI's benchmarking analysis “[does] not incorporate any pipelining in [these] calculations, even though some logic technologies are not constrained by power dissipation may produce higher computational throughput by pipelining.” As per the discussion above, NML circuits could (and should) be inherently pipelined with no overhead. Thus, as per Figure 21.7a, computations in an adder could overlap. If we conservatively assume that 10 adds are active simultaneously, as per Figure 21.7b and c, (generated via the code associated with [56]) the energy–delay products of iNML adders improve and become competitive with low power CMOS. Furthermore, standby power effects, intangibles regarding operating environments, and so on could represent added benefits. Moreover, as per Figure 21.7d, the throughput per unit area of an iNML adder (quantified as peta-integer operations per second, per square centimeter) moves into the most desirable area of the plot.

Finally, the pNML device architecture could offer additional advantages. When comparing the adder design schematics in Figure 21.4c (iNML) and Figure 21.4d (pNML) the number of devices in the critical path in the pNML design is 6 less than the iNML design (8 vs. 14). Furthermore, even if iNML devices with 20 × 30 nm footprints were employed, the area of the one-bit design would be essentially the same as a pNML design comprised of devices with 50 × 50 nm footprints and 50 × 100 nm footprints (i.e., 0.133 μm² for iNML vs. 0.136 μm² for pNML). (Differences can largely be attributed to ease in signal routing.)

21.3.2 Systolic Arrays

Here, we consider alternative, system-level architectures (e.g., nonVon Neumann architectures) that might employ NML devices to perform Boolean logic functions. Of particular interest are architectural approaches that can exploit deeply pipelined logic, and avoid large-scale interconnect.

21.3.2.2 Toward NML Implementations of Systolic Architectures

The fundamental processing element (PE) in a systolic PM circuit appears in Figure 21.8a. Individual bits of a data stream serve as one input to an XNOR gate. The other input to the XNOR is a bit (b_i) of a pattern of interest. (This bit of information could be stored directly at the gate in a nonvolatile, NML device. We are investigating the use of spin transfer torque (STT) to program the b bits.) If the bits match, the output of the XNOR gate is a logic 1; otherwise a logic 0 results. This output then becomes one input to the AND gate – the output of which captures the global history of multiple, concatenated PEs. If at any point the output of an XNOR gate is a 0, the accumulated global history is set to 0, which suggests that there is no match in input stream bits x_m…x_m+n (see Figure 21.8b).

More specifically, when a computation commences, bits from the input data stream (x₀…x_n) flow through the sequence of PEs (i.e., from left to right, as per Figure 21.8). When the first input bit (x₀) arrives at the rightmost PE (PE₀ in Figure 21.8c), initialization is complete, and streaming data analysis can begin. Thus, bit x₀ would be compared to bit w₀ via an XNOR operation, and the output of this gate would then be ANDed with the input signal y_in – initialized to logic “1.” This “global history” is then shifted to an adjacent (left) PE (e.g., PE₁ in Figure 21.8c) such that we can consider the next bit of the input stream. When the shifted global history reaches the leftmost PE (PE₃ in Figure 21.8c), a match is detected if the initial logic “1” has been preserved.

That said, some architectural-level timing constraints must also be satisfied. For instance, bits of the input stream must be “spaced” two PEs apart to ensure that global history bits and streaming input data meet at the proper time. (Note the position of x₁ in Figure 21.8c). This will degrade circuit throughput. However, two different input streams could be interleaved within the systolic array – assuming that one would want to search for the same pattern in each. Interleaved dataflow (e.g., p₁, x₁, p₀, x₀ as noted in Figure 21.8c) would allow for full hardware usage and the highest possible throughput.

21.4.1 Threshold Logic

We believe that devices with PMA (i.e., pNML) could be especially well-suited for realizing threshold logic circuits. As an example, we consider how an adder comprised of multiple layers of pNML-based devices might fare given the context of the most recent NRI benchmarking effort.

The design (Figure 21.9) is based on the two majority gate threshold adder from [61]. The carry output (C_out) can be determined simply by performing the majority voting function M(A, B, C_in) that is native to NML [13]. The sum output can then be realized by a five-input majority voter: . With the in-plane device architecture, the single domain limit necessitates that device footprint be relatively small which limits fan-in. pNML devices can not only be larger (increasing fan-in), but can also couple in multiple dimensions. Note that in Figure 21.9, the AF-coupling between the A, B, and C inputs and the C_out target would result in the generation of . Additionally, by placing the Sum target above A, B, C_in, and , the correct signal values will be fed to Sum.³ (The Sum target is sized such that the fringing field magnitude from C_out is two times that of A, B, or C_in.) As such, a full adder can be realized with just five devices. If we assume that F = 15 nm (as is done in the most recent NRI benchmarking), with this approach, a 32-bit adder could be ∼45× smaller than an iNML-based design and ∼145× smaller than a CMOS design. Moreover, as the carry out signal and sum signals could be calculated simultaneously (see Figure 21.10b—generated via the code associated with [56]), a single, 32-bit add could be completed in the time required for 33 magnet switching events (a 900% reduction compare to iNML). as per Figure 21.10a, this could make the power-constrained throughput of pNML-based hardware highly competitive with respect to other NRI technologies (without even considering any additional benefits from inherent pipelining associated with NML).

21.4.2 NonBoolean Computing

We also believe that NML devices could be used to create nonBoolean information processing systems. As an example, we summarize work presented in [60] that considers an arrangement of pNML devices that could be used for image edge detection.⁴

To begin, consider the arrangements of pNML devices shown in Figure 21.11a. Red boxes represent devices that are magnetized up (+M_z). Later, blue boxes will represent devices that are magnetized down (−M_z). Thus, to make an analogy to a black and white image, one could equate a −M_z magnetization state of an input device to a white pixel, and a +M_z magnetization state to a black pixel.) Input devices could presumably be set via STT [62], and are indicated by green boxes. While pNML devices are assumed, we assume that no dots are FIB irradiated. Therefore, in Figure 21.11a, we might assume that all pNML devices (in both the “interconnect” as well as the inputs) were initially magnetized such that their z-component of magnetization was positive (i.e., by an external field, voltage-based clock, and/or STT.). Additionally, this suggests that a 3 × 3 black square is encoded by this magnet arrangement.

Now, assume that we subject this system to an out-of-plane field that is directionally opposite to the magnetization state of “interconnect” magnets (per Figure 21.11a, a negative H_z field would be applied), and that gradually increases in magnitude. One would expect pNML devices that have more neighbors with a +z component of magnetization to switch first as fringing fields from neighboring devices – also directed in the −z direction – influence switching as well. (As an example, looking at Figure 21.11b, the middle device should switch first as it influenced by both the applied external field as well as neighboring fringing fields.)

In initial studies, we assumed that a given magnet is influenced by devices that are two “squares” away – that is, devices that are closer to a given device will have more influence over it than those that are farther away. (Practically speaking, the pNML design space is large, and the influence of particular device could be “tuned” by changing dot size, material, spacing between dots, irradiating dots, or combinations thereof.) We also assume that the state of the input dots does not change during the switching process – which could be achieved by varying device size, limited FIB irradiation, or combinations thereof. Thus, given different assumptions regarding neighbor to neighbor influence, we calculated how susceptible a given device is to switching when subjected to an out-of-plane field.

If we assume: (i) that the influence of a given magnet falls of as 1/r², (ii) the arrangement of magnets (with the initial state) shown in Figure 21.11a, and (iii) that this magnet ensemble is subjected to a field that is directed in the opposite direction to the initial magnetization state of the devices, the final state of the system is predicted to be similar to that shown in Figure 21.11c.⁵

Note that the number of cells that surround the center input devi`ce that were initially magnetized down (opposite to the direction of the applied field) is lower than the number of cells that surround devices that are now magnetized up. However, the number of devices that surround the input devices on the “edge” of the 3 × 3 black square is lower (i.e., for the center pixel, 6 of the 8 surrounding devices have changed state, while for the edge pixels, only 4 or 5 of the surrounding devices have changed state). If one could measure the resistance of the input and its surrounding cells, one could detect the edges in a black and white image with: (i) a short field pulse per the discussion above and (ii) resistance measurements.⁶ Therefore, even though NML devices have longer switching latencies than a CMOS transistor, an edge detection operation could be accomplished with just a single field pulse and simultaneous reads. The devices in the system “evolve” in parallel.

Notably, micromagnetic simulations suggest that the magnet ensemble described above will evolve almost as predicted (see Figure 21.11d). (Minor differences between Figure 21.11c and Figure 21.11d most likely result from the direction of the nominal x- and y-directed biasing fields that initiate a torque on a given pNML device.) That said, micromagnetic simulations were performed at 0 K, and multiple devices can switch simultaneously as appropriate (e.g., due to the influence of equally weighted neighbors in this environment.) However, we will ultimately need to consider how thermal noise [12] impacts ordered switching. For example, if one cell switches first, it may impact another cell that should switch at the same time, which could impact final system state.

21.4.3 Cellular Automata

Cellular Automata (CA) is a classic and early example of computationally universal nonBoolean computing and ancestor of many modern cellular architectures (such as CNNs). It displays two highly desirable architectural properties of a realizable nano-scale computing system: high-level of parallelism, and nearest neighbor interconnections [63].

In the first step of a CA computation, each computing units (cells) of a CA have to initialized to a certain (possibly digital) value – the initialization pattern can be looked as an input image. Once initialized, the cell's state evolves in discrete time according to a logical rule and the result of the computation is read out after a number of computing steps elapsed. This computing scheme clearly lends itself to a natural realization in pNML architectures.

As a case study for a two-dimensional pNML-based cellular automata, we implemented an image filtering algorithm as described in [64]. Noise of a black and white image can be reduced by: (i) assigning a cell for each pixel of the image, (ii) in every CA iteration, each cell assumes the pixel value of the majority of its neighbors and itself, and (iii) the iteration is repeated for several (5–15) steps until the noise disappears but the image still retains most of its useful information. In these scheme each cell requires an external input/output (for initialization and read-out) and interconnections to the neighboring cells (to determine their majority). The results of the filtering similar to the ones obtainable by a standard Gaussian filter.

A pNML implementation we designed is shown in Figure 21.12. The design does not require any wire crossings and it is entirely tileable, that is, an arbitrary number of cells can be placed and the output (input) of each cell can directly contact the input (output) of its neighbors. Details of the design and simulation results are given in [65].

In order to arrive to this simple design, we slightly changed the used CA rule of [64] and a slightly different rule is applied to even and odd-numbered rows. For even-numbered rows the updated value of the state variable of cell i, j is:

and for rows with odd indices:

where i, j are the column and row indices of the cell.

These cell rules ignore one neighbor (out of the four) and take into account another one with a double weight. We found that although it is a different CA rule from the one described in [64], it performs the filtering operation equally well: as it is shown in the images of Figure 21.12b. The noisy original image clears up after four, eight, and 12 iterations. The overhead of inputting and reading out the image amortized over these number of iteration steps.

Signal race conditions may cause undesired operation of this CA (or any other CA operation): depending on the data being processed some cells may pass data to neighboring cells “too early” and the computing units of the CA fall out of synchrony. To prevent this, the designs needs “transfer dots,” that enable the flow of magnetic information only after each eighth clocking cycles, where all cell outputs are ready. These transfer dots are labeled as “in” in Figure 21.12a.

21.5.1 Retrospective: Experimental Progress to Date

When compared to other emerging information processing technologies, we believe that there has been significant progress with both iNML and pNML on the experimental front. For iNML, fanout structures [21], a one-bit full adder [27], and so on have been experimentally demonstrated and successfully re-evaluated with new inputs. Both field-coupled [28,66] and spin transfer torque (STT) [26,29,30] electrical inputs have been realized. For electrical output, multiple iNML-magnetic tunnel junction hybrids [33] have been proposed and simulated.

Field-based, CMOS compatible line clock structures have been used to simultaneously switch the states of multiple magnetic islands [38], as well as to re-evaluate iNML lines and gates with new inputs [22]. Additionally, recent experiments have considered materials-based solutions to further reduce field/energy requirements for line clock structures. Notably, results from [37,39] suggest that the component energy metrics could be further reduced by as much as 16×. Alternative clocking mechanisms – for example, via multiferroics [41], magnetostriction [24], or the Spin Hall Effect [67] – might also be paths to further reductions in clock energy.

Experimental results suggest that appropriately irradiated pNML structures (to define dataflow directionality) can be controlled by a uniform, homogeneous, oscillating, global clock field [46]. Majority gates [47], AF-lines [46], multi-plane signal crossings [68], and full adders [48,69] have all been experimentally demonstrated with this clocking approach. Field coupled inputs have also been demonstrated [70].

Looking to chip-level implementations, large arrays of pNML devices could be controlled with on-chip inductor structures [49] that could be coupled with a capacitance in an LC oscillator – which opens the door to adiabatic energy recycling. Devices with PMA are also amenable to voltage-controlled clocking [50].

That said, for both device architectures, challenges still remain – particularly with respect to efficient interconnect, reliable device switching, and fault tolerant architectures.

21.5.2 Challenge 1: Efficient Interconnect

One challenge associated with processing information using devices that communicate via fringing fields is interconnect. Signal routing and signal propagation times can be adversely affected. Devices with PMA can help to alleviate the aforementioned issues. With respect to signal routing, the large single-domain size in pNML enables the use of long (several micrometer) domain walls for information transfer. Moreover, per [63] CoPt domain walls can cross above/below one other, and conducing stripes can cross a 30 nm vertical “step” without unwanted pinning. Moreover, simulations suggest that by creating a nucleation center where two stripes cross, the interaction can be switched on, and one of the walls can stop or pass the other wall depending on their relative orientation. (Conditional passing of domain walls may even be used to realize PLAs.) The benefits of NML/domain-wall logic hybrids are threefold: (i) the footprint of domain wall-based devices is reduced and electrical components are necessary only at the inputs and outputs, (ii) interconnect complexity and delay of dot-based interconnections in NML is also reduced, and (iii) more reliable signal transmission may ensue.

Regarding signal propagation times (as well as signal routing), consider an array multiplier – where bits of data word A must be distributed to processing elements in each column of the multiplier, and the bits of data word B must be distributed to processing elements (PE) in each row of the multiplier. If one were to move this information to individual PEs via AF-lines, both signal routing and communication delay would be adversely affected. However, domain wall motion in magnetic stripes above and below NML processing elements could be used to preprogram PEs with the A and B input bits required – vastly simplifying design layout. (The work presented in [71] could be considered to be a preliminary, experimental proof of concept.)

21.5.3 Challenge 2: Error Tolerance

Any circuit and/or architecture comprised of NML devices must ultimately be tolerant to fabrication variations. Consider an iNML device with a symmetric, rounded-rectangle shape. A given device will be in the highest energy state if magnetized along its hard axis with no applied field (see Figure 21.12). However, lower energy states are equivalent and occur at ±90 °. [With no external stimulus to keep such a device in a hard axis-biased state, thermal noise, minor fabrication variations, etc. should determine whether or not it relaxes such that its y-component of magnetization is positive (↑) or negative (↓).] By changing a magnet's geometry, its energy landscape can change as well. More specifically, if the edge of a magnet becomes “slanted,” the highest-energy state does not occur when a device is magnetized along its (geometrically) hard axis. Rather, if biased along its geometrically hard axis, a device is already on one side of the potential barrier and should always relax such that the sign of the y-component of magnetization (i.e., its binary state) is always the same – see Figure 21.13. If devices are sufficiently large, we can exploit the aforementioned energy barrier shift to realize nonmajority gate, two-input AND/OR logic [55]. However, as device sizes scale, the effects of minor fabrication variations on device switching behavior can become more pronounced. If energy barrier shifts like those described above occur, a stuck at fault can ensue.

In pNML, switching field distributions (SFD; from defects formed during layer growth) can impact operation. The width of SFD strongly depends on layer deposition conditions, postgrowth annealing and the applied FIB dose. Thermally induced SFD also have a strong effect. Initial studies show that coupling fields are sufficiently strong to ensure device operation in the presence of SFD [72].

21.5.4 Paths Forward

While NML circuits show benefits over CMOS-based logic, a “killer application” has yet to emerge. We envision that NML circuits may become especially useful in applications, which require close integration of data storage and processing functions. The combination of dense, nonvolatile, possibly three-dimensional storage capabilities of coupled nanomagnet arrays with processing capabilities (such as the systolic pattern matching or image processing) may serve as hardware for future intelligent storage devices.

A challenge with scaled NML is unwanted bit flips that can occur during the switching process due to thermal noise, lithographic variation, and so on. At the device level, improved device to device couplings [73,74] and devices with biaxial anisotropy [23] have been suggested as possible mechanisms to improve the reliability of an NML-based computation. However, even magnet ensembles that employ devices with biaxial anisotropy can be error prone [54]. Thus, fault tolerant architectures should be studied and developed. Of initial interest are stochastic computer architectures where the value of a signal is interpreted as a probability regardless of normal or faulty conditions. Stochastic computation is naturally fault tolerant since a small number of bit flips only result in small deviations from the desired value. While computation time could increase as the precision of stochastic values increases, given the inherently pipelined, streaming dataflow associated with NML, more efficient implementation of stochastic computation architectures should be possible with NML devices (e.g., as one of the main drawbacks of stochastic computation is the rapid growth of computation time with respect to precision).