INDEX
& operator, 13
| operator, 13
~ operator, 13
8-bit operations, 105–109
16-bit operations, 88–91, 105–109
32-bit data (subroutines), 193–194
32-bit operations
addition, 137–141
assignment operations, 134–136
bitwise logical operations, 136–137
comparison conditional tests, 144–146
equality conditional tests, 144–145
inequality conditional tests, 144–145
non-zero conditional tests, 141–144
overview, 134
shift operations, 141
subtraction, 137–141
zero conditional tests, 141–144
32-bit timers (pulse width measurement), 492–496
64-bit multiplication, 218–220
64-bit operations, 146–147
A
ADCs (analog-to-digital converters)
overview, 453–457
parallel port I/O, 290
PIC24
configuration, 463–469
operation, 469–474
overview, 460–463
sample and hold amplifiers, 459–460
successive approximation, 457–459
adders (combinational building blocks), 20–21
addition
binary numbers, 8–9
hexadecimal numbers, 8–9
operations
32-bit, 137–141
fixed-point arithemetic, 228–229
three-operand, 74–76
two-operand, 76
addressing
default working register (WREG), 67–69
file register addressing, 65–67
immediate addressing, 69–70
indirect addressing, 70–72
data dependencies, 171–172
instructions, 170–172
modes, 168–172
register indirect with signed constant offset mode, 170
troubleshooting, 170–172
instruction set regularity, 72–73
register direct addressing, 62–65
algebra, 12–19
ALU (arithmetic logic unit), 230
amplifiers (ADCs), 459–460
analog-to-digital converters (ADCs)
overview, 453–457
parallel port I/O, 290
PIC24
configuration, 463–469
operation, 469–474
overview, 460–463
sample and hold amplifiers, 459–460
successive approximation, 457–459
AND operations, 12–19
arbitration (Inter IC Bus), 553–557
architecture (PIC24), 645–652
arithmetic
addition
32-bit, 137–141
binary numbers, 8–9
fixed-point arithemetic, 228–229
hexadecimal numbers, 8–9
three-operand, 74–76
two-operand, 76
BCD, 235–237
decrement instructions, 77
division, 220–225
fixed-point
addition operations, 228–229
arithmetic logic unit (ALU), 230
converting binary numbers to decimal, 226–227
converting decimal numbers to binary, 226
overview, 225
saturating operations, 228–230
signed fixed-point, 227
subtraction operations, 228–229
unsupported instructions, 230
floating-point
IEEE 754 encoding, 230–233
operations, 233–235
overview, 230
increment instructions, 77
multiplication
64-bit, 218–220
overview, 214–217
operators, 96–99
shift operations
32-bit operations, 141
binary numbers, 11–12
hexadecimal numbers, 11–12
signed data, 155–157
subtraction
32-bit, 137–141
binary numbers, 10–11
fixed-point arithemetic, 228–229
hexadecimal numbers, 10–11
three-operand, 74–76
two-operand, 76
arithmetic logic unit (ALU), 230
arrays
32-bit data subroutines, 193–194
implementing, 190–193
overview, 186–189
repeat instruction, 196–198
strings, 195–196
ASCII
converting
ASCII decimal numbers to binary, 242
ASCII hexadecimal numbers to binary, 240–241
binary numbers to decimal, 239–240
binary numbers to hexadecimal, 237–239
overview, 30–31
assembly language
C comparison, 248–250
programs
16-bit operations, 88–91
data types, 80
nop instruction, 87
overview, 79–87
Word, 88–91
stored program machines, 40–44
assignment operations, 134–136
asynchronous serial I/O, 374–380. See also UART
B
baud rate (UART), 384–386
BCD (binary coded decimal), 235–237
binary data, 4–7
binary numbers
addition, 8–9
BCD arithmetic, 235–237
converting to
ASCII decimal, 239–240
ASCII hexadecimal, 237–239
decimal, 226–227
hexadecimal, 7–8
overview, 5–7
shift operations, 11–12
subtraction, 10–11
bit tests (unsigned conditional tests), 115–116
bits
configuration bits, 272–273
control bits (parallel port I/O), 291
references (compilers), 251–255
bitwise logical operations (32-bit operations), 136–137
bitwise operators, 96–99
Boolean algebra operations, 12–19
branch instructions
encoding, 161–163
unsigned conditional tests, 118–123
buffers
Inter IC bus, 441–445
parallel port I/O
Schmitt Trigger buffers, 288
tristate buffers, 287
building blocks
combinational
adders, 20–21
incrementers, 21
memory, 22–23
multiplexers, 19–20
overview, 19
shifters, 22
sequential
counters, 28
overview, 27
registers, 27–28
shift registers, 28–29
busses (Inter IC bus)
arbitration, 553–557
buffers, 441–445
ESOS
messaging, 638–641
operations, 629–632
overview, 628–629
semaphores, 636–638
transactions, 632–635
interrupts, 441–445
library functions, 424–431
master-slave relationships, 549–553
overview, 419–420
registers, 427–431
reverse string, 555–557
serial EEPROM, 436–445
signals, 421–423
streaming data, 441–445
thermometer, 432–435
C
C
assembly language comparison, 248–250
compiler
bit references, 251–255
compilation process overview, 250–251
conditional compilation, 256–257
function registers, 251–255
inline functions, 256
macros, 256
overview, 250–251
run-time code, 255
variables, 255
calendar (real-time clock calendar module), 532–537
call/return
data memory stack, 177–179
stack, 174–179
CAN (controller area network), 558–572
capacitors, 658–659
cascade mode (pulse width measurement), 504–506
change notification interrupts
idle, 330
latency, 330–332
LED, 345–353
sleep, 330
switches, 345–353
timers, 345–353
characters (encoding character data), 30–31
child tasks (ESOS), 621–624
circuits
capacitors, 658–659
current, 653–657
diodes, 657
Ohm’s Law, 654–655
polarization, 657
resistance, 653–657
voltage, 653–657
configuration, 273
real-time clock calendar module, 532–537
signal
instruction execution, 91–92
sequential logic, 24–25
CMOS operations, 16–19
code (ASCII)
converting
ASCII decimal numbers to binary, 242
ASCII hexadecimal numbers to binary, 240–241
binary numbers to decimal, 239–240
binary numbers to hexadecimal, 237–239
overview, 30–31
combinational building blocks
adders, 20–21
incrementers, 21
memory, 22–23
multiplexers, 19–20
overview, 19
shifters, 22
communication
ESOS, 604–608
serial link
startup schematic, 262
testing, 267–270
comparison conditional tests, 116–123, 144–146
comparison operations (signed data), 157–159
compilation
conditional compilation, 256–257
process overview, 250–251
compiler
bit references, 251–255
compilation process overview, 250–251
conditional compilation, 256–257
function registers, 251–255
inline functions, 256
macros, 256
overview, 250–251
run-time code, 255
variables, 255
complements (signed data)
one’s complement, 148–149
two’s complement, 149–153
complex conditional expressions, 123–126
components (startup schematic), 263
compound operations, 105–109
computers (stored program machines)
assembly language, 40–44
finite state machines comparison, 34–35
hardware, 44–47
instructions, 40–44
modern computer comparison, 48
overview, 40
conditional compilation, 256–257
conditional execution
complex conditional expressions, 123–126
overview, 109–111
unsigned conditional tests
bit tests, 115–116
branch instructions, 118–123
comparison conditional tests, 116–123, 144–146
equality conditional tests, 116, 144–145
inequality conditional tests, 116–118, 144–145
non-zero conditional tests, 112–114, 141–144
overview, 111–112
zero conditional tests, 112–114, 141–144
conditional tests (unsigned)
bit tests, 115–116
branch instructions, 118–123
comparison conditional tests, 116–123, 144–146
equality conditional tests, 116, 144–145
inequality conditional tests, 116–118, 144–145
non-zero conditional tests, 112–114, 141–144
overview, 111–112
zero conditional tests, 112–114, 141–144
configuration
ADCs, 463–469
baud rate (UART), 384–386
clock, 273
configuration bits, 272–273
UART, 386–389
configuration bits, 272–273
configuration macros (parallel port I/O), 291–293
control bits (parallel port I/O), 291
control registers (UART), 380–384
controller area network (CAN), 558–572
converting
ADCs. See ADCs
ASCII decimal numbers to binary, 242
ASCII hexadecimal numbers to binary, 240–241
binary numbers to ASCII decimal, 239–240
binary numbers to ASCII hexadecimal, 237–239
binary numbers to decimal, 226–227
binary numbers to hexadecimal, 7–8
DACs (digital-to-analog converters)
external examples, 482–486
flash, 475–482
Maxim548A, 483–486
overview, 474–475
PWM, 530–532
R-2R resistor ladder, 475–482
data
overview, 450
sensors, 450–453
transducers, 450–453
data types, 106
decimal numbers to binary, 226
hexadecimal numbers to binary, 7–8
counters (sequential building blocks), 28
CPUs (SPI), 414–419
current, 653–657
D
DACs (digital-to-analog converters)
external examples, 482–486
flash, 475–482
Maxim548A, 483–486
overview, 474–475
PWM, 530–532
R-2R resistor ladder, 475–482
data
ADCs. See ADCs
binary, 4–7
converting
overview, 450
sensors, 450–453
transducers, 450–453
DACs (digital-to-analog converters)
external examples, 482–486
flash, 475–482
Maxim548A, 483–486
overview, 474–475
PWM, 530–532
R-2R resistor ladder, 475–482
data dependencies (indirect addressing), 171–172
data transfer. See data transfer
encoding character data, 30–31
signed data. See signed data
streaming data (Inter IC bus), 441–445
data dependencies (indirect addressing), 171–172
data memory
organization, 58–60
values, 60–62
data memory stack, 175–179
data registers (UART), 380–384
data transfer
default working register (WREG), 67–69
file register addressing, 65–67
immediate addressing, 69–70
indirect addressing, 70–72
data dependencies, 171–172
instructions, 170–172
modes, 168–172
register indirect with signed constant offset mode, 170
troubleshooting, 170–172
instruction set regularity, 72–73
overview, 62
register direct addressing, 62–65
data types
assembly language programs, 80
type conversion, 106
datasheets, reading, 270–271
DC motor speed (PWM), 523–524
debugging ISRs, 365–366
decimal numbers
converting ASCII decimal to binary, 242
converting to binary, 226
overview, 5–7
decrement instructions, 77
default interrupt handlers, 325–327
default working register (WREG), 67–69, 108
DFF (D-Flip-Flop), 25–27
digital logic, 4–7
digital-to-analog converters (DACs)
external examples, 482–486
flash, 475–482
Maxim548A, 483–486
overview, 474–475
PWM, 530–532
R-2R resistor ladder, 475–482
diodes, 657
direct memory access (DMA), 542–549
disabling interrupts, 322
division, 220–225
DMA (direct memory access), 542–549
doze mode, 276–284
dynamic memory allocation, 180–182
E
ECAN™ module, 562–572
echo program, 267
EEPROM (Inter IC bus), 436–445
embedded system operating system (ESOS)
child tasks, 621–624
communication, 604–608
flags, 619–620
Inter IC Bus
messaging, 638–641
operations, 629–632
overview, 628–629
semaphores, 636–638
transactions, 632–635
interrupts, 624–628
messaging, 615–619
overview, 596–598
program, 602–604
tasks, 598–602
timer, 608–610
encoding/encoders
branch instructions, 161–163
character data, 30–31
IEEE 754 floating-point, 230–233
NRZ encoding, 375–380
one-hot encoding, 4
rotary encoders, 355–359
serial I/O, 375–380
equality conditional tests, 116, 144–145
ESOS (embedded systems operating system)
child tasks, 621–624
communication, 604–608
flags, 619–620
Inter IC Bus
messaging, 638–641
operations, 629–632
overview, 628–629
semaphores, 636–638
transactions, 632–635
interrupts, 624–628
messaging, 615–619
overview, 596–598
program, 602–604
tasks, 598–602
timer, 608–610
execution
conditional execution. See conditional execution
instructions, 91–92
expressions (complex conditional expressions), 123–126
extensions (sign extension), 151, 159–161
external DACs, 482–486
external interrupts, 332–336
F
families (PIC24), 310–311
file register addressing, 65–67
filtering noisy inputs, 353–355
finite state machines
overview, 35–40
stored program machines comparison, 34–35
fixed-point arithmetic
addition operations, 228–229
arithmetic logic unit (ALU), 230
converting binary numbers to decimal, 226–227
converting decimal numbers to binary, 226
overview, 225
saturating operations, 228–230
signed fixed-point, 227
subtraction operations, 228–229
unsupported instructions, 230
flags (ESOS), 619–620
flash (DACs), 475–482
flashing LED program, 263–267
floating-point arithmetic
IEEE 754 encoding, 230–233
operations, 233–235
overview, 230
function registers, 251–255
functions
function registers, 251–255
inline functions, 256
ISRs
default interrupt handlers, 325–327
overview, 325
traps, 327–329
library functions
Inter IC bus, 424–431
stdio.h library functions, 389
UART, 386–389
G–H
global variables, 203–206
goto instructions, 77–79
handlers (default interrupt handlers), 325–327
hardware (stored program machines), 44–47
hexadecimal numbers
addition, 8–9
converting ASCII hexadecimal to binary, 240–241
converting to binary, 7–8
overview, 5–7
shift operations, 11–12
subtraction, 10–11
I
IEEE 754, 230–233
immediate addressing, 69–70
implementing
arrays, 190–193
pointers, 190–193
subroutines, 179–186
in-circuit serial programming, 262–263
increment instructions, 77
incrementers (combinational building blocks), 21
indirect addressing, 70–72
data dependencies, 171–172
instructions, 170–172
modes, 168–172
register indirect with signed constant offset mode, 170
troubleshooting, 170–172
inequality conditional tests, 116–118, 144–145
infrared decoder, 507–515
initializing global variables, 203–206
inline functions, 256
input . See I/O
input capture mode (pulse width measurement), 507–515
input capture module (pulse width measurement), 496–506
input change notification (parallel port I/O), 289–290
input sampling (LED/switches), 343–346
instructions
branch instructions
encoding, 161–163
unsigned conditional tests, 118–123
clock signal, 91–92
data transfer. See data transfer
decrement, 77
execution, 91–92
fixed-point arithemetic, 230
goto, 77–79
increment, 77
indirect addressing, 170–172
move instructions
default working register (WREG), 67–69
file register addressing, 65–67
immediate addressing, 69–70
indirect addressing, 70–72
instruction set regularity, 72–73
register direct addressing, 62–65
nop, 87
PIC24 overview, 645–652
program control, 77–79
repeat
arrays, 196–198
pointers, 196–198
status register, 100–101
stored program machines, 40–44
unsupported instructions, 230
Inter IC bus
arbitration, 553–557
buffers, 441–445
ESOS
messaging, 638–641
operations, 629–632
overview, 628–629
semaphores, 636–638
transactions, 632–635
interrupts, 441–445
library functions, 424–431
master-slave relationships, 549–553
overview, 419–420
registers, 427–431
reverse string, 555–557
serial EEPROM, 436–445
signals, 421–423
streaming data, 441–445
thermometer, 432–435
interfaces/interfacing
keypads, 359–364
LCD modules, 301–310
master-slave relationships, 414–419
multiple CPUs, 414–419
overview, 401–408
potentiometer, 408–411
thermometer, 411–414
interrupt service routines (ISRs)
debugging, 365–366
functions
default interrupt handlers, 325–327
overview, 325
traps, 327–329
overhead, 324
overview, 318
rotary encoders, 355–359
writing, 365–366
interrupts
change notification
idle, 330
I/O, 329
latency, 330–332
sleep, 330
timers, 345–353
default interrupt handlers, 325–327
disabling, 322
ESOS, 624–628
filtering noisy inputs, 353–355
Inter IC bus, 441–445
INTx external interrupts, 332–336
I/O
change notification interrupts, 345–353
input sampling, 343–346
LED, 343–353
switches, 343–353
ISRs . See ISRs
latency, 323–324
nesting, 322
overview, 318–320
priorities, 322
remappable I/O pins, 332–336
service routines. See ISRs
rotary encoders, 355–359
timers
macros, 339–341
overview, 336–339
square waves, 341–343
testing, 341–343
UART
receive, 390–394
transmit, 394–399
vector tables, 320–321
INTx external interrupts, 332–336
I/O
filtering noisy inputs, 353–355
input capture mode (pulse width measurement), 507–515
input capture module (pulse width measurement), 496–506
input change notification (parallel port I/O), 289–290
input sampling (LED/switches), 343–346
interrupts
change notification interrupts, 329
UART receive, 390–394
UART transmit, 394–399
LED
change notification interrupts, 345–353
input sampling, 343–346
interrupts, 343–353
state machines, 293–301
output compare module (pulse width measurement), 516–520
parallel port I/O
analog-to-digital converters, 290
configuration macros, 291–293
control bits, 291
input change notification, 289–290
open-drain output, 288–289
overview, 284–286
Schmitt Trigger buffers, 288
serial I/O comparison, 372–374
tristate buffers, 287
weak pull-ups, 289–290
remappable I/O pins, 332–336
RS-232 standard, 399–400
serial I/O
asynchronous, 374–380
NRZ encoding, 375–380
parallel port I/O comparison, 372–374
synchronous, 374–375
UART . See UART
master-slave relationships, 414–419
multiple CPUs, 414–419
overview, 401–408
potentiometer, 408–411
thermometer, 411–414
switches
change notification interrupts, 345–353
input sampling, 343–346
interrupts, 343–353
state machines, 293–301
ISRs (interrupt service routines)
debugging, 365–366
functions
default interrupt handlers, 325–327
overview, 325
traps, 327–329
overhead, 324
overview, 318
rotary encoders, 355–359
writing, 365–366
K–L
keypads, 359–364
ladders (DACs), 475–482
latency
change notification interrupts, 330–332
interrupts, 323–324
LCD modules, 301–310
LEDs
change notification interrupts, 345–353
flash program, 263–267
input sampling, 343–346
interrupts, 343–353
state machines, 293–301
left shift operations. See shift operations
library functions
Inter IC bus, 424–431
stdio.h library functions, 389
links (serial link)
startup schematic, 262
testing, 267–270
local variables
dynamic memory allocation, 180–182
registers, 182–186
stack frames, 199–203
logic
digital, 4–7
logic operations, 12–19
sequential
clock signal, 24–25
DFF (D-Flip-Flop), 25–27
overview, 23
logical operations (bitwise logical operations), 136–137
logical operators, 96–99
loops, 126–128
LSB operations, 108–109
M
macros
compiler, 256
configuration macros (parallel port I/O), 291–293
timers (interrupts), 339–341
magnitude (signed magnitude), 147–148
master-slave relationships
Inter IC Bus, 549–553
SPI, 414–419
Maxim548A, 483–486
memory
combinational building blocks, 22–23
data memory
organization, 58–60
values, 60–62
data memory stack, 175–179
direct memory access (DMA), 542–549
dynamic memory allocation
subroutine local variables, 180–182
subroutine parameters, 180–182
program memory, 57–58
regitsers, 104–105
RTSP (run-time self-programming), 572–580
messaging
Inter IC Bus, 638–641
OSes, 593–594
microcontrollers
overview, 54–55
PIC24 . See PIC24
microprocessors, 54–55
mixed operations, 105–109
modern computers, stored program machines comparison, 48
indirect addressing, 168–172
pulse width measurement
capture mode, 507–515
cascade mode, 504–506
modules
ECAN™, 562–572
LCD, 301–310
pulse width measurement
input capture module, 496–506
output compare module, 516–520
real-time clock calendar module, 532–537
motor speed (PWM), 523–524
move instructions
default working register (WREG), 67–69
file register addressing, 65–67
immediate addressing, 69–70
indirect addressing, 70–72
instruction set regularity, 72–73
register direct addressing, 62–65
MSB operations, 108–109
multiple CPUs (SPI), 414–419
multiplexers, 19–20
multiplication
64-bit, 218–220
overview, 214–217
multitasking (Oses), 588–591
N
NAND operations, 13–19
nesting interrupts, 322
networks (CAN), 558–572
noisy inputs, filtering, 353–355
non-return-to-zero (NRZ) encoding, 375–380
non-zero conditional tests, 112–114, 141–144
nop instruction, 87
NOT operations, 12–19
NRZ (non-return-to-zero) encoding, 375–380
number sequencing computers (stored program machines)
assembly language, 40–44
finite state machines comparison, 34–35
hardware, 44–47
instructions, 40–44
modern computer comparison, 48
overview, 40
numbers
ASCII decimal, converting to binary, 242
ASCII hexadecimal, converting to binary, 240–241
BCD arithetic, 235–237
binary
addition, 8–9
converting to ASCII decimal, 239–240
converting to ASCII hexadecimal, 237–239
converting to decimal, 226–227
converting to hexadecimal, 7–8
overview, 5–7
shift operations, 11–12
subtraction, 10–11
decimal
converting to binary, 226
overview, 5–7
hexadecimal
addition, 8–9
converting to binary, 7–8
overview, 5–7
shift operations, 11–12
subtraction, 10–11
O
Ohm’s Law, 654–655
one-hot encoding, 4
one’s complement, 148–149
open-drain output (parallel port I/O), 288–289
ESOS
child tasks, 621–624
communication, 604–608
flags, 619–620
interrupts, 624–628
messaging, 615–619
overview, 596–598
program, 602–604
semaphore, 611–615
tasks, 598–602
timer, 608–610
overview, 584–587
services, 594–595
tasks
messaging, 593–594
multitasking, 588–591
overview, 587–588
schedulers, 588–591
semaphores, 592–593
operations
8-bit, 105–109
16-bit operations, 88–91, 105–109
32-bit
addition, 137–141
assignment operations, 134–136
bitwise logical operations, 136–137
comparison conditional tests, 144–146
equality conditional tests, 144–145
inequality conditional tests, 144–145
non-zero conditional tests, 141–144
overview, 134
shift operations, 141
subtraction, 137–141
zero conditional tests, 141–144
64-bit, 146–147
ADCs, 469–474
addition operations
fixed-point arithemetic, 228–229
three-operand, 74–76
two-operand, 76
AND, 12–19
arrays
32-bit data subroutines, 193–194
implementing, 190–193
overview, 186–189
repeat instruction, 196–198
strings, 195–196
Boolean algebra operations, 12–19
CMOS, 16–19
compound, 105–109
default working register (WREG), 108
division, 220–225
ESOS, 629–632
fixed-point arithemetic, 228–230
floating point arithmetic, 233–235
Inter IC Bus, 629–632
logic operations, 12–19
LSB, 108–109
mixed, 105–109
MSB, 108–109
multiplication
64-bit, 218–220
overview, 214–217
NAND, 13–19
NOT, 12–19
OR, 12–19
pointers
32-bit data subroutines, 193–194
implementing, 190–193
overview, 186–189
repeat instruction, 196–198
strings, 195–196
rotate, 102–105
saturating operations, 228–230
shift, 102–105
32-bit operations, 141
binary numbers, 11–12
hexadecimal numbers, 11–12
signed data, 155–157
signed data
comparison operations, 157–159
overview, 153–154
shift operations, 155–157
sign extension, 159–161
subtraction operations
fixed-point arithemetic, 228–229
three-operand, 74–76
two-operand, 76
UART
receive, 384
transmit, 383
XOR, 13
operators
&, 13
|, 13
~, 13
arithmetic, 96–99
bitwise, 96–99
logical, 96–99
OR operations, 12–19
organization
data memory, 58–60
program memory, 57–58
OSes (operating systems)
ESOS
child tasks, 621–624
communication, 604–608
flags, 619–620
interrupts, 624–628
messaging, 615–619
overview, 596–598
program, 602–604
semaphore, 611–615
tasks, 598–602
timer, 608–610
overview, 584–587
services, 594–595
tasks
messaging, 593–594
multitasking, 588–591
overview, 587–588
schedulers, 588–591
semaphores, 592–593
output . See I/O
output compare module (pulse width measurement), 516–520
overflow
two’s complement, 152–153
stack, 179
overhead (ISRs), 324
P
parallel port I/O
analog-to-digital converters, 290
configuration macros, 291–293
control bits, 291
input change notification, 289–290
open-drain output, 288–289
overview, 284–286
Schmitt Trigger buffers, 288
serial I/O comparison, 372–374
tristate buffers, 287
weak pull-ups, 289–290
parameters (subroutines)
dynamic memory allocation, 180–182
registers, 182–186
stack frames, 199–203
period measurement, 504–506
persistent variables, 280–284
PIC24
ADCs
configuration, 463–469
operation, 469–474
overview, 460–463
architecture, 645–652
arithmetic logic unit (ALU), 230
compiler
bit references, 251–255
compilation process overview, 250–251
conditional compilation, 256–257
function registers, 251–255
inline functions, 256
macros, 256
overview, 250–251
run-time code, 255
variables, 255
data memory, 58–60–62
families, 310–311
instructions, 645–652
overview, 55–57
program memory, 57–58
startup schematic
components, 263
in-circuit serial programming, 262–263
overview, 258–260
power, 260–261
reset, 261–262
serial link, 262
UART
baud rate configuration, 384–386
configuration, 386–389
functions, 386–389
overview, 380–384–386
registers, 380–384
stdio.h library functions, 389
unsupported instructions, 230
pins (remappable I/O pins), 332–336
pointers
32-bit data subroutines, 193–194
implementing, 190–193
overview, 186–189
repeat instruction, 196–198
stack pointers, 175
strings, 195–196
polarization (circuits), 657
ports (parallel port I/O)
analog-to-digital converters, 290
configuration macros, 291–293
control bits, 291
input change notification, 289–290
open-drain output, 288–289
overview, 284–286
Schmitt Trigger buffers, 288
serial I/O comparison, 372–374
tristate buffers, 287
weak pull-ups, 289–290
potentiometer (SPI), 408–411
power
startup schematic, 260–261
timers, 276–284
power-on reset, 274–276
priorities (interrupts), 322
programming (in-circuit serial programming), 262–263
programs
assembly language
16-bit operations, 88–91
data types, 80
nop instruction, 87
overview, 79–87
Word, 88–91
conditional execution. See conditional execution
control, 77–79
echo, 267
ESOS, 602–604
LED flash, 263–267
memory, 57–58
pull-ups (weak pull-ups), 289–290
pulse width measurement
32-bit timers, 492–496
cascade mode, 504–506
infrared decoder, 507–515
input capture mode, 507–515
input capture module, 496–506
output compare module, 516–520
overview, 490–492
period measurement, 504–506
square waves, 519–520
push/pop (stack), 174–179
PWM (pulse width modulation)
DACs, 530–532
DC motor speed, 523–524
overview, 520–522
servos, 524–529
R
R-2R resistor ladder (DACs), 475–482
reading datasheets, 270–271
real-time clock calendar module, 532–537
references (bits), 251–255
register direct addressing, 62–65
register indirect with signed constant offset mode, 170
registers (sequential building blocks), 27–28
compiler function registers, 251–255
Inter IC bus, 427–431
memory, 104–105
register direct addressing, 62–65
register indirect with signed constant offset mode, 170
status register, 100–101
subroutine local variables, 182–186
subroutine parameters, 182–186
UART, 380–384
regularity (instruction set), 72–73
remappable I/O pins, 332–336
repeat instruction, 196–198
resistance, 653–657
resistors (DACs), 475–482
reverse string (Inter IC Bus), 555–557
right shift operations. See shift operations
rotary encoders, 355–359
rotate operations, 102–105
RS-232 standard, 399–400
RTSP (run-time self-programming), 572–580
run-time code (compiler), 255
run-time self-programming (RTSP), 572–580
S
sample and hold amplifiers, 459–460
saturating operations, 228–230
schedulers (Oses), 588–591
schematic (startup)
components, 263
in-circuit serial programming, 262–263
overview, 258–260
power, 260–261
reset, 261–262
serial link, 262
Schmitt Trigger buffers, 288
semaphores
Inter IC Bus, 636–638
OSes, 592–593
sensors (data conversion), 450–453
counters, 28
overview, 27
registers, 27–28
shift registers, 28–29
sequential logic
clock signal, 24–25
DFF (D-Flip-Flop), 25–27
overview, 23
serial busses (Inter IC bus)
arbitration, 553–557
buffers, 441–445
ESOS, messaging, 638–641
ESOS, operations, 629–632
ESOS, overview, 628–629
ESOS, semaphores, 636–638
ESOS, transactions, 632–635
interrupts, 441–445
library functions, 424–431
master-slave relationships, 549–553
overview, 419–420
registers, 427–431
reverse string, 555–557
serial EEPROM, 436–445
signals, 421–423
streaming data, 441–445
thermometer, 432–435
serial EEPROM, 436–445
serial I/O
asynchronous, 374–380
NRZ encoding, 375–380
parallel port I/O comparison, 372–374
synchronous, 374–375
UART
baud rate configuration, 384–386
configuration, 386–389
functions, 386–389
overview, 380–384–386
registers, 380–384
stdio.h library functions, 389
serial link
startup schematic, 262
testing, 267–270
Serial Peripheral Interface (SPI)
master-slave relationships, 414–419
multiple CPUs, 414–419
overview, 401–408
potentiometer, 408–411
thermometer, 411–414
serial programming, 262–263
services
interrupt service routines. See ISRs
OSes, 594–595
servos (pulse width modulation), 524–529
shift operations, 102–105
32-bit operations, 141
binary numbers, 11–12
hexadecimal numbers, 11–12
signed data, 155–157
shift registers (sequential building blocks), 28–29
shifters (combinational building blocks), 22
signals (Inter IC bus), 421–423
signed data
one’s complement, 148–149
operations
comparison operations, 157–159
overview, 153–154
shift operations, 155–157
sign extension, 159–161
overflow, 152–153
overview, 147
signed magnitude, 147–148
two’s complement, 149–153
signed fixed-point, 227
signed magnitude, 147–148
sleep
interrupts (change notification interrupts), 330
sleep mode, 276–284
sleep mode, 276–284
speed (DC motors), 523–524
SPI (Serial Peripheral Interface)
master-slave relationships, 414–419
multiple CPUs, 414–419
overview, 401–408
potentiometer, 408–411
thermometer, 411–414
square waves
pulse width measurement, 519–520
timers (interrupts), 341–343
call/return, 174–179
data memory stack, 175–179
overflow/underflow, 179
overview, 174–175
push/pop, 174–179
stack frames, 199–203
stack pointers, 175
subroutine local variables, 199–203
subroutine parameters, 199–203
stack frames, 199–203
stack pointers, 175
startup schematic
components, 263
in-circuit serial programming, 262–263
overview, 258–260
power, 260–261
reset, 261–262
serial link, 262
state machines, 293–301
status register, 100–101
stdio.h library functions, 389
stored program machines
assembly language, 40–44
finite state machines comparison, 34–35
hardware, 44–47
instructions, 40–44
modern computer comparison, 48
overview, 40
streaming data (Inter IC bus), 441–445
strings
arrays, 195–196
pointers, 195–196
reverse string (Inter IC Bus), 555–557
subroutines, 172–174
32-bit data
arrays, 193–194
pointers, 193–194
implementing, 179–186
local variables
dynamic memory allocation, 180–182
registers, 182–186
stack frames, 199–203
parameters
dynamic memory allocation, 180–182
registers, 182–186
stack frames, 199–203
stack
call/return, 174–179
data memory stack, 175–179
overflow/underflow, 179
overview, 174–175
pointers, 175
push/pop, 174–179
stack frames, 199–203
subtraction
binary numbers, 10–11
hexadecimal numbers, 10–11
operations
32-bit, 137–141
fixed-point arithemetic, 228–229
three-operand, 74–76
two-operand, 76
successive approximation (ADCs), 457–459
switches
change notification interrupts, 345–353
input sampling, 343–346
interrupts, 343–353
state machines, 293–301
synchronous serial I/O, 374–375
T
tables (vector tables), 320–321
tasks
child tasks, 621–624
OSes
messaging, 593–594
multitasking, 588–591
overview, 587–588
schedulers, 588–591
semaphores, 592–593
testing/tests
serial link, 267–270
timers (interrupts), 341–343
unsigned conditional tests
bit tests, 115–116
branch instructions, 118–123
comparison conditional tests, 116–123, 144–146
equality conditional tests, 116, 144–145
inequality conditional tests, 116–118, 144–145
non-zero conditional tests, 112–114, 141–144
overview, 111–112
zero conditional tests, 112–114, 141–144
Inter IC bus, 432–435
SPI, 411–414
three-operand addition operations, 74–76
three-operand subtraction operations, 74–76
timers
ESOS, 608–610
interrupts
change notification interrupts, 345–353
macros, 339–341
overview, 336–339
square waves, 341–343
testing, 341–343
overview, 276–284
pulse width measurement
32-bit timers, 492–496
cascade mode, 504–506
infrared decoder, 507–515
input capture mode, 507–515
input capture module, 496–506
output compare module, 516–520
overview, 490–492
period measurement, 504–506
square waves, 519–520
PWM (pulse width modulation)
DACs, 530–532
DC motor speed, 523–524
overview, 520–522
servos, 524–529
real-time clock calendar module, 532–537
transactions (Inter IC bus), 423–427, 431, 632–635
transducers, 450–453
transfering data
default working register (WREG), 67–69
file register addressing, 65–67
immediate addressing, 69–70
indirect addressing, 70–72
data dependencies, 171–172
instructions, 170–172
modes, 168–172
register indirect with signed constant offset mode, 170
troubleshooting, 170–172
instruction set regularity, 72–73
overview, 62
register direct addressing, 62–65
transmit operations (UART), 383, 394–399
traps
interrupts, 322–323
ISRs, 327–329
tristate buffers (parallel port I/O), 287
troubleshooting indirect addressing, 170–172
two’s complement (signed data), 149–153
two-operand addition operations, 76
two-operand subtraction operations, 76
type conversion, 106
U
UART (Universal Asynchronous Receiver Transmitter). See also asynchronous serial I/O
baud rate configuration, 384–386
configuration, 386–389
functions, 386–389
interrupts
receive, 390–394
transmit, 394–399
overview, 380–384–386
receive operations, 384
registers, 380–384
stdio.h library functions, 389
transmit operations, 383
unsigned conditional tests
bit tests, 115–116
branch instructions, 118–123
comparison conditional tests, 116–123, 144–146
equality conditional tests, 116, 144–145
inequality conditional tests, 116–118, 144–145
non-zero conditional tests, 112–114, 141–144
overview, 111–112
zero conditional tests, 112–114, 141–144
unsupported instructions (fixed-point arithemetic), 230
V
values (data memory), 60–62
variables
compiler, 255
global variables, initializing, 203–206
local variables
subroutine dynamic memory allocation, 180–182
subroutine registers, 182–186
subroutine stack frames, 199–203
persistent, 280–284
32-bit data subroutines, 193–194
implementing, 190–193
overview, 186–189
repeat instruction, 196–198
stack pointers, 175
strings, 195–196
vector tables (interrupts), 320–321
voltage, 653–657
W–Z
watchdog timer, 276–284
weak pull-ups, 289–290
Word, 88–91
WREG (default working register), 67–69, 108
writing (ISRs), 365–366
XOR operations, 13