9.1 General Statements

In this chapter we consider and discuss the main stages of system design of the digital target return signal processing subsystem employed by a complex surveillance radar system using a phased array. However, this is not considered a practical case. Preliminarily, we will discuss some general considerations associated with the designing and construction of a digital target return signal processing subsystem, particularly in the context of an automated complex “radar-digital signal processing and control subsystem” (complex radar system or CRS).

The basic idea of any CRS digital signal processing and control subsystem is defined, first of all, by the type and purpose of the CRS. Before starting the designing process, at the initial stage of analysis of the problems to be solved by a higher-order system, the specifications of the corresponding CRS support must be first defined. The first step will be to consider and select which type of CRS to construct, including type of radar to be used; thus it is critical to define the problems typically associated with digital signal processing and control subsystems and embark on a design process that is prepared to solve the many problems that might arise during the design and construction of the subsystem. At the same time, there is a need to adhere to the following principal positions. The CRS, as a source of information, is very complicated and expensive. It is designed and constructed in a way to ensure compliance of the highly technical specifications that form part of the design procedure. Evidently, the CRS digital signal processing and control subsystem must be able to stabilize the radar performance under hard conditions that involve high-precision operations and applications.

From the viewpoint of automated CRS digital signal processing and control processes, we can distinguish between the automatic and automated radar systems. The automatic radar systems are required, for example, to monitor the air condition in regions that are difficult to access. However, the complete automatization of digital signal processing and control subsystems is worthwhile in the case of CRSs operating in global systems on control, earth-based guidance and tracking, landing, and so on. In doing so, all available methods and tools to cancel the interference and noise must be used. The digital signal processing and control subsystem must be able to keep stable the probability of false alarm to prevent overloading on the central microprocessor system. If it is found that complete automation of a CRS is not worthwhile or impossible on account of specific technical or tactical considerations, then keeping such requirements in mind, different types of systems are designed customizing the system to meet specific requirements, especially where some of the processes are manually carried out by an operator, for example, even signal processing and other specific controls. For example, the operator is responsible for blanking the intensive interference and noise zones, primary target lock-in with the purpose of target tracking, switching on the security equipment and tools of interference and noise protection, semiautomatic target tracking, and so on.

The level of development and production status of the digital computing system element base are critical for effective designing and construction of the digital signal processing and control systems. By this, we only mean computer-driven applications deployed to solve specific problems encountered in the signal processing and control, not computer techniques in general. Thus, there is increased interest in a new element base, namely, graphene.

While designing a specific digital signal processing and control system, theoretical and technical investigations on signal processing methods and algorithms, the technical team, including engineers and subject experts, communications skills, and so on play a very important role.

9.2 Design of Digital Signal Processing and Control Subsystem Structure

9.3 Structure of Coherent Signal Preprocessing Microprocessor Subsystem

The digital coherent signal preprocessing subsystem ensures an interface between the analog receiver linear tract and the central computer system of radar complex. The following important operations are carried out by the digital coherent signal preprocessing subsystem:

• Analog-to-digital conversion

• Signal detection based on the generalized approach to signal processing in noise of linear-frequency-modulated target return signals

• Suppression of passive interferences

• Coherent accumulation of target return signals

• Data provision to assist with solving the problems of stabilization of the probability of false alarm

The digital coherent signal preprocessing subsystem is realized by an individual microprocessor sub-subsystem or a distributed set of specific microprocessor sub-subsystems.

A key part of the design process involves the design and construction of the digital coherent signal preprocessing subsystem and justification of structure of the corresponding microprocessor sub-subsystem or set of microprocessor sub-subsystems. Further, we assume that the following alternatives are key to designing and constructing the digital coherent signal preprocessing microprocessor subsystem:

• Design and construction of specific microprocessor sub-subsystem based on very-large-scale integration (VLSI) circuits

• Microcomputer based on a set of microprocessor sub-subsystems

• Specific processor based on analog charge-coupled device components

The use of microcomputer based on a set of microprocessor sub-subsystems is not worthwhile because these cannot satisfy the functional requirements when the speed of operation takes priority, for example, during conditions requiring matched filtering and compression of linear-frequency-modulated target return signals. Microprocessor sub-subsystems with analog-to-digital conversion based on charge-coupled devices, in principle, may satisfy the main requirements on speed of operation and low power consumption, but, at the current level of research, the main elements of the digital coherent signal preprocessing subsystem, for example, the GD linear tract filters, have not been studied thoroughly. Thus, an effective alternative is the digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem.

It is worthwhile to employ hardware in the specific digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem to solve the following problems:

• Signal detection based on the generalized approach to signal processing in noise

• Suppression of passive interferences

• Computation of target return signal amplitudes

• Estimation of interference and noise power

To solve the problems of Doppler filtering it is worthwhile to implement the FFT processor or filter using the effective and simple realization methods and procedures of complex multiplication. All elements of the specific digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem must possess high reliability and low power consumption. High reliability can be ensured by equipment reservation or information redundancy. Low power consumption can be achieved by very careful circuit designing and implementation of VLSI with small power dissipation.

Now, consider an interaction between the elements of the specific digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem (see Figure 9.2) and discuss the principles of realization of the main objectives of digital coherent target return signal preprocessing subsystems and the main technical specifications of hardware.

The first element of the global structure of digital coherent target return signal preprocessing subsystem is the analog-to-digital converter (ADC) of target return signals at the phase detector output. Because the duration of the compressed linear-frequency scanning signal is τscancomp=2μs, the limiting frequency of sampling in time must be f_s = 500 kHz both for in-phase and quadrature channels. However, to improve the digital GD (DGD) characteristics it is worthwhile to increase this frequency, at least twice, that is, f_s = 1 MHz (see Chapter 2). The number of amplitude quantization bits is selected based on linear transformation of the target return signals exceeding the receiver noise on 50-60 dB. For this purpose, we need to use 10-bit ADC and/or ADC with capacity of more than 10 bits. Thus, ADC must issue the signal codes at the outputs of in-phase and quadrature channels with resolution τ_s = 1μs and capacity N_capacity = 10 bits.

Next element of the total structure of digital coherent target return signal preprocessing subsystem is the DGD for linear-frequency-modulated target return signals that can be realized in time domain employing the nonrecursive filter or in frequency domain using the FFT processor or filter. In doing so, while using the sequential scheme of DGD in time domain to compute a single magnitude of the output signal, we need to use 4f_sτ_scan = 4 × 1 × 64 = 256 multiplications and 252 additions. Consequently, the required speed of operation of DGD is equal to 256 × 10⁶ multiplications per second, which is very difficult to realize. Under realization of DGD in frequency domain we obtain some benefits in speed of operations (see Chapter 2), but these benefits are not so essential that we could use them without any doubts.

To improve the DGD speed of operation we can use properties of parallelism of matched filtering algorithms. For this reason, to realize DGD with high speed of operation we can use the parallel mixers based on ROM, parallel adders with simultaneous addition of several numbers, and parallel registers. For example, for parallel nonrecursive digital filter, coincidence-type adders, and parallel registers the minimal time of convolution both in the in-phase channel and in the quadrature channel is 75 ns. For a four-channel DGD (see Figure 2.7) the minimal time to obtain a single magnitude of the output signal is 100ns.

The nonrecursive smoothing filter with short impulse response is placed after DGD. The main tasks of this filter are, first, to suppress the signal side lobes at the DGD output and, second, to decrease the sampling rate to the frequency corresponding to the sampling theorem requirements. Decrease in the sampling rate in m times (m is the integer) is carried out by the element providing a sample of each mth element from the sequence of input sampled target return signals {x(kT_s)}. As a result, we obtain the output signal {x(kmT_s)} with the sampling period Ts′=mTs. Naturally, the sampling period Ts′ must satisfy the following condition:

both at the in-phase channel and at the quadrature channel.

The cancellation of correlated interference is realized after the signal detection based on the generalized approach to signal processing in noise. For this purpose, the samples of in-phase and quadrature channels in each resolution element by radar range (the number of resolution elements by radar range is M_R = 500) are stored during 10 periods by the buffer memory with capacity of Q_BM = 2 × 500 × 10 = 10⁴ of 10-bit words. After that, 10-pulse bursts corresponding to each resolution element by radar range are processed by the rejector filters with the interperiod subtraction of the order ν = 2 individually both in the in-phase channel and in the quadrature channel. Owing to the simplicity of the rejector filters with the interperiod subtraction of the order ν = 2 algorithm, its realization in real time is not difficult. Thus far, we have considered and discussed operations during the first stage of digital coherent signal processing. To ensure the required reliability, all hardware elements of the first stage must be doubled. The output signals of the main and reserved hardware set are compared by a specific module. Comparison results are used both by the searching system and by the default system.

Signals at the outputs of the rejector filters with the interperiod subtraction of the order ν = 2 in the form of 8-pulse bursts come in individually by the in-phase and quadrature channels at the input of filter carrying out a coherent accumulation of the target return signals within the limits of 8-pulse bursts. In the considered case, the target return signal coherent accumulation is realized in the frequency domain using the FFT processors or filters. Using the FFT processor or filter is the most appropriate choice considering the simplicity of usage and tuning convenience while processing pulse bursts with variable width. Information at the FFT processor or filter output is accumulated during eight scanning periods, that is, 8 × 10⁻³ s, T_scan = 10⁻³ s. The number of resolution elements by radar range is M_R = 500. Consequently, 8-point FFT must be finished within the limits of 16|Lts. With current level of technology, it is possible to use different schemes of FFT realization that guarantee faster operations without any problems. Moreover, to increase the efficiency of coherent signal processing and the reliability of its corresponding hardware module, three FFT processors or filter in series with the time are required, as shown in Figure 9.3. This functional capability of FFT processors or filters reduces requirements for faster operation of FFT processors or filters and for the high reliability of the corresponding hardware module.

Each FFT processor or filter possesses a buffer memory to store the input data. The buffer memory capacity must store the 8-pulse burst signals at each of the 500 resolution elements by radar range and take into consideration the in-phase and quadrature channels, that is, Q_BM = 2 × 8 × 500 = 8 × 10³ 10-bit words. At the FFT processor or filter output, the signal weighting at the Doppler channels 2–6 is carried out to reduce the effect of signal side lobes and expand zero part width of amplitude-frequency characteristics of Doppler filters. Weighting is carried out based on the algorithm given by (9.5). By this operation, the coherent signal processing is concluded, and the envelope amplitude of target return signals needs to be selected, for example, to unify signals at the outputs of in-phase and quadrature channels.

Estimation of envelope amplitudes at each resolution element by radar range for all Doppler channels is to be carried out in accordance with signal processing algorithms discussed in Chapter 3. Estimations of squared envelope amplitudes obtained in the zero Doppler channel are used to make corrections in the interference and noise power map. Estimations of squared envelope amplitudes obtained in other Doppler channels come in at the input module of definition and estimation of interference and noise power. For this purpose, the signal processing algorithm used to estimate the sampled interference and noise variance within the limits of the window, including eight resolution elements by radar range (approximately 2.5km) from both sides of the central (signal) element given by (9.6), is realized. Estimations of sampled interference and noise variance are defined at the outputs of each Doppler channel, except for zero Doppler channel. The corresponding magnitudes of squared amplitudes σ^12,…,σ^72 and variances x^12,…,x^72 are transmitted to the noncoherent signal preprocessing subsystem.

9.4 Structure of Noncoherent Signal Preprocessing Microprocessor Subsystem

9.5 Signal Reprocessing Microprocessor Subsystem Specifications

The information about the detected target pip coordinates comes in at the input of digital signal reprocessing subsystem (see Figure 9.4). The main tasks of digital signal reprocessing subsystem are to achieve the target trajectory detection, target tracking and target trajectory tracking, filtering of target trajectory parameters, and other digital signal processing algorithms derived during the target processing stages and to provide definite information to the user. In the said example, we assume that all tasks of the digital signal reprocessing subsystem are carried out by a single microprocessor subsystem. We also assume that the typical digital signal processing algorithms, which we discussed previously, modified for the case of two-coordinate surveillance radar are realized in the course of digital signal reprocessing. For this reason, we do not present in this section a detailed description of operations and global digital signal reprocessing algorithm. Some specific features of these digital signal processing algorithms are defined by specific application of the considered two-coordinate surveillance radar and are reduced to the following ones.

1. To reduce the required number of operations for solving the problem of new target pip binding to target tracked trajectories, there is a need to perform a target trajectory picking within the limits of ±15° from a direction corresponding to the azimuth of new target pip. This rough narrow-beam pulse sampling by azimuth allows us to select only such target trajectories for comparison that can be continued using a new target pip taking into consideration their displacements in radial direction with maximum velocity and the acceptable number (three) of missing target pips on the target trajectory. Coordinate extrapolation at the instant of getting a new target pip, gating, and a verification of new target pip present within the limits of gate are carried out sequentially for the target trajectories thus selected. Gate dimension depends on the number of confirmation omissions that the target trajectory was tested in the previous scanning periods.

2. The target trajectory binding is carried out using the criterion “2 from 3”. The target trajectory binding can be also considered as a decision about the target trajectory detection. Thus, in the considered case, the operations of confirmation about the target trajectory bindings using one or several target pips are excluded.

3. Each detected target is estimated by the principle “important-not important,” and a decision “to apply-not apply” a signal processing to the detected target is made.

4. The information generated must be precise for it allows us to implement an individual smoothing of the Cartesian coordinates X and Y without taking into consideration the correlation between them. In this case, laborious operations on the vector and matrices are excluded while computing, which essentially reduces the number of operations under realization of the digital signal reprocessing algorithms.

5. Determination of the target velocity scalar of vector V^ntg and the target course Qntg at nth step of filtering the Cartesian coordinates X and Y is made by the following formulas:

   V^ntg(V^Xntg)2+(V^Yntg)2;⁢(9.17)
   Q^n′=arctg|Y˙^n||X˙^n|;⁢(9.18)
   Q^ntg={Q^n′ifY˙^n>0,X˙^n>0;π−Q^n′ifY˙^n>0,X˙^n>0;π+Q^n′ifY˙^n>0,X˙^n>0;2π−Q^n′ifY˙^n>0,X˙^n>0;⁢(9.19)

   where V^Xntg and V^Yntg are the estimations of target velocity by the Cartesian coordinates X and Y. Logical flowchart of the digital signal reprocessing algorithm is shown in Figure 9.5. Based on this flowchart, the sequence and interaction of operations under realization of the digital signal reprocessing algorithm can be defined.

Now, consider the main requirements for the speed of operation and the memory capacity of digital signal reprocessing microprocessor subsystem. In the case of a single realization of the digital signal reprocessing algorithm partly responsible for processing a single new target pip, a reduced number of approximately 2 × 10³ operations are required. Considering that for each scanning period about 20 new true and 5 false target pips come in at the digital signal reprocessing microprocessor subsystem input, we obtain NΣop=5×104 operations per scanning period. The scanning period is T_scan = 4.5 s. The required effective speed of operation is ηΣeff≈104 operations per second. Thus, we can conclude that the speed expected of the digital signal reprocessing microprocessor subsystem is not high.

To determine the required memory capacity of digital signal reprocessing microprocessor subsystem, we assume that 10 false target pips are stored by the memory device in addition to the 20 true target pips. Our estimation shows that data about a single target trajectory requires approximately fifteen 32-bit words. Consequently, to store data about 30 tracked trajectories approximately four hundred and ffty 32-bit cells are required. Moreover, to store data on the detected target trajectories and the new target trajectories taking into consideration a reserved memory capacity, it is reasonable to have approximately 100 more 32-bit cells. The memory capacity requires about 400-500 cells. Thus, to solve the digital signal reprocessing problems we need about 10³ memory cells.

The foregoing analysis shows the digital signal reprocessing problems do not require high computational resources compared to the previous stages of target return signal processing. This allows to assign for the digital signal reprocessing microprocessor subsystem the problems to control over all elements and parameters of the CRS and the problems of the current hardware and computational process control, additionally. Considering that the control optimization problems are not solved in dynamic mode in the automatic “radar complex-global digital signal processing complex” system and the control system is constructed as the system with a predetermined fixed sequence of control commands, we do not consider such system in the present chapter. It is assumed that the scheduled problems are considered and analyzed at the next stage of designing and construction of the CRS.

9.6 Structure of Digital Signal Processing Subsystem

Functional requirements, cost, reliability, conveniences in fault lookup, maintainability—all these factors are taken into consideration in the course of designing the global digital signal processing structure of the CRS. The functional requirements to individual elements of this structure, which have been discussed in the previous sections, are evidences of differences in the intensity of information flows processed by the central computer system of the radar complex. The digital coherent target return preprocessing subsystem working in real time has the greatest service load. For this reason, given the latest technological breakthroughs in signal detection and signal processing theory and in computer applications, there is a need to design and construct a specific nonprogrammable microprocessor subsystem for the digital coherent target return preprocessing subsystem working in real time, which consists of specific adders, mixers, convolution networks, memory devices based on VLSI, and charge injection devices. Without any doubts, we can state that the possibility of designing and constructing such specific microprocessor subsystems is the foundation stone to developing solutions for the problems encountered in automatic digital target return signal processing under real conditions of CRS functioning.

At the output of digital coherent target return preprocessing microprocessor subsystem the information density is essentially reduced, and at the stage of noncoherent digital signal preprocessing, we can use the programmable microprocessor subsystems. Analysis of requirements to specific subsystems of global computer system of radar complex and existing general avenues applicable to the microprocessor subsystems in digital target return signal processing systems favor using a module structure of target return signal processing systems, the main body of which consists of several identical microprocessor networks. Such microprocessor networks enhance ease of use, reliability, and effectiveness of the digital signal processing system as a whole. However, such microprocessor networks require that the problems of some stages of target return signal processing be parallel. In particular, we have considered such requirement while discussing the noncoherent target return signal preprocessing subsystem. Moreover, there is a need to focus on organizing the control process in such multimicroprocessor network system.

In our case, the control process must be hard; that is, it must be carried out in accordance with a program assigned before and must be subject to the given time sequence. This can be organized by way of instructions to carry out the signal processing and control problems using the specific stack memory with subsequent task choice in accordance with the time diagram of global digital signal processing system. After fulfillment of the immediate task, each micro-processor subsystem can select from the programmable control device memory the next task, indicating the following:

• The operation that must be done

• Initial data that must be used

• Memory cells that should store the obtained results

• Way for further computational process

Thus, carrying out the foregoing steps will enable the microprocessor networks to operate independently of each other. Increasing the number of microprocessor networks will enhance the reliability and speed of data processing without any changes in administration principles.

In accordance with general principles discussed thus far and needing consideration during the design and construction of the central computer system for global signal processing and control employed by radar complex, one variant of a structural flowchart is shown in Figure 9.6. These are the following subsystem boxes:

1. Coherent signal preprocessing microprocessor subsystem with the buffer memory to store the information data issued for the noncoherent signal preprocessing subsystem

2. Programmable control subsystem to control the CRS issuing the time sequence of control command and operations, such as

   1. Radar antenna scanning control

   2. Changing the transmitter carrier frequency

   3. Computation of detection thresholds

   4. Definition of operation mode—scanning mode or request “native–foreigner” mode

3. Radar synchronizer forming the signals controlling the global digital signal processing system and radar complex

4. Memory device to store the power map of interference formed by the underlying surface and local objects; this memory device is represented by individual box owing to large capacity and specific problems solved

   

   FIGURE 9.6 Structure of the central computer system for global signal processing and control.

5. Module of communication with the user, with interface functions “input-output,” preparation of information for display, and sending information by the communication channel

6. Four central microprocessor networks (three microprocessor networks are working and one microprocessor network is reserve) assigned to solve all problems and tasks of global signal processing and control system, except for the problems and tasks assigned for the coherent target return signal preprocessing subsystem

7. Memory device for cooperative use assigned for the execution of central computer system functions during data processing and control distributed in space and time

8. The structure of the central computer system for global signal processing and control employed by the radar complex gives us an original approximation under solution of the assigned problem. Furthermore, we need to consider all partial signal processing and control algorithms in detail, incorporate these algorithms into the complex signal processing and control algorithm, and design the functional time diagram of the system. This stage of designing must be started after selecting specific types of microprocessor networks and the decision whether it is practicable to continue with a specific process of CRS design and construction

9.7 Summary and Discussion

The first stage of system design of any radar system is the selection of structure and energy parameters of radar being a constituent of the CRS. The radar antenna type, shape, and width of radar antenna directional diagram, method and period of scanning coverage, transmitter power, duration and scanning signal modulation technique, period of scanning pulsing, resources and methods of protection from active interferences, and other radar parameters must be defined and justifed at this stage. At the second stage of CRS design the structure is designed, the parameters of digital signal processing subsystem are justifed, and the ways of specific realizations are defined. At the initial stages, the main problems and tasks of digital signal processing and control subsystem should be discussed and the procedures to solve these problems should be defined.

It is worthwhile to employ the rejector filters with the interperiod subtraction of the order ν and the filters of coherent accumulation in the form of FFT processors or filters in series to ensure the required quality of passive interference cancellation and to improve the detection performance of moving targets. Stabilization of the probability of false alarm is also a very important problem. The methods of adaptive threshold control under signal detection are widely used to solve this problem. The implementation of adaptation to the interference and noise power can stabilize the probability of false alarm under detection of target return signals, but, in this case, the average number of false detections is not controlled and can be estimated only during simulation and digital signal processing and control subsystem sample debugging.

Functions such as automatic target lock-in, target trajectory tracking, and target trajectory reset play a vital role and require thorough understanding. A demand to operate in automatic mode under conditions of the high-level interference requires sufficiently effective measures that prevent overloading of the digital signal reprocessing subsystem while processing both the targets that are not captured by the CRS and the false targets. These effective measures are as follows: effective algorithm to detect the target trajectories providing the methods and procedures to decrease the probability of false target track beginning; selection of target pips in target tracking gates taking into consideration the high density of false target pips; filtering the target trajectory parameters providing tracking of both the nonmaneuvering targets and maneuvering targets; implementation of specific algorithms of target classification providing a selection of the most important targets for target tracking; ensuring appropriate speed of operation and memory capacity of central computer system. Under the automatic mode of operation, the most important problem associated with the central microprocessor system is effective control of the CRS as a whole and functional synchronization of operations of all elements. Algorithmic designing and realization of digital signal processing and control subsystem are other problems to be considered while designing the central computer system.

The principle of division of signal processing procedure into various stages, that is, coherent digital signal preprocessing, noncoherent digital signal preprocessing, and digital signal reprocessing, forms the basis of designing the structure of global digital signal processing and control system of radar complex, which consists of the digital coherent target return signal preprocessing subsystem, digital noncoherent target return signal preprocessing subsystem, digital signal reprocessing subsystem, and digital control subsystem.

The digital coherent signal preprocessing subsystem ensures an interface between the analog receiver linear tract and the central computer system of radar complex. The following important operations are carried out by the digital coherent signal preprocessing subsystem: analog-to-digital conversion; generalized signal processing algorithm of linear-frequency-modulated target return signals; suppression of passive interferences; coherent accumulation of target return signals; and generation of data to solve the problems related to stabilization of the probability of false alarm. The digital coherent signal preprocessing subsystem is realized by individual microprocessor sub-subsystem or distributed set of specific microprocessor subsystems. Choosing the right approach to design and construct the digital coherent signal preprocessing subsystem and justification of structure of the corresponding microprocessor sub-subsystem or set of microprocessor sub-subsystems is the first and foremost requirement of the system design process.

It is worthwhile to employ hardware in the specific digital coherent signal preprocessing sub-system designed based on VLSI microprocessor sub-subsystem to solve the following problems: generalized signal processing algorithm, suppression of passive interferences, computation of target return signal amplitudes, and estimation of interference and noise power. To solve the problems of Doppler filtering, it is worthwhile to implement the FFT processor or filter using effective and simple methods and procedures such as complex multiplication. All elements of the specific digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem must possess high reliability and require low power consumption. High reliability can be achieved by equipment reservation or information redundancy. Low power consumption can be achieved by very careful circuit designing and implementation of VLSI with small power dissipation.

The first element of the global structure of digital coherent target return signal preprocessing sub-system is the ADC of the target return signals at the phase detector output. Next element of the total structure of the digital coherent target return signal preprocessing subsystem is the DGD for linear-frequency-modulated target return signals that can be realized in the time domain employing the nonre-cursive filter or in the frequency domain using the FFT processor or filter. To improve the DGD speed of operation, we can use properties of parallelism applied to the matched filtering algorithms. For this reason, to realize the DGD with high speed of operation we can use the parallel mixers based on ROM, parallel adders with simultaneous addition of several numbers, and parallel registers. The nonrecursive smoothing filter with short impulse response is placed after DGD. The main tasks of this filter include the following:first, suppressing the signal side lobes at the DGD output and, second, decreasing the sampling rate to frequency corresponding to requirements of the sampling theorem. A decrease in the sampling rate in m times (m is the integer) is carried out by the element providing a sample of each mth element from sequence of input sampled target return signals.{x (kT_s)}. The cancellation of correlated interference is realized after the matched filtering. The operations discussed are part of the first stage of the digital coherent signal processing. To ensure the required reliability all hardware elements of the first stage must be doubled. The output signals of the main and reserved hardware set are compared by specific modules. Comparison results are used by both the searching system and the default system.

In accordance with the global structure of digital signal processing and control system used by the radar complex (see Figure 9.1), the noncoherent signal preprocessing subsystem solves the following problems: (a) noncoherent accumulation of signals after the coherent signal processing of each from three 8-pulse bursts by the FFT processor or filter; (b) noncoherent accumulation of interference and noise power estimations for all Doppler channels, except for the zero Doppler channel, and for all resolution elements by radar range; (c) corrections of the interference and noise power map, forming the adaptive detection thresholds; (d) signal detection to be provided by comparison between the signals and the corresponding thresholds computed for each cell’s “radar range–Doppler frequency”; (e) estimation of the target azimuth by a set of signals exceeding the detection threshold at three neighboring positions of the radar antenna directional diagram by azimuth.

The requirements to speed of operation of the noncoherent target return signal preprocessing microprocessor subsystem are sufficiently high. However, the noncoherent target return signal preprocessing operations can be conducted in parallel using two microprocessor subsystems simultaneously. For example, the first microprocessor subsystem must perform the noncoherent accumulation of target return signals, corrections in the interference and noise power map, and the target azimuth estimation. The second microprocessor subsystem must carry out the noncoherent accumulation of interference and noise power, threshold forming, and signal detection. In this case, the required speed of operation of each microprocessor subsystem is not more than 2 × 10³ operations per second.

The main tasks of the digital signal reprocessing subsystem include the following: to realize the target trajectory detection, the target tracking and target trajectory tracking, the filtering of target trajectory parameters, and other digital signal processing algorithms accomplished during the target processing stages, and to provide precise information to the user. The analysis performed thus shows that the digital signal reprocessing problems do not require the high computational resources in comparison with the previous stages of target return signal processing. This fact allows us to assign for the digital signal reprocessing microprocessor subsystem the problems of control over all elements and parameters of the CRS and the current hardware and computational process control problems. Taking into consideration that the control optimization problems are not solved in dynamic mode in the automatic. “radar complex–global digital signal processing complex” system and the control system is constructed as the system with a fixed, predetermined sequence of control commands.

Functional requirements, cost, reliability, conveniences in fault lookup, maintainability are the important factors that are taken into consideration in the course of designing the global digital signal processing structure of the CRS. The functional requirements to individual elements of this structure discussed and considered previously are evidences of differences in the density of information flow processed by the central computer system of radar complex. The digital coherent target return preprocessing subsystem working in real time has the greatest service load. For this reason, and given the technological breakthroughs in the signal detection and signal processing theory and computer applications, there is a need to design and construct a specific nonprogrammable micro-processor subsystem for the digital coherent target return preprocessing subsystem working in real time, which consists of the specific adders, mixers, convolution networks, memory devices based on. VLSI and charge-injection devices. Without any doubts, we can state that the possibility of designing and constructing such specific microprocessor subsystems is the foundation stone for developing processes that solve the problems encountered in automatic digital target return signal processing in the functioning of the CRS under real-time conditions.

References

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