CHAPTER 1: INTEGRATION OF GRAPHICS PROCESSING CORES WITH MICROPROCESSORS (Deepak C. Sekar and Chinnakrishnan Ballapuram)

Integration is at the forefront of practically any design activity. Putting more features in the same piece of silicon has been driving all segments of the industry, starting from manufacturing and ending with CAD tools. This chapter talks about the recent trend of combining multiple cores in a single chip and boost performance of the overall system this way, instead of just increasing the system clock speed. With more advanced processes, integration of many components such as peripheral control hubs, dynamic random access memory (DRAM) controllers, modems, and, more importantly, graphics processors have become possible. Single-chip integration of graphics processing units (GPUs) with central processing units (CPUs) has emerged and also brought many challenges that arise from integrating disparate devices or architectures, starting from overall system architecture, software tools, programming and memory models, interconnect design, power and performance, transistor requirements, and process-related constraints.

CHAPTER 2: ARITHMETIC IMPLEMENTED WITH SEMICONDUCTOR QUANTUM-DOT CELLULAR AUTOMATA (EARL E. SWARTZLANDER JR., Heumpil Cho, Inwook Kong, and Seong-Wan Kim)

The second chapter introduces us to quantum-dot cellular automata (QCA). Nanotechnology and QCA open new ways of performing what has been done for decades using the standard CMOS technology. What has been done for years at the transistor level, QCA attempt to do at the single electron level. Instead of voltage levels, QCA use electron position to save the information. And from there build more complicated functional elements like adders, multipliers and dividers, ripple carry and carry lookahead adders, and many more. As there is still some time before QCA elements can be physically implemented, this chapter investigates possible concept and architectures that can be implemented in various types of QCA technologies currently being developed.

CHAPTER 3: NOVEL CAPACITOR-LESS A2RAM MEMORY CELLS FOR BEYOND 22-NM NODES (Noel Rodríguez and Francisco Gamiz)

Each technology or material will reach its limits sooner or later. It can be power consumption, speed, minimum voltage operation, scaling, and so on. But even before that happens, researchers are trying to find a replacement. Chapter 3 shows us what is happening in the world of nonvolatile memories. A lot of energy is spent on such alternatives as resistive RAM (Re-RAM), magneto-resistive RAM (MRAM), or floating-body RAM (FB-RAM). The last alternative is the focal point of this chapter. According to the authors, floating-body DRAM seems to offer new ways of storing the charge and sensing it reliably and at the same time offering superior density and power performance.

CHAPTER 4: FOUR-STATE HYBRID SPINTRONICS–STRAINTRONICS: EXTREMELY LOW-POWER INFORMATION PROCESSING WITH MULTIFERROIC NANOMAGNETS POSSESSING BIAXIAL ANISOTROPY (Noel D’Souza, Jayasimha Atulasimha, and Supriyo Bandyopadhyay)

For the second time in this book we will be exploring nanotechnology; this time the focus is multiferroic nanomagnets. Multiferroic nanomagnets (consisting of piezoelectric and magnetostrictive layers) can be used as multistate switches to perform both Boolean and non-Boolean computing while dissipating only about a few hundreds of kT/bit of energy at clock rates of ~1GHz. At these power and speed levels, multiferroic nanomagnets can be used as memory elements for data storage, logic gates for Boolean computing, and associative memory for complex tasks such as ultrafast image reconstruction and pattern recognition.

CHAPTER 5: IMPROVEMENT AND APPLICATIONS OF LARGE-AREA FLEXIBLE ELECTRONICS WITH ORGANIC TRANSISTORS (Koichi Ishida, Hiroshi Fuketa, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, and Takayasu Sakurai)

Chapter 5 takes us into another popular and promising branch of electronics—organic transistors. Organic transistors offer completely new ways of building, integrating, and using electronic devices. With the advantage of the circuit integration on a plastic thin film with either printable or printing technology, the organic transistor is a promising candidate for realizing large-area flexible electronics. In this chapter, authors will present the most recent advancements in organic transistor technologies.

CHAPTER 6: SOFT-ERROR MITIGATION APPROACHES FOR HIGH-PERFORMANCE PROCESSOR MEMORIES (Lawrence T. Clark)

Chapter 6 brings up the well-known topic of soft errors. First DRAM, and then SRAM and logic designers have been dealing with soft errors for years. But as fabrication processes are reaching new scaling levels, the likelihood of radiation-induced bit upsets and logic transients in both terrestrial and aerospace environments is increasing and making their mitigation even more important. Several techniques have been developed to deal with soft errors, and this chapter investigates the efficiency of some of them, error detection and correction, redundancy, and error checking.

CHAPTER 7: DESIGN SPACE EXPLORATION OF WAVELENGTH-ROUTED OPTICAL NETWORKS-ON-CHIP TOPOLOGIES FOR 3D-STACKED MULTI- AND MANY-CORE PROCESSORS (Luca Ramini and Davide Bertozzi)

Chapter 7 introduces us to yet another new and very promising technology—photonics. Integration of many cores on the same chip has been discussed in Chapter 1. Solving interconnection problems has been identified as one of the many problems facing engineers working on the multicore, multichip designs. Photonic interconnect technology promises to lower the power and improve the bandwidth of multi- and many-core integrated systems. The presented material makes interesting insights into the latest developments in components, tools and technologies, and challenges preventing photonics from being widely adopted.

CHAPTER 8: QUEST FOR ENERGY EFFICIENCY IN DIGITAL SIGNAL PROCESSING: ARCHITECTURES, ALGORITHMS, AND SYSTEMS (Ramakrishnan Venkatasubramanian)

Cloud computing in a few short years turned from concept to reality. At the moment it is mostly associated with data storage, but imaging, video, and analytics processing in cloud-based computing and handheld devices is becoming increasingly common. Energy efficient digital signal processing (DSP) is key in delivering the best imaging and video experience at the lowest power budget. DSP architectures have evolved over the last three decades from simple vector co-processors to multicore DSP processor architecture-based systems to enable energy efficient DSP. This chapter explores the recent advances in industry and academia to solve this quest for DSP energy efficiency, holistically—in architecture, algorithms, and systems.

CHAPTER 9: NANOELECTROMECHANICAL RELAYS: AN ENERGY EFFICIENT ALTERNATIVE IN LOGIC DESIGN (Ramakrishnan Venkatasubramanian and Poras T. Balsara)

Lower power consumption is the ultimate goal of any design. And it does not apply to handheld, battery-powered devices only. Power consumption becomes important in all aspects of human life. The carbon dioxide footprint of large computer farms is something everyone is concerned with. The authors of this chapter introduce us to the concept of nanoelectromechanical (NEM) relays, which are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. The zero leakage operation of relays has renewed the interest in relay-based low-power logic design. This chapter covers the recent advances in relay-based logic design, memory design, and power electronics circuit design. NEM relays offer unprecedented 10X–30X energy efficiency improvement in logic design for low-frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well.

CHAPTER 10: HIGH PERFORMANCE AND CUSTOMIZABLE BIOINFORMATIC AND BIOMEDICAL VERY-LARGE-SCALE-INTEGRATION ARCHITECTURES (Yao Xin, Benben Liu, Ray C.C. Cheung, and Chao Wang)

Bioinformatics is an application of computer science and information technology to the field of biology and medicine. It is a hybrid and emerging field in which computational tools, information systems, databases, and methodologies supporting biology and genomic research are designed and developed. Challenges facing designers working in this field are the sheer amount of data and bandwidth needed to process high complexity algorithms. Off-the-shelf CPUs are operating close to their speed limits, therefore, new architectures are needed to supplement or replace them. This chapter presents two successful architectures designed for bioinformatic applications. The first one is called stochastic state point process filter (SSPPF), which is an effective tool for tracking coefficients in neural spiking activity research. And the second one is a parameterizable very-large-scale-integrated (VLSI) architecture for geometric biclustering developed for data mining operations.

CHAPTER 11: BASICS, APPLICATIONS, AND DESIGN OF REVERSIBLE CIRCUITS (Robert Wille)

Moore’s Law has been shaping the electronics industry for the last several decades. Even though it was declared dead many times, and so far prematurely, everybody expects that the ongoing miniaturization will eventually come to a halt. When feature sizes of a single transistor approach the atomic scale, no further improvement can be expected. Therefore, the search for alternative technologies continues. This chapter looks at a promising new computing paradigm called reversible computation. In a standard computation, the output does not always define the state of the inputs—for example, if the output of a two input AND gate is 0, the state of the inputs is not 100% determined. In contrast, reversible computation uses operations where inputs can be derived from outputs and vice versa. This characteristic leads to some interesting and promising applications. The author tries to show how reversible circuits can help to solve many practically relevant problems much faster than conventional solutions.

CHAPTER 12: THREE-DIMENSIONAL SPINTRONICS (Dorothée Petit, Rhodri Mansell, Amalio Fernández-Pacheco, JiHyun Lee, and Russell P. Cowburn)

In this chapter, we are looking one more time at nonvolatile storage memories. Alternatives to the standard charge storage NVM memories have been researched for many years. Spintronics is one of them, although much less advanced than memories based on magnetism, for example. Spintronics uses the spin and the charge of the electron to store the information. In this chapter, authors discuss the possibility of using spintronics to design three-dimensional, highly scalable, low-power, and radiation-hardened storage devices.

CHAPTER 13: SOFT-ERROR-AWARE POWER OPTIMIZATION USING DYNAMIC THRESHOLD (Selahattin Sayil)

Power consumption has been mentioned in books a few times as the limiting factor of further integration of integrated circuits. In this chapter, a technique to lower the power consumption is looked at from the reliability perspective. One common technique to lower power consumption is to lower the supply voltage level. This trend has been observed for years across all recent process nodes. Main voltage supply level dropped from 1.8 to 0.8–0.9 V for the most advanced 20- to 28-nm processes. IO voltage dropped at the same time from 5 to 2.5 V and now to 1.8 V. Reduction in voltage levels is possible by the reduction of threshold voltages to maintain the circuit speed and high current drive. However, lower threshold voltages mean higher sensitivity to soft errors. In this chapter, the author presents an analysis of various dynamic threshold voltage reduction techniques from the perspective of the soft error tolerance.

CHAPTER 14: THE FUTURE OF ASYNCHRONOUS LOGIC (Scott C. Smith and Jia Di)

This chapter talks about yet another way of overcoming the problem of scalability and increasing power consumption of the chips, which would allow even more complex and highly integrated applications—asynchronous logic.

Asynchronous logic is not a new idea; it has been discussed for many decades, but never became a mainstream design methodology. Synchronous circuits with well-established design flow and tools dominate the industry. But it is believed that asynchronous design will gain ground over the next 5–10 years. This chapter will provide the reader with more details about the state-of-the-art asynchronous logic, its current utilization in the industry, and its future.

CHAPTER 15: MEMRISTOR-CMOS-HYBRID SYNAPTIC DEVICES EXHIBITING SPIKE-TIMING-DEPENDENT PLASTICITY (Tetsuya Asai)

The synapse is a structure that allows one neuron to communicate with another one by sending an electrical or chemical signal. In this chapter, the author introduces a concept of an electronic system mimicking functions of a neuronal interconnect system by using nonvolatile resistors. Such a device would have the ability to update the synaptic connections based on spike timing differences between pre- and postneuronal devices. The synaptic device consists of a Re-RAM, a capacitor, and metal oxide semiconductor field effect transistors (MOSFETs). Through extensive experimental results, the author shows that the memristor-based synaptic device offers a promising alternative for the implementation of nonvolatile analog synapses.

CHAPTER 16: VERY-LARGE-SCALE INTEGRATION IMPLEMENTATIONS OF CRYPTOGRAPHIC ALGORITHMS (Tony Thomas)

The growth of the Internet and mobile communication technologies has increased the importance of cryptography in our day-to-day life. In the present day communication systems, high-speed hardware implementations of cryptographic algorithms for data encryption, cryptographic hashing, and digital signatures are required. This chapter examines the VLSI implementations of major symmetric and asymmetric key cryptographic algorithms, hash functions, and digital signatures.

CHAPTER 17: DYNAMIC INTRINSIC CHIP ID FOR HARDWARE SECURITY (Toshiaki Kirihata and Sami Rosenblatt)

Counterfeit devices have been in circulation for many years, either recovered from recycled equipment or stolen from the supply chain, in both cases endangering the reliability of sometimes live supporting systems. To keep the military, avionic, or health supply chains as safe as possible, engineers came up with very sophisticated counterfeit hardware. Conventional chip authentication procedures utilize markers such as bar codes or nonvolatile memory, which are extrinsic to the actual product and can be copied or transferred with inexpensive resources. In this chapter, authors describe an emerging approach to enable physically unclonable functions (PUFs) using intrinsic features of a VLSI chip.

Authors propose to use embedded dynamic random access memory (eDRAM) to create a PUF based on a skewed and controllable random bit pattern generator. The concept is demonstrated using IBM 32-nm high-K/metal gate eDRAM.

CHAPTER 18: ULTRA-LOW-POWER AUDIO COMMUNICATION SYSTEM FOR FULL IMPLANTABLE COCHLEAR IMPLANT APPLICATION (Yannick Vaiarello and Jonathan Laudanski)

Health care is the area where new VLSI circuits can make a big difference. From monitoring and communicating vital signs to administering drugs, integrated circuits can help do it all. But chips and systems built for medical applications are facing severe acceptance criteria. Usually they have to be small, consume low power, and they always have to be extremely reliable.

This chapter talks about chips for cochlear implants, a medical device that restores the hearing sensation. There are hundreds of thousands of people experiencing the loss of hearing to a smaller or larger degree. The authors present a wireless microphone chip designed in a 130-nm CMOS process for transmitting an audio signal to an implanted cochlear neurostimulator.

CHAPTER 19: HETEROGENEOUS MEMORY DESIGN (Chengen Yang, Zihan Xu, Chaitali Chakrabarti, and Yu Cao)

In this chapter, the authors look one more time at various memory technologies and introduce a new memory system, which they believe will work the best in sub-10-nm technologies. The authors argue that there will be no single winner in the battle to be the next technology of choice. Every new memory, whether phase change memory or spin-transfer torque magnetic memory, has its advantages but none will be flexible enough to dominate the market. That is why the authors’ heterogeneous memory system, which combines advantages of the different memory technologies to deliver superior system performance, seems to offer the best of all solutions. The authors try to show how the integration of multiple memory technologies at the same level can be used to improve system latency and energy, providing superior reliability at the same time.

CHAPTER 20: SOFT-ERROR RESILIENT CIRCUIT DESIGN (Chia-Hsiang Chen, Phil Knag, and Zhengya Zhang)

In this final chapter the authors talk about soft errors and how designers are trying to build circuits that can be more resistant and work in environments where the probability of encountering soft errors is high. Research on soft errors started in the early 1970s when it was understood that the main source of particles that can create soft errors were actually integrated circuit packages. As packages evolved and contained fewer and fewer compounds creating alpha particles, the focus shifted toward cosmic rays. Techniques to combat soft errors were introduced at device and system levels. Authors are reviewing a few of them, such as a circuit-level hardening technique called dual interlocked storage cells, built-in soft error resilience elements, and more.

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