Index
Δ∑ analog-to-digital converter (ADC), 97
λ-router topology, layout, 169
23 by 3-bit reciprocal ROM, 43, 44
3DES, see Triple Data Encryption Standard
3D stacked integrated systems, 153
3D Tri-Gate transistors, 58
4 × 4 generalized wavelength-routed optical router (GWOR), 151
4 × 4 nonblocking nanophotonic switching node, 151
4 × 4 optical turnaround-router, 151
4-bit by 4-bit array multiplier, 33, 34
4-bit by 4-bit Wallace multiplier, 35–38
6 transistor (6T) SRAM cell approach, 360
8-bit by 8-bit array multiplier, 33, 35
8-bit by 8-bit Wallace multiplier, 35–38
8-bit microprocessor on plastic foil, 96
12-bit Goldschmidt divider, 42, 45–46
20 V CMOS, 106
100 V AC Energy Meter, 104–106
A
Accelerated Massive Parallelism (AMP), 9
Accelerated processing units (APUs), 3
area and power implications in, 10–11
ACE, see Achronix CAD Environment
Achronix, 322
Achronix CAD Environment (ACE), 322, 323
Adders, QCA, 20
types of, 16
for Wallace multipliers, 37
Additive and multiplicative pattern plot (AMPP), 238
Advanced Encryption Standard (AES) block cipher, 345–347
AES block cipher, see Advanced Encryption Standard block cipher
Algorithms
bioinformatics and biomedical, 230–232
block diagram of, 5
AMP, see Accelerated Massive Parallelism Amplifiers, 395, 396
AMPP, see Additive and multiplicative pattern plot
Analog demodulation receiver, principle of, 402, 403
Analog to time converter, 397, 398
Anisotropy
Antiferromagnetic (AF) coupling, 78, 81
Application processor, real-time processing-DSP vs., 184–185
Application-specific DSP (AS-DSP), 181
Application-specific integrated circuits (ASICs), 84
implementation, of SHA-3, 352–353
APUs, see Accelerated processing units
A2RAM memory cell
experimental electrical results, 53–58
memory states, 52
source and drain regions, 51
three words/three bits memory matrix, 56–58
Architecture design
customizable VLSI architecture, for compute-intensive, 249–253
scalable VLSI architecture, for data-intensive, 241–243
Architecture (hardware platform), DSP, 196–199
ARM® CorePac, 197
Array bit pattern (BITMAP), 364–366
Array multipliers, 44
AS-DSP, see Application-specific DSP
ASICs, see Application-specific integrated circuits
Asymmetric encryption, 340
Asymmetric-key algorithms, 338, 340
Asynchronous logic circuits, 311–313
NULL convention logic, 313–319
Automatic voltage scaling (AVS), 181
AVS, see Automatic voltage scaling
B
Band-to-band (BTB) tunneling, 53, 55–61
BCDMR, see Bistable cross-coupled dual modular redundancy
clock cycle and stress sequences, 82
of two-state logic chains, 70
BER, see Bit error rate
Bias sequence, A2RAM memory cell, 53, 54
Biaxial anisotropy
applications of nanomagnets, see Nanomagnets
four-state nanomagnets, 70, 71
Bilayer multiferroic nanomagnet, 69
Bioinformatics and biomedical engineering, 230–233
Bio-sequence, analysis for, 231–232
Bipolar junction transistor (BJT) programming technique, 51
Bipolar ReRAM, array of, 327, 328
BISER, see Built-in soft-error resilience
Bistable cross-coupled dual modular redundancy (BCDMR), 437
BIST engine, see Built-in-self-test engine
Bitcell architectures, NEM relays comparison, 220–225
Bit cell upsets, 131
Bit error rate (BER), 422
Bit-level parallelism, 235
Bit line (BL)
read, 129
values, 118
BJT programming technique, see Bipolar junction transistor programming technique
Block ciphers, 339
embeddings of, 269
Boolean synthesis approaches, 270–271
Borophosphosilicate glass (BPSG), 116
Bounded-delay model, 311
BPSG, see Borophosphosilicate glass
BTB tunneling, see Band-to-band tunneling
Built-in-self-test (BIST) engine, 361
Built-in soft-error resilience (BISER), 435–437
Burrows-Wheeler transform, 231
C
Cache bank clocks, 129
Cache error detection circuits, 124–125
Cache memory, 113
CAD tools, see Computer-aided design tools Camgian Microsystems, 321
Cantilever beam-based NEM relay, 206, 207
Carry-flow ripple carry adder (CFA), 21–22
Carry lookahead adder (CLA), 23–28
Casimir force, 209
CDC, see Confidence-driven computing
CDW, see Computational density per watt
CE, see Confidence estimator
Central processing units (CPU)
programming and memory models, 8–10
three-dimensional integration of, 7
CFA, see Carry-flow ripple carry adder
Checksums, 340
Chip identification, evolution of, 358
Chip microphotograph, of eDRAM array, 373
Circuit nodes, engineering of, 430
CLA, see Carry lookahead adder
Classic single-core DSP, 186
Clocking nanomagnetic logic, 66–68
with multiferroic nanomagnets, 69–70
Clock management, FPGA, 241
Clock-shift temporal redundancy, 437, 438
C-memristor circuit, conductance modulation and readout circuitry in, 326, 327
CMOS, see Complementary metal-oxide-semiconductor
CMOS-ReRAM-hybrid synaptic circuit, 326–327
Cochlear implant system, 390
inner ear pathology and, 392
Combination process, GBC, 239–241
Commercial applications, soft-error resilient circuit design, 444–445
Communication link budget, 395
Comparator, 398
Complementary metal-oxide-semiconductor (CMOS), 204
replacement devices, see Mechanical relays
role of, 16
Complementary metal-oxide-semiconductor molecular (CMOL) architecture, 334
Computational density per watt (CDW), 190–191
Compute-intensive application, 236
customizable VLSI architecture for, see Customizable VLSI architecture, for compute-intensive
Computer-aided design (CAD) tools, 166
Compute Unified Device Architecture (CUDA), 8–9
Conditional sum adder (CSAs), 28–31
Conductance-preservation law, 326
Confidence-driven computing (CDC), 441–442
Confidence estimator (CE), 441, 442
ControlledNOT (CNOT) gate, 265
Controlled square-root-of-NOT gates, 265
ControlledV gate, 265
ControlledV+ gate, 265
Convex channel 1T-DRAM structure, 50, 51
Coplanar “wire” crossing, 18–19
CPU, see Central processing units
Critical charge
values for various dynamic threshold inverter schemes, 305
Cross-coupled inverter approach, 360
Cross-layer resilient architecture, 443
Cryptographic algorithms, 338
Cryptographic hash function, 340
Crystalline silicon microring resonator electrooptic modulators, 150
CSAs, see Conditional sum adder
CUDA, see Compute Unified Device Architecture
Customizable VLSI architecture, for compute-intensive, 246–247
D
DARPA computing, see Defense Advanced Research Projects Agency computing
Data controller, FPGA, 241–242
Data Encryption Standard (DES) block cipher, 343–345
Data-intensive applications, 236
scalable VLSI architecture for, see Scalable VLSI architecture, for data-intensive
Data-intensive problem, 241
Data-level parallelism, 235, 236, 241
DATA/NULL cycle time, 316, 317
Data storage time (DST), 421
Data structure, GBC accelerator, 243
Defense Advanced Research Projects Agency (DARPA) computing, 182–184
Delay-based PUF, 361
Dense Linear Algebra dwarf, 236
Deposited silicon nitride waveguides, 150
DES block cipher, see Data Encryption Standard block cipher
Design predictability gap, 156
cause for, 149
DHA, see Duplicated half adder
DICE, see Dual interlocked storage cell
Diffie-Hellman key exchange protocol, 350
Digital signal processing (DSP)
application processors and GPU comparison, 184–186
compute and memory bandwidth trends, 180–184
dynamic range and precision, 188–189
fixed and floating point convergence, 189–190
fixed vs. floating point, 187–188
Dipolar interaction, effect of, 284–287
Divide and Conquer method, 235
DMR RFs, see Dual mode redundancy RFs
DNTT-based pMOS transistor, 106
Domain-specific DSP (DS-DSP), 181
Doping, of triple-gate A2RAM, 58, 59
Dot diagram
of 8-bit by 8-bit Wallace multiplier, 37
of 4-bit by 4-bit Wallace reductions, 36
Double sampling sequential circuits, 439–441
DS-DSP, see Domain-specific DSP
DSP, see Digital signal processing
DSP CorePac, 197
DST, see Data storage time
DTMOS, see Dynamic threshold MOS
Dual interlocked storage cell (DICE), 430–433
Dual mode redundancy (DMR) RFs, 136–143
Duplicated half adder (DHA), 29–31
DVFS, see Dynamic voltage and frequency system
Dwarf, 235
Dynamic intrinsic chip ID, 366–372
hardware authentication, 373–374
Dynamic micro-ID approach, 385
Dynamic threshold MOS (DTMOS), 296, 299–304
Dynamic threshold techniques, soft-error-aware power optimization via, 299–305
Dynamic voltage and frequency system (DVFS), 3
E
Ear, and hearing brain, 390–391
EC, see Error checker
ECC, see Elliptic curve cryptosystem; Error control coding
ECDLP, see Elliptic curve discrete logarithm problem
EDAC, see Error detection and correction
EDE mode, see Encryption-Decryption-Encryption mode
eDRAM, see Embedded dynamic random-access memory
eFUSE approach, see Electrically blowable fuse approach
Electrically blowable fuse (eFUSE) approach, 358
Electrical masking, 297
Electromagnetic interference (EMI) measurement sheet, 98–100
Electromechanical system model, 208–210
Electrooptic modulator, 150
Electrostatically actuated NEM relay devices, 205–206
Elimination module, SSPPF architecture, 251, 252
Elliptic curve cryptosystem (ECC), 349–351
Elliptic curve discrete logarithm problem (ECDLP), 350
Embedded dynamic random-access memory (eDRAM), 359, 362
Embedded processing SoCs, 198
EMI measurement sheet, see Electromagnetic interference measurement sheet
Encryption-Decryption-Encryption (EDE) mode, 343
End of conversion signal (EOC), 400
Energy efficiency, DSP
in memory and IO interfaces, 194–195
Energy harvesting, 103
EOC, see End of conversion signal
Error checker (EC)
area impact, 129
circuit, 125
Error control coding (ECC), 118, 422
Error detection and correction (EDAC), 135–136
Error resilient system architecture (ERSA), probabilistic applications, 442–443
ERSA, see Error resilient system architecture
ExaFLOPs, 183
F
FA, see Full adder
Fabrication, A2RAM memory cell, 52–53
Failure-in-time (FIT), 298
Fat Tree-based Optical NoC topologies (FONoCs), 151
FB-DRAMs, see Floating-body dynamic random-access memory
Ferromagnetic (F) coupling, 78, 81
Ferromagnetic multilayer scheme, 74
Field-programmable gate arrays (FPGAs), 230, 234
components in, 241
Field-tolerant approach, 381–382
Field-tolerant intrinsic chip ID, 374–379
hardware authentication, 379–381
Filter-based topology, optical ring vs., 172–175
Fingerprints, 359
FIT, see Failure-in-time
Floating-body dynamic random-access memory (FB-DRAMs), 49
Floating point convergence, fixed and, 189–190
FM multilayer scheme, see Ferromagnetic multilayer scheme
Folded cascode OTA operational amplifie, 397
Folded crossbar, 162
layout, 169
FONoCs, see Fat Tree-based Optical NoC topologies
Four-state nanomagnets, biaxial anisotropy, 70, 71
FPGAs, see Field-programmable gate arrays
Freescale’s QorIQ Qonverge, 199
Fulcrum Microsystems, 322
Full adder (FA), 16
Full implantable device, 392–393
Fully printed organic circuits, 97
G
Gate array (G/A) architectures, 101
GBLs, see Global bit lines
GCN, see Graphics Core Next
Generalized Laguerre-Volterra model (GLVM), 247–248
General-purpose CPU vendors, 234
General purpose DSP (GP-DSP), 181
General-purpose GPU (GPGPU)
programming, 8
Generic wavelength-routed optical router (GWOR), 157
layout, 169
Geometric biclustering (GBC), 237–238
accelerator, optimization of, 244–246
work flow, 238
Giant magnetoresistance (GMR) scheme, 73–74
Global bit lines (GBLs), 120, 122
precharge, 128
Global clocking, 68
Global connectivity
vs. network partitioning, 172
wavelength-routed topologies, 159–161
GLVM, see Generalized Laguerre-Volterra model
GMAC scaling, 187
GMR scheme, see Giant magnetoresistance scheme
Goldschmidt divider, QCA, 39
GP-DSP, see General purpose DSP
GPU, see Graphics processing units
Graphics, 2
Graphics Core Next (GCN), 9–10
Graphics processing units (GPU)
as first-class processors, 11–12
programming and memory models, 8–10
three-dimensional integration of, 7
Graph Traversal dwarf, 236
GWOR, see Generic wavelength-routed optical router
H
Hamming, 422
Hardening, SDEs, 306
Hard errors, 421
Hardware identification method, 358
Hardware Multicore Parallel Programming (HMPP), 9
Hash codes, 340
Hash functions, 340
Hash values, 340
HBM, see High-Bandwidth Memory Interface
Hearing, pathologies of, 391–393
Hearing prothesis, pathologies of, 391–393
Heterogeneous memory system
architecture for main memory, 419–420
nonvolatile memories, see Nonvolatile memories (NVMs)
Heterogeneous multicore platform, 197–199
Heterogeneous System Architecture (HSA), 10
High-Bandwidth Memory Interface (HBM), 194
Highly reliable cores (SRCs), 443
High-performance computing (HPC), 182–184
defined as, 233
High-performance computing (HPC) space
DSPs in, 180
multicore SoC complexity, 199
High-performance embedded-dynamic random access memory, 362–364
High-performance very-large-scale integration, 233–237
HMC, see Hybrid Memory Cube
HMPP, see Hardware Multicore Parallel Programming
Hough transform (HT), 238
HPC, see High-performance computing
HSA, see Heterogeneous System Architecture
HT, see Hough transform
Hybrid design technique, 230
Hybrid Memory Cube (HMC), 194
“Hybrid spintronics and straintronics” scheme, 69
Hypergraph partitioning method, 246
I
IDLE/Standby power management, 196
IHCs, see Inner hair cells
Image recovery, nanomagnets, 84–89
Inner ear
pathology and cochlear implants, 392
transducing hydraulic waves into electric signals, 391
Inner hair cells (IHCs), 391
Input-output (IO) bandwidth, vs. latency comparison, 195
Insertion loss, relative topology, 161–162
Insole pedometer, with piezoelectric energy harvester, 103–104
Instruction-level parallelism, 235
Instruction Set Architecture (ISA), 10
Instructions per cycle (IPC), of PRAM and STT-MRAM heterogeneous main memories, 418, 419
Integrated charge-boosting flip-flop, 216–218
Integrated CPU-GPU cores, case study of, 3–5
Integrated GPU, benefits of, 2–3
Integrator topology, 398
block diagram of, 6
International Technology Roadmap for Semiconductors (ITRS), 205
asynchronous circuits, 311, 323
Intrinsic capacitance of relay, 210–211
dynamic, see Dynamic intrinsic chip ID
security and authentication enhancement for, 381–384
Inverters, QCA, 18
ISA, see Instruction Set Architecture
ITRS, see International Technology Roadmap for Semiconductors
K
Karnaugh-map, 77
k-bit decoder, 244
Keystone Multicore SoC, 197–198
Keystone software platform, 199
k1MTM_k2RMT module, SSPPF architecture, 253
L
Landauer limit, 266
Landau-Lifshitz-Gilbert (LLG) equation, 85–86
Large-area flexible electronics applications
100 V AC Energy Meter, 104–106
insole pedometer with piezoelectric energy harvester, 103–104
stretchable EMI measurement sheet, 98–100
Laser sources, silicon photonics, 152–153
Laterally actuated NEM relays, 206
Late-way-select architecture, 113
LBL, see Local bitline
L2 caches, 119
LET, see Linear energy transfer
LFSRs, see Linear Feedback Shift Registers
Linear energy transfer (LET), 115–116
Linear Feedback Shift Registers (LFSRs), 339
LLG equation, see Landau-Lifshitz-Gilbert equation
Local clocking, 68
of magnets, 69
Logical masking, 297
Logic computations, defined as, 262
Logic propagation, nanomagnets, 80–84
Logic topologies, wavelength-routed topologies, 160, 166–168
Low-k MOX, 51
Low power compensation system architecture, 400
Low-voltage organic complementary metal-oxide-semiconductor (CMOS) circuit, 97
M
Magnetic multilayers, topological kink solitons in, 277–278
Magnetic quantum cellular automata, 66
Magnetic tunneling junction (MTJ), 411
Magnetocrystalline anisotropy, 71, 72
Matrix inversion module, SSPPF architecture, 251, 252
MCUs, see Multicell upsets
Mean squared error (MSE), 254, 256
Mechanical relays
electrostatically actuated NEM relay devices, 205–206
Memory
cache, 113
device operation and performance of, 408
energy efficiency in, 194
FB-DRAMs, 49
high-performance embedded-dynamic random access memory, 362–364
phase-change memory, see Phase-change memory (PRAM)
quantum well floating-body dynamic random-access memory, 50–51
Memory array soft errors, 130–131
Memory controller, FPGA, 241
Memory model, 10
Memory scrubbing, EDAC, 135–136
Memristor-based STDP synaptic device, 334
Memristor STDP circuit, fundamental unit of, 326
Metal-oxide-semiconductor FET (MOSFET), 205
MHAs, see Modified half adders
Micromagnetic calculations, 287–291
Micro-multiple ID approach, 385
Microphones, acquisition and amplifier output, 402
Microprocessor, trends of, 1–2
Middle ear
acoustics to mechanics waves, 390–391
pathologies and implants, 392
MINs, see Multistage interconnection networks
MMI tapers, see Multimode interference tapers
Mobile camera sensor, 182, 183
Modes of operation, for block ciphers, 339–340
Modified half adders (MHAs), 29–31
Modular multiplication, 348, 349
Modulators, silicon photonics, 150–151
MOSFET, see Metal-oxide-semiconductor FET
Most significant bits (MSBs), 349
MSBs, see Most significant bits
MSE, see Mean squared error
MTJ, see Magnetic tunneling junction
Multibody floating-body-1T-dynamic random-access memory, 50–51
Multicell upsets (MCUs), 136
Multicore systems, DSP, single-core vs., 186
Multiferroic nanomagnet, transfer function of, 90
Multilayer “wire” crossing, 19
adder comparisons with, 32
Multimode interference (MMI) tapers, 150, 170, 172, 174
Multi-output Boolean function, 262–263
comparison of, 39
Multistage interconnection networks (MINs), 156
N
Nanoelectromechanical (NEM) relays, 206–208
electrostatically actuated, 205–206
parameter, definition of, 208
Nanoelectromechanical (NEM) voltage doubler, 216–217
Nanomagnet-based computing architectures, 66
Nanomagnetic logic (NML), 66
Nanomagnets
image reconstruction and pattern recognition, 84–89
NanoWatt Design, 321
NCV gate library, 265
NCV-4 gate library, 265
NEM relay-based digital logic design
intrinsic capacitance of, 210–211
performance, energy, and area comparison, 214–215
relay-based flop circuits, 212–214
relay-based latch circuits, 211–212
using charge boosting, performance improvement of, 215–218
NEM relay-based memory design
bitcell architectures comparison, 220–225
Network partitioning
global connectivity vs., 172
logic schemes, 168
wavelength-routed topologies, 166
Neural coding, 232
Neurons, 231
Neutron-induced soft errors, 296
NML, see Nanomagnetic logic
NM multilayer scheme, Nonmagnetic multilayer scheme
Node engineering approaches, 431
Nonmagnetic (NM) multilayer scheme, 74
Nonvolatile memories (NVMs), 408
energy and latency comparison, 413–415
spin torque transfer magnetic random-access memory, 411–412
Normalized instructions per cycle (IPC), PRAM, 416, 418
NOT gate, 265
N PEs processing, FPGA, 242
N single-bit dual-rail NCL registers, 315, 316
n-type metal-oxide-semiconductor (nMOS) transistors, 96
NULL convention logic circuits, 313–319
NVMs, see Nonvolatile memories
O
OEM, see Original Equipment Manufacturer
OHC, see Outer hair cells
On-chip embedded SRAM, 194
One-time programmable read-only memory (OTPROM), 358
One-transistor and one capacitor (1T1C), 362
ONoCs, see Optical networks-on-chip
On-off keying (OOK) modulation, 394, 395
OOK modulation, see On-off keying modulation
OpenCL, see Open Computing Language
Open Computing Language (OpenCL), 9
Operating system (OS), CPU and GPU, 11–12
Optical communication channels, structures for, 150
Optical network interface architecture, 165
Optical networks-on-chip (ONoCs), 148
Optical ring topology, 164–166
vs. filter-based topology, 172–175
Optics, 148
Optimization, reversible circuits, 271
Optimized NULL convention logic full adder, 318, 319
Original Equipment Manufacturer (OEM), 365–366
database, 382
OS, see Operating system
OTPROM, see One-time programmable read-only memory
Outer ear, acoustics to mechanics waves, 390–391
Outer hair cells (OHC), 391
Out-of-plane excursion, 86–87, 89
P
Paging mechanism, CPU, 7
Parallel computing applications, 236
Parallelism exploration
for GBC combination process, 241
Parallelism, levels of, 235
Parallel 4R RAM bitcell (P4RRAM), 218–219
Parallel 3R RAM bitcell (P3RRAM), 220, 221
Parallel VLSI architecture, for SSPPF, 250
Patent-pending technology, 322
Pattern recognition, nanomagnets, 84–89
pbm, see Probability based mapping
PCHB circuits, see Precharge half buffers circuits
PERFECT program, see Power Efficiency Revolution For Embedded Computing Technologies program
Performance metrics, bitcell architectures, 222
PEs, see Processing elements
Phase-change memory (PRAM), 409–411
Phase lock loop (PLL), 129
Photodetectors, 152
Photonic interconnect technology, 148
Photonic switching elements (PSEs), 151–152
Physical gap, 155
Physically Unclonable Function (PUF), 359
Physical topologies, wavelength-routed topologies, 168–170
Pipelining, 250
Placement constraints, role of, 158
PLL, see Phase lock loop
pMOS transistor, see p-type metal-oxide-semiconductor transistor
Polyvinylidene difluoride (PVDF) sheet, 103
Power dissipation, radiation hardening, 124
Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program, 184
Power efficiency, wavelength-routed topologies, 170–172
Power-efficient CMO, 200
Power gating, 4
PRAM, see Phase-change memory
Precharge half buffers (PCHB) circuits, 319–320
Predictability-critical optical networks-on-chip topologies, 155–156
Primitive memristor, experimental results of, 327, 328
Private key cryptosystem, 338
Probability based mapping (pbm), 267
Processing elements (PEs), 236
architecture of, 242
internal structure of, 244–245
Processor-memory communication, custom-tailored solution for, 167
Programming model, 10
Propagation channel, 393
Proton testing, 143
P4RRAM, see Parallel 4R RAM bitcell
PSEs, see Photonic switching elements
Pseudorandom keystream, 339
P3RRAM, see Parallel 3R RAM bitcell
p-type metal-oxide-semiconductor (pMOS) transistor, 96, 114, 115, 298
Public-key algorithms, 338
Public-key cryptosystem, 338
Public-key encryption, 340
PUF, see Physically Unclonable Function
PVDF sheet, see Polyvinylidene difluoride sheet
Q
QCA, see Quantum-dot cellular automata
QDI, see Quasi-delay-insensitive
Quantum-dot cellular automata (QCA)
adders, see Adders, QCA
design rules, 20
Goldschmidt divider, see Goldschmidt divider, QCA
multipliers, see Multipliers, QCA
types of, 16
Quantum dot lasers, 153
Quantum gates, universal set of, 265
Quantum well floating-body dynamic random-access memory, 50–51
Quasi-delay-insensitive (QDI), 312, 323
R
RAD750, 112
Radiation hardened by design (RHBD) processors, 112
Radiation-hardened microprocessors, 112
Radiation hardening, by design DMR RFs, 136–137
Radiation hardening, Level 1 cache design
power dissipation, 124
single event effect (SEE) hardness, 130–134
speed and power measurement, 129–130
Radio-frequency identifications (RFIDs), 96
Random dopant fluctuation (RDF), 412
RAT, see Read access time
Razor doubling sampling techniques, 439–441
RBL, see Read bitline
RDF, see Random dopant fluctuation
Read access time (RAT), 219
Read bitline (RBL), 219
Read word line (RWL) errors, 138
Real-time processing-DSP vs. application processor, 184–185
Reduced instruction set computer (RISC), 186
Register-transfer level (RTL) description, 353
Relative topology, comparison of, 161–164
Relaxed reliability cores (RRCs), 443
Relay-based flop circuits, 212–214
Relay-based latch circuits, 211–212
ReRAM-CMOS-hybrid synaptic devices, experimental results, 331–334
Retention-based intrinsic chip ID, 364–366, 371
probability of uniqueness of, 372
Retention time, A2RAM memory cell, 55–56
Reversible circuits
in design of low-power encoders, 267–268
to quantum circuits, mapping, 264–266
verification and debugging, 271
RFIDs, see Radio-frequency identifications
RFs, see Register files
RHBD processors, see Radiation hardened by design processors
Ring-oscillator (RO)-based PUFs, 361
Ring topology, layout, 169
RISC, see Reduced instruction set computer
RKKY coupling, see Ruderman-Kittel-Kasuya-Yosida coupling
RRCs, see Relaxed reliability cores
RSA asymmetric-key cryptosystem, 347
encryption and decryption algorithms, 347–348
RTL description, see Register-transfer level description
Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling, 276, 284
RWL errors, see Read word line errors
S
SAFs, see Synthetic antiferromagnets
SAM technology, see Self-assembled monolayer technology
S-box RAM, 342
Scalable VLSI architecture, for data-intensive
geometric biclustering, 237–241
Scaled systems, optical ring vs. filter-based topology in, 172–175
Scaled technologies, energy and latency comparison in, 413–415
SCL technology, see Sleep convention logic technology
SDC error, see Silent data corruption error
SDEs, see Soft delay errors
SDPPF, see Steepest decent point process filter
Sea-of transmission-gates (SOTG), 100–103
Second generation of A-RAM cell, see A2RAM memory cell
Secret-key algorithms, 338
Self-assembled monolayer (SAM) technology, 96
Semiconductor QCA, 16
SERs, see Soft-error rates
SE soft errors, see Single-event soft errors
SET, see Single event transient
SET-induced peripheral circuit errors, 132
SEU, see Single event upset
SF process, see Slow-Fast process
Silent data corruption (SDC) error, 117–118
Silicon, 149
Silicon electrooptic modulator, 150
Silicon-on-insulator (SOI) transistor, 49
Silicon photonics, 148
photonic switching elements and ONoCs optical routers, 151–152
SIMD, see Single-instruction multiple data
Simulation Program with Integrated Circuit Emphasis (SPICE) parameters, 410–412
Simulink simulation framework, 162
Single-bit dual-rail register, 315
Single-chip consumer applications, error rate, 298–299
Single-core DSP, vs. multicore, 186
Single-cycle Level 1 (L1) caches, 112–113, 118–119
Single-domain nanomagnet, 66
Single event effect (SEE), 114, 117–118
testing, radiation hardening, 139–143
Single event effect (SEE) hardness
memory array soft errors, 130–131
tag peripheral circuit errors, 132
testing, 130
Single-event (SE) soft errors, 296–299
Single event transient (SET), 115
Single event upset (SEU), 114, 297
error checking in periphery circuits, 125–129
Single-instruction multiple data (SIMD)
processing unit, 4
VLIW and, 185
Single-precision floating-point operation, 188
Single Spin Logic paradigm, 66
Sleep convention logic (SCL) technology, 321–322
Slow-Fast (SF) process, 401
layout, 169
SNM approach, see Static-noise margin approach
SNR, see Storage node refresh
Soft delay effects, 298
Soft delay errors (SDEs), 297–298
Soft-error-aware power optimization, via dynamic threshold techniques, 299–305
Soft-error hardened (SEH)
Soft-error mechanisms, 114–115
charge collection physics, 115–116
circuit cross-section measurements, 116
Soft-error rates (SERs), 298
Soft-error resilient circuit design
commercial applications, 444–445
confidence-driven computing, 441–442
probabilistic applications, error resilient system architecture, 442–443
temporal redundancy techniques, 437–439
Software-controlled repair mechanisms, 138–139
Software execution platform, SSPPF, 255–257
Software reference design, 246
SOI transistor, see Silicon-on-insulator transistor
Soliton mobility
Soliton-soliton interaction, 283
SOTG, see Sea-of transmission-gates
Space-routed torus, 157
Space routing, 151
SPARC AT697, 112
SPICE parameters, see Simulation Program with Integrated Circuit Emphasis parameters
Spin-transfer torque magnetic random-access memory (STT-MRAM), 411–412
Sponge function, 352
SRAM, see Static random-access memory
SSPPF, see Stochastic state point process filter
Stability metrics, bitcell architectures, 222
Stack edge effects, 281
Stacked transistor approach, 444
Static-noise margin (SNM) approach, 360, 361
Static random-access memory (SRAM), 112–113
Steepest decent point process filter (SDPPF), 248
Stochastic state point process filter (SSPPF), 230, 247–248
Storage node refresh (SNR), 220, 221
Stream cipher, 339
Stream generation, by RC4 cipher, 342
STT-MRAM, see Spin-transfer torque magnetic random-access memory
Stuck-SET failure, 422
Submicrometer crystalline silicon waveguides, 150
Suspended gate relays, 206–208
Symmetric-key algorithms, 338
Synthesis approaches, reversible circuits, 270–271
Synthetic antiferromagnets (SAFs), 88–89
Systemability concern, 155
T
Tag comparators, 129
Tag peripheral circuit errors, 132
Task-level parallelism, 235
Tclk-Q delay, 214
Temporal masking, 297
Temporal redundancy techniques, 437–439
Theseus Logic, 321
Three-dimensional spintronics
dipolar interaction effect, 284–287
micromagnetic calculations, 287–291
Three-relay random access memory (3RRAM), 218, 219
Through-silicon vias (TSV) technologies, 194
TH34w2 Gate, 314
TI 66AK2E05, embedded processing SoCs, 198
TI 66AK2H12, embedded processing SoCs, 198
Tiempo, 321
Time-shift temporal redundancy, 438–439
TI TDA2X, embedded processing SoCs, 198
TMR, see Tunneling magnetoresistance
Toffoli gate, 263
Transition-detection temporal redundancy, 438
Transmission electron microscopy, of A2RAM memory cell, 52
Transmitters
internal analog signal of, 403
layout of, 401
spectrum of, 404
test printed circuit board, 402
Tridimensional A2RAM memory cell, 58–61
Triple Data Encryption Standard (3DES), 343–345
TSV technologies, see Through-silicon vias technologies
Tunneling magnetoresistance (TMR), 411
Two-relay random access memory (2RRAM), 218, 219
U
UCLP, see User customizable logic paper
Ultra-low-power audio communication system, see also Cochlear implant system
implementation and experimental results, 401–405
Unidirectional propagation, soliton stability, 282–283
Universal logic gates, nanomagnets, 74–80
User customizable logic paper (UCLP), 100–103
V
Van der Waals’ force, 209
Vector processing method, 251
Verilog-A model, of suspended gate relay, 208–210
Very-large-scale-integration (VLSIs), 240
high-performance multilevel parallel designs, 234–237
Very-large-scale integration (VLSI) implementations, 230
of cryptographic primitives, 339–340
in RSA asymmetric-key cryptosystem, 347–349
of SHA-3 hash function, 351–353
Very long instruction word (VLIW)
core, 4
and SIMD, 185
V gates, 265
V+ gates, 265
VLIW, see Very long instruction word
VLSI/FPGA parallel architectures, 235
VLSIs, see Very-large-scale-integration
Voice activation application, 196
VWL, see Wordline low voltage
VWLH, see Wordline high voltage
W
Wallace multipliers, for QCA, 33–38
Waveguide crossings, 150
Waveguide, optical link, 149–150
Wavelength division multiplexing (WDM), 150
Wavelength-routed Δ∑-router, 157
Wavelength-routed ONoC (WRONoC) topologies, 151, 155, 156
Wavelength-routed topologies, design space exploration of, 158–159
network partitioning, global connectivity vs., 172
optical ring topology comparison, 164–166
relative topology comparison, 161–164
WDM, see Wavelength division multiplexing
Weighted threshold gate, 313–314
Window Rule, 368
Wireless microphone design
assertion, 126
Wordline high voltage (VWLH), 361
Wordline low voltage (VWL), 363, 365
Write-back (WB)
cache, 119
error, 140
Write bit line and enable assertion, 128
Write word line (WWL)
checking circuit, 136
error, 140
WRONoC topologies, see Wavelength-routed ONoC topologies
WWL, see Write word line
Z
Zero-temperature macrospin simulations, 278