Challenges to Ultralow-Power Semiconductor Device Operation

Francis Balestra

IMEP-LAHC, Minatec, Grenoble-Alpes University, 38016 Grenoble Cedex 1, France

1 Introduction

The historic trend in micro-/nanoelectronics over the last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition, and to develop many novel functionalities for future electronic systems. We are facing today dramatic challenges for “more Moore” and “more than Moore” applications: substantial increase of energy consumption and heating that can jeopardize future IC integration and performance, reduced performance due to limitation in traditional high-conductivity metal/low-κ dielectric interconnects, limit of optical lithography, heterogeneous integration of new functionalities for future nanosystems, and so on.

Therefore, many breakthroughs, disruptive technologies, novel materials, and innovative devices are needed in the next two decades.

With respect to the substantial reduction of the static and dynamic power of future high-performance/ultralow-power terascale integration logic and autonomous nanosystems, new materials and novel device architectures are mandatory for ultimate complementary metal-oxide-semiconductor (CMOS) and beyond-CMOS eras, as well as new circuit design techniques, architectures, and embedded software.

Alternative memories, especially PCRAM, RRAM, or MRAM will be useful for pushing the limit of integration and performance beyond those afforded by present nonvolatile, DRAM and SRAM memories.

In the interconnect area, optical and RF interconnects, carbon or other 2D materials can overcome the present limitations of copper interconnects for power consumption and performance.

Concerning ultimate processing technologies, extreme ultraviolet (EUV) lithography, immersion multiple patterning, multi-e-beam maskless or imprint lithography, as well as self-assembly of nanodevices could be used for different applications.

Future autonomous nanosystems will also need the development of nanoscale high-performance novel functionalities, which could be integrated on CMOS platforms. In this respect, nanostructures and nanodevices, especially nanowires (NWs), are of great interest, for instance, for improving the sensitivity, resolution, selectivity, energy consumption, and response time of nanosensors, and for solar, mechanical, and thermal energy harvesting.

Parallel or sequential processes could be used for the integration of these future high-performance and low-power sustainable, secure, ubiquitous and pervasive systems, which will be of high added value for many applications in the field of (autonomous) detection and communication of health problems, environment quality and security, secure transport, building and industrial monitoring, entertainment, education, and so on.^1–14

This chapter focuses on the main trends, challenges, limits, and possible solutions for ultralow-power nanoscale devices in the CMOS and beyond-CMOS arena, including many novel materials, ultrathin films, multigates, nanowires, and small slope switches.

2 Ultimate MOS transistors

The slowdown of V_DD scaling and the substantial increase of the subthreshold leakage lead to a dramatic enhancement of the dynamic and static power consumption. This power challenge is due to the subthreshold slope limit S, which is 60 mV/dec at room temperature for MOSFETs. A lower limit in energy per operation can be reached with minimum V_DD ∼ S and minimum E ∼ CS², where C is the device capacitance, as illustrated schematically in Fig. 1.¹⁵

There are several ways of reducing the swing SS, given by

1

One can decrease of the transistor body factor m, using ultrathin body silicon-on-insulator (SOI), multigate or nanowire MOSFETs, carbon nanotube or 2D channels (leading to m ∼ 1), and negative capacitance field-effect transistors (FETs), or MEMS/NEMS structures (leading to m < 1). Alternatively, one can resort to low-temperature operation, which cannot be applied to traditional applications. Finally, one can modify the carrier injection mechanisms by turning to impact ionization or band-to-band tunneling (BTBT).

In the field of MOSFETs, several very interesting advances have been recently reported. Ultrathin semiconductor films and 3D-FETs can improve sub-20 nm CMOS node performance and substantially reduce supply voltage and short channel effects.

The best MOSFET devices leading to SS close to its minimum value are using fully depleted channels^16–19 (e.g., FD-SOI with very thin buried oxide¹⁹) or fully inverted ones with volume inversion²⁰ that is even more effective into optimizing electrostatic control²¹ of the structure (e.g., double-gate (DG), bulk, or SOI tri-gate/fin-FET, gate-all-around (GAA) MOSFET or nanowire FET).

The first fully depleted SOI MOSFETs have been fabricated on SOS materials¹⁶ but with Si films of poor quality. The first FD-SOI MOSFET with an ideal swing of about 60 mV/dec was demonstrated by numerical simulation in 1985 (see Fig. 2).¹⁷ The first experimental demonstration of an FD-SOI MOSFET with SS ∼ 60 mV/dec followed in 1986.¹⁸

Short channel effects (DIBL and charge sharing) in multigate MOSFETs are also reduced with decreasing the silicon film thickness t_Si (down to 5 nm) and doping, regardless of whether the architecture is single- or DG (see Fig. 3). Furthermore, a reduced sensitivity to t_Si and doping is observed for the DG devices, which is promising for the optimization of their electrical properties.²¹

DG devices with gate underlap have also shown to lead to a very good I_D, a reduction in the drain-induced barrier lowering (DIBL) and drain-to-gate leakage current, and a decrease in propagation delay and power.²²

Small diameter (3 nm) nanowire FETs have demonstrated experimentally very good I_ON/I_OFF performance,²³ with the best SS ∼ 75 mV/dec obtained by numerical simulation down to 5 nm gate length for both strained Si and InGaAs channel materials, as shown in Fig. 4.²⁴

In addition to III–V materials, there are other high-mobility materials that may replace Si in future VLSI applications. In this respect, heterogeneous 2D atomic crystals, especially transition-metal dichalcogenides (TMDs), have atomically smooth surface without dangling bounds or thickness fluctuations, as well as good mobility in chemical vapor deposition (CVD)-deposited films. They are thus very attractive enablers of ultimately scaled transistors and 3D ICs. The first CMOS-compatible TMD 3D transistor technology using novel hybrid Si/MoS₂ channel fin-FET and NW FET was demonstrated recently (see Fig. 5).

These 3D TMD transistors exhibit improved electron mobility compared to Si-based 3D FETs as well as higher drive current I_ON, as illustrated in Figs 6 and 7, respectively.²⁵ It has also been shown that MoS₂ FETs can meet high-performance (HP) requirement up to 6.6 nm node by employing bilayer MoS₂ as the channel material, while low-standby-power (LSTP) requirements present significant challenges for sub-10 nm nodes. On the other hand, the high mobility and the low effective mass of tungsten diselenide (WSe₂) may enable 2D FETs for both HP and LSTP applications down to the 5 nm node.

The subthreshold swing and DIBL were evaluated for both DG and SOI structures from monolayer (1L) to three-layer (3L) MoS₂, and compared to Si-based ultrathin-body (UTB) DG FETs. It was shown that MoS₂ FETs generally have better electrostatics than Si devices. Single-gate SOI topology can only sustain good electrostatics for 1L TMDs, while DG topology can present interesting performance for up to 3L TMDs, as shown in Fig. 8.²⁶

Carbon nanotube FETs, with a very good control of short channel effects and with the highest current drive to-date (>100 µA/µm at 400 nm channel length and 1 V drain bias) have been demonstrated while simultaneously achieving reasonable I_ON/I_OFF > 5000.²⁷

On the other hand, silicon fin-FETs with silicided source/drain, exploiting biased Schottky barriers, have been demonstrated. By combining a positive feedback induced by weak impact ionization with a dynamic modulation of the Schottky barriers, the device achieves a minimal subthreshold slope of 3 mV/dec and an average subthreshold slope of 6.0 mV/dec over 5 dec of current at room temperature. However, a drain bias of several volts is needed.²⁸

A comparative analysis of ring oscillators based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of speed gain and power consumption reduction for MOSFET architectures is achieved by switching from 7 nm Si baseline fin-FET process to 5 nm vertical Si NWs.²⁹

Another interesting possibility at the end of the roadmap could be to use semimetals for channel and source/drain. Indeed, for 1D devices, the band gap of semiconductors and semimetals increases with decreasing NW diameter. Therefore, a semimetal could become a semiconductor in the sub-10 nm range, as shown in Fig. 9. In this case, 1D structures could be used for the channel and thicker metallic source/drain regions could be made from the same material (e.g., Sn, Bi) without any extrinsic doping. Very good electrical properties have been shown by ab-initio simulations for 1 nm GAA Sn NWs with a 2.3 nm gate length, leading to a 72 mV/dec swing and I_ON ∼ 3 mA/µm at V_D = 250 mV.³⁰

3 Small slope switches

In the domain of small slope switches, the tunneling field-effect transistors (TFETs) seem very promising. However, so far, no one has demonstrated experimentally a TFET that has simultaneously both an I_ON comparable to a CMOS FET and a subthreshold swing of less than 60 mV/dec for several decades. The highest current for which a subthreshold swing of 60 mV/dec is observed is approximately 10 nA/µm. While the experimentally observed I_ON are in reasonable agreement with theoretical predictions, there is disparity in the subthreshold characteristics due to the fact that simulations usually neglect nonidealities and defects and that these advanced technologies using novel materials, technologies, and device architectures have to be optimized.³¹

The originally studied TFET configurations also suffered from low I_ON current levels usually in the order of few µA/µm caused by the misalignment of the tunneling direction and the gate-induced electric field. A new class of TFETs was introduced in which both BTBT direction and gate electric field are kept parallel, which allows I_ON to be proportional to the gate length. Among such transistors, the electron–hole bilayer tunneling field-effect transistor (EHBTFET) was proposed to exploit BTBT between a 2D electron gas and a 2D hole gas. Tunneling between 2D regions was demonstrated to be the most advisable scenario to optimize switching behavior. Semiclassical simulations for Ge EHBTFET showed impressive results that later on needed to be corrected for quantum mechanical effects and parasitic lateral tunneling and its undesired implications for the device performance.

It has been demonstrated that the inclusion of quantum confinement in Ge EHBTFET gives rise to the appearance of tunneling paths misaligned with the gate electric field that were not present in the semiclassical framework. This unwanted leakage between the overlap and underlap regions of the device reduced the steepness of the I–V curves and degraded SS. To overcome this problem, a heterogate EHBTFET may provide a potential solution to suppress the lateral tunneling in the subthreshold region while maintaining the high I_ON due to vertical BTBT in the overlap region.³²

Simulated DG TFETs with 2D layers using MoS₂–WTe₂ vertical tunneling, shown in Fig. 10, also showed very good subthreshold swing.³³

Finally, TFETs realized with III–V materials, for example, InAs, strained InAs, GaSb–InAs heterostructures, graded AlGaSb source H-TFET and quantum well (QW) InAs–GaSb source with InAs channel have been compared by quantum simulations. The best results were obtained for the QW-TFET, with graded source TFET coming second, and both significantly outperforming the reference MOSFET – see Fig. 11.³⁴

4 Conclusion

We are facing dramatic challenges dealing with future nanoscale devices, including performance, power consumption, new materials, device integration, interconnects, ultimate technological processes, and novel functionalities, needing disruptive approaches and inducing fundamental trade-offs for future ICs and nanosystems. This chapter reviewed recent advances and promising solutions for future ultralow power devices combining novel materials and innovative device architectures, including 2D layers, TMDs, heterostructures and quantum wells using strained Si, Ge, and III–V thin films, as well as multigate, nanowire, CNT transistors, and tunnel FETs.

Acknowledgments

The author would like to thank the Sinano Institute Members and Partners of Nanosil and Nanofunction FP7 European Networks of Excellence.

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