Prospects of Future Si Technologies in the Data-Driven World

Kinam Kim and Gitae Jeong

Semiconductor Business Division, Samsung Electronics Co. Ltd., Giheung, Gyeonggi-do, South Korea

1 Introduction

The evolution of human knowledge has been accelerated by storing and sharing information, which had been accomplished by using paper until twentieth century. In recent decades, magnetic tape and hard disk drives (HDDs) have taken over the role, as paper has been supplanted by semiconductor memory and storage.

Nowadays, it is expected that the amount of data will be doubling in every 2 years from 4.4 ZB in 2013 to 44 ZB in 2020.¹ The number of Internet-connected devices will increase from 0.5 billion in 2002 to 50 billion in 2020,² giving rise to the tremendous growth of Internet protocol (IP) traffic, which is expected to exceed 10²¹ bytes per year in 2016. The huge amount of information has a great impact on our daily lives, which can be filled with comfort, convenience, and safety by using and analyzing the so-called big data. That is, we live in data-driven world, where data-driven decision management,³ agriculture,⁴ health care,⁵ and even data-driven journalism⁶ are now a reality. It is noteworthy that we can store, share, and utilize the huge amount of data with the aid of silicon (Si) technology. This means that the novel Si technologies will be deployed to continuously enrich the data-driven world of the future.

In order to fully utilize big data, we need more accurate sensors, higher density memories, higher performance CPUs with low power consumption, and higher speed interconnection technologies. Higher density memories and faster CPUs with low power consumption will be enabled by the continuous scaling of Si technology, which is now heading to the 1X nm node. Higher speed interconnection can be achieved by parallel interconnection, such as through silicon vias (TSVs), and eventually by optical interconnection technologies. High-resolution complementary metal-oxide semiconductor image sensors (CISs) and advanced sensor technology like dynamic vision sensors (DVSs) employing global shutters will bring new valuable data to our data-driven world. Therefore, it is quite useful to review the bleeding-edge technologies and their future trends. In this chapter, we address the evolution of Si technology and predict its future directions.

2 Memory – DRAM

Dynamic random access memory (DRAM) has been successfully employed as a working memory for more than 40 years. The DRAM density has doubled every 18 months through technology innovations in the two key elements: the cell capacitor and the cell transistor.⁷ In order to guarantee successful operation, the sensing voltage ΔV_BL should be higher than the sensing noise after the refresh time as shown in the following equation, where C_S is the cell storage capacitance, C_BL is the bit line (BL) loading capacitance, I_L is the leakage current of the storage node, t_REF is the refresh time, and ΔV_MG is the minimum signal sensing margin:

1

Scaling technologies have been developed to maintain C_S/C_BL ratio, suppress I_L, and minimize the signal sensing noise.⁸ The capacitor's aspect ratio has been increased in every generation as shown in Fig. 1.⁹ Innovative patterning technology was developed to generate small and deep contact holes. In addition, equivalent oxide thickness (EOT) has been decreased by using the higher dielectric constant ZrO₂-based multilayered materials introduced at the 20 nm node. Further on, down at the 10 nm-class node, a novel stacking scheme will be required to conserve the integrity of the capacitor structure.

Cell transistor has evolved toward reducing the leakage current. The junction leakage current had been reduced by the recessed-channel cell transistor up to the 40 nm node. However, in the sub-40 nm regime, gate-induced-drain-leakage (GIDL) current due to the reduced overlap region between the gate and source/drain (S/D) becomes the major problem, which can be solved by the buried word line (WL) scheme. Down to the 10 nm node, a gate-all-around (GAA) structure may have to be implemented to solve the intercell disturbance.

In DRAM cell capacitor technology, in spite of the increasing aspect ratio and decreasing EOT, cell capacitance has decreased from 25 fF to around 10 fF at the 20 nm node, reducing the signal sensing margin. Therefore, additional innovation is required to maintain the sensing voltage of Eq. (1). A key technology for fully compensating the small storage capacitance at the 20 nm node is to lower the bit line loading capacitance. The ratio of the bit line and storage capacitance is the key parameter for successful DRAM operation, since ΔV_BL ∼ (1 + C_BL/C_S). It can be maintained at the same value as previous generations by introducing an air spacer around the bit line as shown in Fig. 2.

Fabricating the cell capacitor of 1X nm node DRAM is extremely challenging. The required aspect ratio will be near 80 and there is no space for dielectric material. Therefore, it will be necessary to achieve very high step coverage of the high-κ dielectric around the high aspect ratio stack and also develop thinner dielectric material with low enough leakage current. Greater than 95% step coverage will be required at the 10 nm node and the dielectric leakage current will need to be suppressed even at an EOT of 5 Å by workfunction engineering of the high-κ dielectric material.

At the device level, we expect that DRAM will be scaled down to 10 nm or less through the continuous innovations of cell storage capacitor and cell array transistor. Expected challenges at the 10 nm node are fabrication cost and manufacturability issues, such as overlay and uniformity. These issues will be resolved by novel integration schemes as well as improved process technology.

3 Memory – NAND

Over the last decade, physical dimensions of planar NAND flash memory have been successfully scaled down, so that even 1X nm technology node has been commercialized in recent years. NAND flash memory has played an important role in the data-driven world by providing higher bit density, lower cost, and smaller form factor indispensable in this mobile age.⁹

For NAND flash memory, the key scaling challenges involve overcoming the degradation of the V_T window, minimizing the interference coupling, and guaranteeing data retention for reliable device operation as shown in Fig. 3 ^{10, 11} while maintaining a wide process window for mass production. The V_T window for program and erase operation is decreased by short channel effects (SCEs), whereas the interference coupling increases since the electrostatic coupling becomes severe as the distance between adjacent cells is reduced. In addition, the number of stored electrons decreases rapidly as the device shrinks. Thus, only several tens of electrons are stored for 2X nm regime, which makes it difficult to satisfy the data retention requirements. At each node, those barriers have been overcome by significant technological breakthroughs in structures, materials, and intelligent operation algorithms implemented by circuits.

Up to the present technology node, the SCEs have been solved successfully by field-induced junction formation technology,¹² as well as continuous scaling of the tunnel oxide and oxide-nitride-oxide (ONO) layer thicknesses. The interference coupling has been suppressed by the timely adoption of the gate air-gap processes and innovative circuit technologies, including parallel programming, shadow programming, and extended error correction codes (ECCs).¹³ However, the reduction in the number of stored electrons and the increases in the interference coupling are great obstacles to scaling beyond the 1X nm node. Moreover, uncontrollably small process windows pose another major challenge. For those reasons, a paradigm shift from planar to 3D technology^{7, 14, 15} may become necessary for further progress.

In terms of the memory cell itself, 3D vertical NAND (V-NAND) has three main differences compared to the planar NAND: a vertical channel with a GAA structure, a thin film transistor (TFT) with a poly-Si channel, and a charge trapping storage layer instead of the poly-Si floating gate, as shown in Fig .3.¹⁶ The GAA structure helps to suppress SCEs, as does the thin poly-Si channel, which leads to stronger gate control. The interference coupling along the word line (WL) direction is greatly reduced by increasing the distance between the adjacent cells, while the interference coupling along the bit line (BL) direction is eliminated by using a GAA structure in which each BL is completely shielded by the gate metal layer. The minimum feature size of the cell has been increased by about a factor of 10, resulting in an increase of the number of stored electrons.

Consequently, 3D V-NAND with negligible interference coupling allows single-step rather than dual-step programming, resulting in faster programming speed and lower power consumption, which makes it more competitive compared with planar NAND.^{17, 18} In addition to the faster programming, 3D V-NAND with enhanced V_T window can push the limit of multilevel cell technology to 4 bits as shown in Fig. 4.

As illustrated in Fig. 4, the stacking of 3D cells in the vertical direction is another key advantage to overcome the small process windows beyond the 1X nm node. Since the physical design rule of the planar NAND should be decreased to achieve a higher bit density, the patterning process is getting more complex and difficult. The current double patterning technology (DPT) has reached its limits and thus the more complex and expensive quadruple patterning technology (QPT) has become an essential process. On the other hand, 3D V-NAND relieves the photolithographic limit since the number of stacked layers determines the bit density.

Despite the advantages of 3D V-NAND over the conventional planar NAND, there was considerable doubt in the memory industry regarding mass production of 3D V-NAND because of several challenges, such as the fabrication of high-aspect ratio channel holes, the control of mechanical stress in thick cell stacks, the uniformity of dielectric layer deposition in deep contact holes, and so on. However, with advances in dry etching technology and materials have allowed 3D V-NAND to be commercialized, as shown in Fig. 5.¹⁹ The 3D V-NAND with 32 stacked layers gives twice the density of a 16 nm planar NAND and, by increasing the number of stacked layers, it is expected that NAND flash memory scaling with 3D V-NAND technology will continue beyond 10 nm into the 1 Tb era.

4 Logic technology

Logic complementary metal-oxide semiconductor (CMOS) technology has successfully evolved over many decades, satisfying the market demand for high performance, low power, and low cost-per-function. This has been achieved through the “silicon shrinking technology” – the innovation of processes, materials, and device structures.⁸ In a data-driven world, more emphasis will be placed on the power-constrained performance because only a limited amount of power can be available per chip. Total power dissipated by a CMOS circuit consists of two components, dynamic power P_DYN and static power P_STAT, as illustrated in the equation:

2

where C, f, and α are total capacitance, operating frequency, and activity factor, respectively. Thus, for high performance with low power consumption, it is indispensable to scale the supply voltage V_DD without sacrificing the current drive I_ON or increasing the leakage current I_L.

The most critical challenges in conventional CMOS shrinkage down to 20 nm were the control of SCEs and the enhancement of carrier mobility. The SCEs have been suppressed by a thin gate oxide and shallow S/D junction depth. Both shorter gate length L_G and thinner gate oxide have continuously provided an increase in I_ON and a decrease in the total capacitance, thus faster switching speed despite a lower V_DD. At the same time, more CMOS transistors can be integrated onto a single chip for more functionality. However, the exponential increase in the gate leakage current puts a physical limitation on shrinking the SiO₂ gate oxide thickness to ∼1.2 nm.²⁰ This limit has been overcome through the high-κ gate dielectric and metal gate (HKMG) process, shrinking the EOT below 1.0 nm without aggravating the gate leakage current.²¹ On the other hand, carrier mobility can be enhanced by applying an appropriate mechanical stress to a silicon channel. Embedding SiGe into S/D region of PMOS and high stress SiN capping film over NMOS can provide much higher hole and electron mobilities at lowV_DD.²²

From the 14 nm node onward, it is extremely challenging to reduce V_T and its variability without sacrificing low subthreshold leakage current, which is key for low power consumption. Innovative device structures, such as 3D FinFETs or trigate devices, have successfully suppressed SCEs, and improved drain induced barrier lowering (DIBL) and subthreshold swing (SS) with much better control of channel potential. This made it possible to reduce V_DD and save over 30% of the dynamic power consumption, see Fig. 6.²³ Furthermore, a lightly doped channel provides the improved immunity to V_T variability thanks to suppressed random dopant fluctuation (RDF). However, there are some challenges to overcome before mass-production: low-cost patterning process, complexity in design optimization due to a quantized number of fins, and V_T tuning using gate workfunctions.²⁴ Cost-effective multiple patterning technology (MPT) may be an interim solution before extreme ultraviolet (EUV) lithography becomes cost-competitive.

For the 7 nm technology node and beyond, novel materials and device structures will be needed to meet market needs for low power consumption, low cost-per-function, small form-factor, and advanced functions, such as energy harvesting and communication – see Fig. 7. GAA or 1D nanowire (NW) transistors can provide a nearly ideal (60 mV/dec) electrostatic control over the channel potential.^{25, 26} These device structures may be combined with alternative channel materials to enhance carrier mobility. Thus far, InGaAs and Ge are promising candidate materials for NMOS and PMOS, respectively.²⁷ However, there are many challenges to overcome, the main ones being the precise control of nanowire thickness and its interface for high performance and reliability, and the cost-effective integration of III-V channel materials onto a single silicon substrate. Also, tunneling field-effect transistors (TFETs) shows a great potential to provide an extremely low supply voltage operation with a steeper subthreshold swing of <60 mV/dec. However, its small on-current drive capability should be overcome; one of the promising approaches is the combination of perpendicular and parallel electric fields at the tunneling junction.^{30, 31}

Logic CMOS technology is entering the sub-10 nm regime, emphasizing the low power consumption with high performance. Further downscaling will continue through the combination of innovative processes, materials, and device structures.

5 CMOS image sensors

Recently, CISs have gained widespread adoption by replacing charge-coupled device (CCDs). As the mobile market is rapidly expanding, it is very important to scale down the CIS pixel size for satisfying the needs of high resolution and small form factor. In the CIS development trend, the pixel size has been continuously shrunk toward 1.0 µm. The key technological challenge to going down to submicron pixels is to maintain a high signal-to-noise ratio (SNR) in the reduced pixel size.^{32, 33} The SNR is mainly determined by pixel sensitivity and crosstalk between the pixels, which both degrade as the pixel size decreases. Therefore, technology innovation is focused on maintaining a large SNR with high pixel sensitivity and low crosstalk.

The sensitivity is decreased as the pixel size scales down because the number of photons is reduced. In order to maintain high sensitivity, the pixel illumination technology has migrated from front-side illumination (FSI) to back-side illumination (BSI).³⁴ Since there is no optical obstacle for incident light from microlens to photodiode in the BSI technology, as shown in Fig. 8(a), the sensitivity is maximized. Furthermore, BSI sensors can be manufactured using a bonding technology that allows for 3D integration. For example, stacked image sensors can be manufactured by bonding separately processed pixel and circuit wafers. Using this stacked sensor, chip size can be effectively shrunk and special processes can be used on the pixel wafer, thus enhancing the chip performance.

The undesired crosstalk becomes more severe as the pixel size shrinks due to the diffraction of incident light. The nondiagonal elements of color conversion matrix (CCM) become larger as the crosstalk increases, worsening the SNR of final image, as illustrated in Fig. 9. Therefore, it is very important to minimize the crosstalk between the pixels to enhance SNR at both low and high illumination. In order to reduce the crosstalk, physically complete isolation between neighboring pixels can be introduced, for example, via deep trench isolation (DTI). Recently, a combination of DTI structure with a vertical transfer gate, known as the ISOCELL process, was introduced for better color and image quality, see Fig. 8(b). The ISOCELL technology will allow us to overcome the 1 µm pixel barrier of the CIS technology for further pixel downscaling.

Novel pixel technologies can add new value to CISs. Among them, one of most beneficial techniques is the global shutter sensor, whose main function is to eliminate the so-called “jello” effect of blurring in images of fast-moving objects or when a camera vibrates as shown in Fig. 10. This distorted image occurs because of time lag in sequential gathering of the information from the pixels. With the in-pixel global shutter, light is captured by all pixels simultaneously, eradicating the time lag and the jello effect. This is achieved by temporarily storing photoelectrons in each photodiode by adding a storage element to each pixel.

Another useful innovation is the DVS, which mimics the human photoreceptor cells that respond only changes in the scene. Since DVS has an event-based asynchronous operation rather than the traditional synchronized and frame-based one, we can detect relatively faster movements. This technology will be useful for mobile, surveillance, and obstacle detection for drones.

6 Packaging technology

As recent IT paradigm shifts from PC to mobile applications, integration of devices becomes more important in electronic systems. In the previous PC era, semiconductor chips were massively produced in a certain standardized form. Primary requirements for semiconductor packaging were the simple and discrete forms and low cost.³⁵ This trend has been completely changed by the advent of smartphones, in which portability and small form factor are very critical characteristics for packaging. Therefore, 3D packaging based on die and package stacking has become a key technology.³⁶ There are two major components in 3D packaging: TSV-based die stacking and package stacking.

Originally, TSV technology was adopted in server-specific DDR4 DRAM memory units. Cloud servers require high-speed, high-capacity, and low-power DRAM memory. It is difficult to satisfy these requirements with conventional wire bonding because of the restricted I/O density and long interconnect lines. Compared to conventional package stacks, TSVs increase the I/O density by a factor of 17 and shorten interconnect length by a factor of 40. Consequently, TSVs can have high performance and high capacity with low power consumption and small form factor.³⁷ One of the possible concerns in TSVs is excessive loading, but it is not an issue because only the master chip is required to communicate with the controller regardless of the number of stacks, as shown in Fig. 11. Evaluation of an RDIMM unit with TSV technology showed a 24% reduction in power consumption compared to a wire-bonded LRDIMM unit as shown in Fig. 12.⁹

The other emerging memory technology using TSVs is a high bandwidth memory (HBM), which aims at high bandwidth DRAM applications such as high-performance computing, networks, and graphics. It is possible to have high bandwidth in HBM through wide I/O interconnects, which can be achieved by fine pitch TSVs. TSVs allow up to 1024 I/O's per chip, while the number of I/O's per chip is limited to 32 in conventional wire bonding technology. As a result, bandwidth of over 1 Tb/s can be achieved with relatively low I/O speed as shown in Fig. 13.³⁸

Package stacking, also known as package-on-package (PoP), can be used to achieve higher system-level integration. Previously, devices were packaged individually and mounted onto a board. However, Internet of things (IoT) and wearable devices are encouraging the convergence of IT technologies, requiring the integration of various devices and passive elements onto a single small package platform.³⁹ Early PoP versions involved integrated application processors (APs) and mobile DRAM stacks. Embedded package-on-packages (ePoPs) were an extension of this, where the surrounding embedded memory and passive elements were included into the integrated system in response to demand for smaller form factors, as shown in Fig. 14. The DRAM, NAND, buffer chip, and passive elements were stacked onto the largest component of the AP. This resulted in an overall package footprint reduction of over 60%.

In the near future, we will need to integrate numerous semiconductor devices in a single package – such as AP, memory, CIS, MEMS, and so on. This system integration in a package is expected to provide a huge size reduction and great performance enhancement for future IoT and wearable devices. The major challenges will be focused on improving thermal performance, increasing I/O density, and designing for power noise reduction. There are current research efforts in all of these areas.

7 Silicon photonics technology

Data center traffic has been and will be continuously increasing as people use more connected devices. There are forecasts of Internet-connected devices increasing from 4.9 billion in 2014 to 25 billion in 2020. The global data center Internet protocol (IP) traffic forecasts estimate a threefold increase from 2013 to 2018.⁴⁰ In order to meet the bandwidth demand, data centers will expand the deployment of optical interconnects. Infonetics Research expects that 100G optical modules will make up 50% of data center transmission capacity by 2019.⁴¹

Research on Si photonics is ongoing to reduce the cost of optical interconnects and accelerate the replacement of copper wire. Silicon photonics will allow optical devices to be fabricated at low cost using standard semiconductor technologies and integrated with microelectronic devices.^{42, 43} Figure 15 summarizes the recent research activities on Si photonics at Samsung.⁴⁴ Photonic devices are fabricated using locally crystallized silicon on a bulk Si substrate that allows lower material cost and process compatibility with CMOS transistors. Lasers for light sources are formed with III/V gain layers that are wafer-bonded to Si-photonic die, shown in Fig. 15(b). Bonded lasers are expected to provide light sources at lower cost compared to external laser diode modules. Integrated microlenses on the top surface enable passive alignment and correspondingly cheaper package cost, shown in Fig. 15(c). Figure 15(d) presents major device building blocks made on a bulk Si platform, including modulators, photodetectors, waveguides, and vertical grating couplers.

It is expected that optical interconnection technology using Si photonic devices will be widely used in data-driven world. High bandwidth capability of optical interconnection technology will be essential in data centers, high-bandwidth consumer electronics, and so on.

8 Concluding remarks

In this chapter, the evolution and prospects for the future Si technologies have been reviewed. The Si-based memory and logic technologies have been successfully scaled down to 1X nm node. From the device point of view, all of these Si devices face no fundamental physical limitations down to sub-10 nm nodes. Practically, fabrication cost and manufacturability are of increasing concern. Patterning difficulties, as well as tight overlay and uniformity tolerances, will increase fabrication costs. However, these difficulties will be eventually overcome by innovative integration schemes, new materials, and so on.

Along with the individual technology evolution, the convergence of various technologies will generate new areas of functional diversification. Packaging technologies, including TSV, will not only improve the performance but also merge various functions of many different devices. Integrated CISs will collect more useful data that will be processed, analyzed, and stored by advanced Si technologies. Huge amounts of data will be transferred between the devices, generating heavy IP traffic – an issue that can be resolved by novel interconnection technology such as optical interconnects. It is expected that all of these advanced Si technologies will open the era of a truly data-driven world.

Acknowledgments

We would like to thank Duckhyung Lee, Jungchak Ahn, Sayoon Kang, Tae-Je Cho, Sujin Ahn, Kyungho Ha, and Daewon Ha for the helpful technical discussions.

References

1. 1. IDC, “The digital universe of opportunities: rich data and the increasing value of the Internet of things,” 2014.
2. 2. D. Evans, The Internet of Things: How the Next Evolution of the Internet is Changing Everything, Cisco Systems, 2011.
3. 3. A. McAfee and E. Brynjolfsson, “What makes company good at IT?,” Wall St. J. (2011).
4. 4. M. Guild and T. Danaher, “Big data comes to the farm,” Financial Sense (2014), www.financialsense.com/contributors/guild/big-data-farm.
5. 5. Editorial, “Data driven healthcare,” MIT Technol. Rev. (2014).
6. 6. M. Lorenz, “Data driven journalism: What is there to learn?” Presented at Innovation Journalism Conf., Stanford (2010), www.technologyreview.com/business-report/data-driven-health-care.
7. 7. K. Kim, U.-I. Chung, Y. Park, et al., “Extending the DRAM and flash memory technologies to 10 nm and beyond,” Proc. SPIE 8326, 832605 (2012).
8. 8. K. Kim, “From the future Si technology perspective: Challenges and opportunities,” Tech. Dig. IEDM (2010), pp. 1–9.
9. 9. K. Kim, “Silicon technologies and solutions for the data-driven world,” Proc. ISSCC (2015), pp. 1–7.
10. 10. Y. Park and J. Lee, “Device considerations of planar NAND flash memory for extending towards sub-20 nm regime,” Proc. Intern. Memory Workshop (2013) pp. 1–4.
11. 11. Y. Park, J. Lee, S. S. Cho, G. Jin, and E. Jung, “Scaling and reliability of NAND flash devices,” Proc. Intern. Reliability Phys. Symp. (2014), no. 6860599.
12. 12. J. Seo, K. Han, T. Youn, et al., “Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies,” Tech. Dig. IEDM (2013), no. 6724554.
13. 13. K.-T. Park, M. Kang, D. Kim, et al., “A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories,” IEEE J. Solid State Circ. 43, 919–927 (2008).
14. 14. H. Tanaka, M. Kido, K. Yahashi, et al., “Bit cost scalable technology with punch and plug process for ultra high density flash memory,” Proc. VLSI Symp. (2007), pp. 14–15.
15. 15. J. Jang, H.-S. Kim, W. Cho, et al., “Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory,” Proc. VLSI Symp. (2009), pp. 192–193.
16. 16. J. Choi and K. S. Seol, “3D approaches for non-volatile memory,” Proc. VLSI Symp. (2011), pp. 178–179.
17. 17. K.-T. Park, J.-M. Han, D. Kim, et al., “Three-dimensional 128 Gb MLC vertical NAND flash-memory with 24-WL stacked layers and 50 MB/s high-speed programming,” Tech. Dig. ISSCC (2014), pp. 334–335.
18. 18. J.-W. Im, W.-P. Jeong, D.-H. Kim, et al., “A 128 Gb 3b/cell V-NAND flash memory with 1 Gb/s I/O rate,” Proc. ISSCC (2015), article 7.2.
19. 19. J. Elliott and E. S. Jung, “Ushering in the 3D memory era with V-NAND,” Presented at Flash Memory Summit (2013).
20. 20. T. Skotnicki, C. Fenouillet-Beranger, C. Gallon, et al., “Innovative materials, devices, and CMOS technologies for low-power mobile multimedia,” IEEE Trans. Electron Devices 55, 96 (2008).
21. 21. K. Mistry, C. Allen, C. Auth, et al., “A 45 nm logic technology with high-κ+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging,” Tech. Dig. IEDM (2007), pp. 247–250.
22. 22. T. Ghani, M. Armstrong, C. Auth, et al., “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” Tech. Dig. IEDM (2003), pp. 978–980.
23. 23. C. Auth, C. Allen, A. Blattner, et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” Proc. VLSI Symp. (2012), pp. 131–132.
24. 24. H. Kawasaki, V. S. Basker, T. Yamashita, et al., “Challenges and solutions of finFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond,” Tech. Dig. IEDM (2009), no. 5424366.
25. 25. J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator ‘gate-all-around device’,” Tech. Dig. IEDM (1990), pp. 595–598.
26. 26. S. D. Suk, S.-Y. Lee, S.-M. Kim, et al., “High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” Tech. Dig. IEDM (2005), pp. 717–720.
27. 27. M. Radosavljevic, B. Chu-Kung, S. Corcoran, et al., “Advanced high-κ gate dielectric for high-performance short-channel In_0.7Ga_0.3As quantum well field effect transistors on silicon substrate for low power logic applications,” Tech. Dig. IEDM (2009), no. 5424361.
28. 28. O. Weber, Y. Bogumilowicz, T. Ernst, et al., “Strained Si and Ge MOSFETs with high-κ/metal gate stack for high mobility dual channel CMOS,” Tech. Dig. IEDM (2005), pp. 137–140.
29. 29. K. Ikeda, M. Ono, D. Kosemura, et al., “High-mobility and low-parasitic resistance characteristics in strained Ge nanowire pMOSFETs with metal source/drain structure formed by doping-free processes,” Proc. VLSI Symp. (2012), pp. 165–166.
30. 30. Y. Morita, T. Mori, S. Migita, et al., “Synthetic electric field tunnel FETs: Drain current multiplication demonstrated by wrapped gate electrode around ultrathin epitaxial channel,” Proc. VLSI Symp. (2013), pp. 236–237.
31. 31. K. E. Moselund, H. Schmid, C. Bessire, M. T. Bjork, H. Ghoneim, and H. Riel, “InAs–Si nanowire heterojunction tunnel FETs,”. IEEE Electron Device Lett. 33, 1453 (2012).
32. 32. J. C. Ahn, C.-R. Moon, B. Lee, et al., “Advanced image sensor technology for pixel scaling down toward 1.0 µm,” Tech. Dig. IEDM (2008), no. 4796671.
33. 33. H. Wakabayashi, K. Yamaguchi, M. Okano, et al., “A 1/2.3-inch 10.3 Mpixel 50 frame/s back-illuminated CMOS image sensor,” Tech. Dig. ISSCC (2010), pp. 410–411.
34. 34. K. Lee, J. C. Ahn, B. Kim, et al. “SNR performance comparison of 1.4 µm pixel: FSI, light-guide, and BSI,” Intern. Image Sensor Workshop (2011), pp. 9–11.
35. 35. R. R. Tummala, “Packaging: Past, present, and future,” Proc. 6th Intern. Conf. Electronic Packaging Technol. (2005).
36. 36. R. R. Tummala, System on Package: Miniaturization of the Entire System, New York: McGraw Hill, 2008.
37. 37. J. Burns, “TSV-based 3D integration,” chapter in: A. Papanikolaou, D. Soudris, R. Radojcic, eds., Three-Dimensional System Integration, New York: Springer, 2011, pp. 13–32.
38. 38. H. Goto, “Memory evolution for next generation GPU,” PC Watch (2015).
39. 39. G. A. Riley, “How 3D is stacking-up,” Adv. Packag. 17, 16–18 (2008).
40. 40. Cisco Systems, “Cisco global cloud index: Forecast and methodology, 2013–2018,” 2014.
41. 41. Infonetics Research, “10G/40G/100G data center optics biannual market size and forecast,” April 2015.
42. 42. Editorial, “Simply silicon,” Nature Photonics 4, 491 (2010).
43. 43. M. Streshinsky, R. Ding, Y. Liu, et al., “The road to affordable, large-scale silicon photonics,” Opt. Photonics News 24, 32–39 (2013).
44. 44. H. Byun, J. Bok, K. Cho, et al., “Bulk-Si photonics technology for DRAM interface,” Photonics Res. 2, A25–A33 (2014).