Graphene and Atom-Thick 2D Materials: Device Application Prospects

Sungwoo Hwang, Jinseong Heo, Min-Hyun Lee, Kyung-Eun Byun, Yeonchoo Cho and Seongjun Park

Device Laboratory, Samsung Advanced Institute of Technology, Suwon, 443-803, South Korea

1 Introduction

The electronic properties of low-dimensional systems have long been an interesting topic in both physics and engineering societies. Silicon MOSFET and III–V HEMT devices, for example, not only have been the most essential elements in micro- and nanoelectronics since their early days but have also provided wonderful playgrounds for correlated 2D electron systems, leading to such fundamental discoveries as the integer and fractional quantum Hall effects. These traditional 2D electron systems have now reappeared in the form of atomic sheets, shedding light on entirely new physics originating from the orbital confinement, as well as new materials science aspects. The new physics, in turn, enables innovation in the 2D device realm. In this chapter, we consider these new opportunities and accompanying challenges, examining various aspects of potential device applications of graphene and atom-thick 2D materials, including optoelectronic devices, new types of transistors, and possible CMOS integration. Direct growth is the key technology to make all these applications realistic, so we will also address the prospects of wafer-scale graphene and 2D materials growth.

2 Conventional low-dimensional systems

Back in 1967,¹ Stern and Howard considered the two-dimensional electron gas (2DEG) at the Si/SiO₂ interface, where the electron wavefunction is confined within a few nanometers in the direction perpendicular to the interface. High-mobility 2DEG was then created in III–V HEMTs by Stormer et al. in 1979.² Physicists utilized these 2DEGs as a wonderful playground for new types of electronic states. The integer quantum Hall effect,³ a manifestation of magnetic field-induced localization–delocalization transition, was observed at the Si/SiO₂ interface. Subsequently, the fractional quantum Hall effect⁴ arising in strongly correlated 2D electron liquids was found in high-mobility HEMTs. These observations were only made possible by superb quality of the devices. In 1981, when integer quantum Hall effect was first observed, Intel was already manufacturing processors with more than 100,000 transistors. Advances in large-scale CMOS circuits have been driving modern information technology to this date.

If the electronic wavefunction of a 2DEG is further confined, one can realize a one-dimensional electron gas (1DEG). In 1988, van Wees et al.⁵ fabricated 1DEGs by placing split gates on a III–V HEMT and defining a narrow electron channel by negatively biasing these gates. The mobility of the HEMT wafer was 10⁶ cm²/V·s, resulting in the mean free path of several microns at 4 K making it possible to observe conductance quantization whenever the gate voltage opened a new conductance channel. Scott-Thomas et al.⁶ fabricated silicon 1DEGs by the double-gate technique and observed Coulomb blockade oscillations. These early 1DEGs studied for fundamental physics have now reappeared in such devices as fin-FETs⁷ and gate all-around (GAA) Si nanowire FETs,⁸ illustrated in Figs. 1 and 2, respectively, as examples of ultimate highly scaled Si MOSFETs.

Figure 2 also shows the conductance measured as a function of gate bias V_G in GAA Si nanowire FETs with length ranging from 400 to 20 nm. It shows conductance overshoot when the channel length is shorter than 40 nm. This length scale is comparable to the mean free path of electrons in Si at room temperature, providing strong evidence of ballistic transport. One well-known but important message is that the device performance will not be improved much in these nodes even though we scale the channel length.

3 New atomically thin material systems

Newly discovered atom-thick 2D systems, including graphene, can be thought of as a traditional 2DEG shrunk to atomic thickness. The extreme orbital confinement manifests itself in new physics originating from material aspects and dimensional confinement on the atomic scale. The new physics is giving us many new opportunities for creating new device functionalities and innovating conventional 2D devices.

Graphene, one isolated sheet of graphite or a honeycomb 2D lattice of carbon atoms, was discovered by Geim and Novoselov in 2004.⁹ In layered graphite, each carbon atom has sp² hybridization, leading to strong intralayer covalent bonding and relatively weak van der Waals interlayer interaction, with an interlayer distance of 0.34 nm. Such weak bonding between layers leads to simple mechanical exfoliation using adhesive tape, resulting in atomically thin monolayers of carbon atoms (see Fig. 3(a) and (b)). Having linear energy–momentum dispersion relation, shown in Fig. 3(c), low energy excitations of carriers in graphene mimic relativistic Dirac particles with a reduced velocity of c/300, called massless Dirac fermions.¹⁰ A simple consequence of this unique dispersion is the absence of backscattering, leading to mobility up to 200,000 cm²/V·s at room temperature. More excitingly, many novel physical effects have been explored experimentally: half-integer quantum Hall effect,⁹ Coulomb drag (frictional coupling between electric currents flowing in spatially separated conducting layers due to interlayer electron–electron interactions),¹¹ and Hofstadter's butterfly effect,¹² when 2D electrons in both a magnetic field and a periodic electrostatic potential exhibit a self-similar recursive energy spectrum.

In addition to new fundamental physics, graphene has a number of superior technological properties in terms of transparency, bulk resistivity, current density, chemical inertness, surface area, and thermal conductivity. Graphene has high transparency of 97.7% over a wide spectral range, bulk resistivity of 10 µΩ cm, and can carry current densities of 10⁶ A/cm², compared to 1.68 µΩ cm and 4020 A/cm² for Cu of monolayer thickness, respectively. It also has chemical inertness from aromatic bonds of 518 bond enthalpies kJ/mol compared to 348 for C—C bond; a high surface area of 2630 m²/g compared to 500 for activated carbon; and thermal conductivity of 5300 W/m·K, compared to 2320 for diamond. These properties can be combined and exploited in transparent electrodes, interconnects, barrier materials, supercapacitor, and heat sink applications – see Fig. 4. For example, transparent electrodes require both high transparency and low sheet resistance. Doped four-layer graphene has 30 Ω/ sheet resistance at 90% transparency, superior to commercial indium tin oxides.¹³ Moreover, for flexible applications, graphene-based transparent electrode can withstand strains of more than 6%, whereas ITO cracks under 2–3% strain. As another example, heat management in modern integrated chips or CPUs is becoming increasingly important because of ever-larger heat dissipation as device density increases. Given a thermal conductivity of around 40 times larger than Si, graphene is expected to provide viable solutions for heat management in modern integrated chips when incorporated in the form of composites or inks.

Since its discovery in 2004, graphene has been at the center of new materials research both in academia and industry for disruptive innovation. However, for applications such as flexible digital electronics, new functional nanomaterials beyond graphene are required, with such properties as an electronic bandgap or atomically clean dielectric interfaces. The search for other layered materials that can be easily exfoliated has produced a large number of 2D materials besides graphene. These include monoatomic phosphorene and diatomic materials such as hexagonal boron nitride (h-BN) and transition metal dichalcogenides (TMDCs)¹⁴ – see Table 1. While graphene is a semimetal, some TMDCs are semiconducting, whereas h-BN is a dielectric with an ultraclean surface. The most studied semiconducting TMDCs are MoS₂ (see Fig. 5 for bandstructure), MoSe₂, WS₂, and WSe₂. From the optoelectronic application viewpoint, these 2D materials span the range from zero bandgap graphene to a large bandgap semiconductor such as GaS (∼3 eV), to the insulator h-BN. In addition to aforementioned basic components, there is also a new class of materials such as 2D superconductors, for example, NbS₂ and NbSe₂. With a whole library of 2D materials and their heterostructures, one can envisage a new atomic system with a broad range of functionalities.¹⁵

4 Device application of new material systems

• Photodetectors

Two-dimensional materials provide strong light-matter interaction, such that even a single monolayer can have up to 10% absorption, depending on wavelength and material bandgap.¹⁶ With large absorption coefficients of 10⁵–10⁶ cm⁻¹ of 2D materials in the visible range, almost two orders of magnitude larger than Si, photodetectors based on 2D materials can be made as thin as a few tens of nanometers. One of the photodetector figures of merit is responsivity or external quantum efficiency, which measures the number of electrons generated per incident photon.¹⁷ Focusing on vertically stacked photodetectors with a transparent electrode/photoactive region/electrode sequence, a responsivity of 20 A/W was measured in graphene/MoS₂/graphene heterostructures (see Table 2).

Another figure of merit of photodetectors is response time or bandwidth, a critical measure for optical communication. Graphene has the highest mobility and ultrabroadband photoresponse but only absorbs 2.3% of light.²² The weak absorption of graphene can be overcome by integrating it with a Si waveguide in order to enhance the detection area along the propagation direction^23–25 (see Fig. 6).

Graphene/Si hybrid photodetectors showed a 3 dB bandwidth of 20 GHz at 1550 nm wavelength. Monolayer deposition of graphene on a Si waveguide offers simpler and cheaper integration than heteroepitaxial growth of III–V or Ge layers on Si for upcoming all-optical chips.

• New types of transistors

Graphene FETs showed unprecedented mobility of over 100,000 cm²/V·s at room temperature,²⁶ two orders of magnitude larger than Si CMOS. As a result, graphene was considered a candidate for future electronics in post-Si era. But graphene lacks a bandgap of at least a few hundred millielectron volts, making it difficult to switch off the FET current. A number of graphene-based alternatives have been proposed – graphene nanoribbons,²⁷ bilayer graphene with tunable bandgap,²⁸ and graphene nanomeshes,²⁹ – but all have suffered from either lithographically patterned irregular edges, the absence of uniformity and controllability over large area, or small on/off current ratios.

The challenges of using standalone graphene for digital applications shifted the focus to graphene hybrid systems. In order to attain an appropriate energy barrier to turn off charge flow, semiconducting materials were brought in contact with graphene. For example, graphene–Si hybrid junctions make Schottky diodes where the barrier height of the junction can be tuned by gate voltage as the workfunction of graphene is modulated (see Fig. 7).³⁰ This solid-state triode system, called graphene barristor, enabled high on/off ratio of 10⁵ and a half-adder circuit was demonstrated upon its integration.

The work on graphene barristors also demonstrated a new finding: the absence of pinning in graphene on Si. This unique property can be applied to reduce source–drain contact resistance, which is discussed in Section 5.2. Graphene/2D semiconductor heterotunnel junctions were also demonstrated to show large on/off ratio³¹ and atomically thin semiconductors, such as WS₂, sandwiched between graphene layers, led to transparent and flexible tunneling transistors.³² Recent results in this area are summarized in Table 3. Graphene–semiconductor–metal tunnel junctions on 8-in. wafer scale provide a versatile platform to be tailored by varying materials and deposition thicknesses for low-power electronics, as in Fig. 8.³⁵

• Challenges

It should be noted that many conceptually new device concepts that appeared in the ITRS, including carbon nanotubes, single electron transistors, and spin MOSFETs, have not to date succeeded in displacing Si technology. In that regard, the new graphene- and/or other atom-thick 2D material-based optoelectronic or electronics devices discussed above could require many years before showing up in the market.³⁶ Even though they show higher photoresponsivity and optical communication speeds, as well as on/off ratios comparable to conventional devices, there are still many challenges to overcome.

As far as heterojunctions are concerned, there is the perennial question of interfaces. First of all, large-scale graphene grown on germanium³⁷ or catalytic metal surfaces³⁸ has to be transferred to the target substrate, including exposed Si or other 2D materials. The transfer process usually involves adhesives, polymers, or chemical etchants,³⁹ which in turn introduce organic, ionic, or metal residues. Spatial variation of these residues degrades device uniformity and controllability. Second, there is the 2D semiconductor and metal contact issue. With lack of precise doping control for both p- and n-type 2D semiconductors, true Ohmic contact is difficult to achieve. So far, only limited chemical doping has shown some reduction of contact resistance,⁴⁰ but the results are still inferior to state-of-the-art Si technology. Third, there is no thorough study on scaling of two-dimensional devices including both channel and contact area. Even though the best I_ON of 10 µA/µm² at 0.5 V for 2D heterojunction tunnel devices is comparable to state-of-the-art Si contact resistivity, all aforementioned issues result in nonuniform distribution and degradation of on-current for electronic devices.

5 Components in Si technology

So far, we discussed devices based on active functions of graphene or related 2D materials for optoelectronic or electronic applications that might be adopted in 5–10 years. More realistic application of those materials is implementation as a component layered material in Si device process, enhancing device performance.

The first MOSFET, patented in 1960 by D. Kang⁴¹ and shown in Fig. 9, was a flat device using only Si, SiO₂, and Al as constituent materials. Continued performance improvement and dimensional scaling of MOSFETs during last half century have been made possible only by continuously adopting new type of structures, materials, and processing technologies. Compared to Fig. 9, a modern CMOS device architecture, shown in several chapters of this book, is replete with tremendous complications and adaptations. The Al interconnect was replaced by Cu for the lower parasitic resistance in the late 1990s, in spite of the high diffusivity of Cu into active device regions and the deep defect level of Cu in Si. Also, the damascene process was adopted to solve the difficulty in etching Cu.⁴² Then, SiO₂/poly-Si gate was replaced by high-κ/metal gate stack for scaling the equivalent oxide thickness (EOT) from the 45 nm technology node onward, regardless of the difficulties in threshold voltage (V_T) alignment and complex new process steps, such as atomic layer deposition (ALD).⁴³ Two-dimensional atom-thick materials hold potential promise as passive components in following two possible scenarios in sub-10 nm technology node.

• Interconnects

The exponential increase in the number of interconnects and their increasing resistance with device downscaling have always comprised a major limiting factor for fabricating more complex electronic device. Until the recent sub-20 nm nodes, additional Cu metal layers and the damascene process provided reasonable resistance and manufacturability in the back-end-of-line (BEOL) process flow. However, shrunken Cu interconnects have to carry higher current densities, resulting in migration, deformation, or diffusion to other regions because of increased heat dissipation. Moreover, electron scattering at the surfaces and grain boundaries, as well as line edge roughness (LER), start to play an increasing role in the conduction properties of metal, and the effective resistivity of Cu more than doubles as the line width decreases from 100 to 10 nm.⁴⁴ Furthermore, the thickness of the liner/barrier layer has remained almost constant and the portion of liner/barrier layer in interconnect has increased from 1% to 50%.⁴⁵

There are few possible ways to overcome these issues: improvement of the effective resistivity of Cu by increasing grain size and decreasing LER, hybridization or replacement of interconnect material with lower resistivity materials, and introduction of an atomically thin liner/barrier layer. Chemical vapor deposition of graphene on catalytic metals³⁸ is a well-known method for large-scale and high-quality graphene film production. Among other metals, Cu offers the best quality of monolayer graphene because of near-zero solubility and self-terminated growth mechanism.⁴⁶ As a result, Cu–graphene hybrid interconnect appears a promising alternative to Cu alone, and graphene-covered Cu brings a lot of benefits. Since graphene is both a good electrical and thermal conductor, and a good barrier material, graphene–Cu interconnects can prevent electromigration and provide increased current-carrying capacity – see Fig. 10. These concepts were patented⁴⁷ by IBM, Toshiba, and others and published in a few of papers.^{48 49} For example, Yeh et al. reported the current-carrying capacity of 22 nm-node interconnect was increased from 1.1 × 10⁸ to 1.1 × 10⁹ A/cm² when Cu was replaced by graphite–Cu grown at 400 °C.⁴⁹

Finally, full replacement of Cu by graphene can be expected at line widths of a few nanometers.⁵⁰ Experimentally, graphene shows a peak current capacity on the order of 10⁸ A/cm² and the comparable resistivity to Cu lines scaled below 40 nm.^{51 52} Also, multilayer graphene intercalated with iron chloride may outperform copper in a current capacity and resistivity (>10⁷ A/cm², 3.2 µΩ at 8 nm width).^{48 53}

• Source–drain contacts

Scaling issues also challenge the front-end-of-line (FEOL) process. The Si/metal contact resistance increases as the inverse square of the device size, unlike other resistances that increase linearly as the device size decreases. This rapid increase in the contact resistance has led to it to exceed the channel resistance below 32 nm node⁵⁴ (see Fig. 11). Larger contact resistance in scaled devices prevents optimal scaling of the supply voltage, resulting in greater power consumption.

Theoretically, the contact resistance is strongly dependent on the Schottky barrier height, formed by the misalignment between the metal workfunction and the semiconductor affinity of electrons or holes. Thus, low workfunction (∼4.0 eV) metals for n-type Si and high workfunction (∼5.2 eV) metals for p-type Si are supposed to guarantee Ohmic contact behavior and low contact resistance. However, most metals show high measured Schottky barrier heights of about 0.5 eV due to pinning effects at the semiconductor interface. There have been a few candidates for resolving this contact issue by introducing a highly doped Si S/D layers or thin insertion layers between highly doped Si and contact metal. The highly doped Si results in a sufficiently narrow depletion width for effective charge tunneling, and this technique was widely used in current Si devices. However, this method is approaching the dopant solubility limit in semiconductor (<10²¹ cm⁻³), and faces challenges in shallow junction formation, high source–drain leakage currents, and low thermal stability. The insertion layer prevents Fermi level pinning between metal and semiconductor, and at the same time, the layer is thin enough that tunneling probability of charges approaches unity. For example, Agrawal et al. reported that 1 nm-thick TiO_2−x layer inserted between Ti and n-Si reduces contact resistance by an order of magnitude to 9.1 × 10⁻⁹ Ω cm².⁵⁵ However, the insulating layer is hard to control when its thickness falls below 1 nm and the thermal stability on the Si layer may be insufficient.

On the other hand, 2D materials with monolayer thickness less than 1 nm can be an optimal candidate for depinning the interface and maximizing tunneling probability. As mentioned in Section 4.2, the Schottky barrier height between graphene and Si was changed by the same amount as the workfunction of graphene by a gate voltage, proving depinning of the graphene–Si interface.³⁰ This is an attractive property for the Si/metal contact formation. Also, the graphene can reduce the metal workfunction by charge transfer, similar to surface doping.⁵⁶ This could prove helpful for n-type semiconductor contacts that need a low workfunction below 4 eV (see Fig. 12).

In addition, 2D materials have other attractive features for insertion into contacts: nonpermeability, high thermal stability, and digital thickness control with low predicted Schottky barrier heights, as shown in Fig. 13.⁵⁷

To test the effect of a graphene insertion layer at metal/Si junction, a Si AFM tip was contacted to graphene/Ni and Ni surfaces for comparison in a vacuum chamber.⁵⁸ As shown in Fig. 14, the Si/Ni junction exhibited rectifying diode-like I–V characteristics, whereas the graphene-inserted junction was Ohmic with low resistance. The measured minimum contact resistance ranged from 10⁻⁸ to 10⁻⁹ Ω·cm², comparable to state-of-the-art Si technology.

6 Graphene on Ge

For most of device applications, direct growth of high-quality graphene and 2D materials on various substrates is the most important issue. Typically, graphene has been grown on metallic catalyst substrates such as Ni³⁸ or Cu.⁴⁶ For interconnect applications, growth of graphene on insulators such as SiO₂ or SiN will be essential. Contact applications require the growth of high-quality graphene or 2D materials directly on the semiconductor surface. Recent reports on the growth of graphene on Si⁵⁹ and Ge^{37 60} and growth of MoS₂ on fused silica⁶¹ are therefore of great interest. Another important aspect is the crystallinity of graphene. Polycrystalline graphene was usually obtained in earlier works on metallic catalysts. Great progress on single-crystal graphene growth has been made using a single seed,⁶² and recent work using multiple aligned seeds³⁷ represents an interesting breakthrough.

7 Conclusion

Newly emergent 2D materials including graphene and TMDCs began as playgrounds for observing exotic physics, such as unconventional quantum Hall effect and quantum transport phenomena. Just as the fundamental understanding and exploration of conventional 2DEG in an earlier era became the cornerstone of modern IT industry, these atom-thick 2D materials may lead to an industrial revolution in the post-Si era. In particular, for electronic devices, atomically thin tunnel transistors can offer additional transparency and flexibility with comparable performance to Si, whereas for photodetectors 2D materials can provide wider bandwidth and cheaper integration with Si for data communication. They may also provide atomically thin, flexible photodetectors compatible with any surface. However, these device applications requiring active functions of 2D materials may take 5–10 years to reach the marketplace due to challenges and issues of material quality and integration. For more realistic near-term applications, we have discussed Cu–graphene hybrid interconnects and graphene-inserted source–drain contacts that may help with the critical challenges in further scaling of Si technology.

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