Gallium Nitride-Based Lateral and Vertical Nanowire Devices

Y.-W. Jo, D.-H. Son, K.-S. Im and J.-H. Lee

School of Electronics Engineering, Kyungpook National University, 80, Daehak-ro, Buk-gu, Daegu, South Korea

1 Introduction

GaN-based field-effect transistors (FETs) are widely used in power switching and amplifier applications due to the superior material properties of GaN, such as wide bandgap, high breakdown electric field, and high electron saturation velocity, which result in high current density and high breakdown voltage.^{1 2} However, GaN-based devices still suffer from challenges, such as surface and buffer-related trapping effects, that occasionally result in severe current collapse decrease and degradation of the off-state performances. While surface-related problems can be effectively addressed by appropriate surface treatment and passivation techniques,^3–6 trapping in the buffer layer cannot be easily solved because the buffer layer usually contains many defects originating from the heteroepitaxial growth of the GaN layer. Recently, AlGaN-/GaN-based triple-gate fin-shaped field-effect transistors (fin-FETs) have demonstrated superior off-state performance and also suggested a possible avenue for reducing the buffer-related trapping effects.^7–10 Even though the GaN-based gate-all-around (GAA) structure have not been realized with top-down approach thus far due to their complicated fabrication process, the GAA structure seems to exhibit greatly improved on- and off-state performances due to the enhanced gate controllability.^11–14 Furthermore, the GAA structure should also be more effective in eliminating buffer layer trapping because the entire active region of the device is surrounded by the gate metal and completely separated from the underlying thick GaN buffer layer.

In this chapter, we report on the first fabrication and characterization of GaN-based lateral and vertical nanowire (NW) FETs by using top-down approach, where we combined conventional e-beam lithography and dry etching techniques with strong anisotropic tetramethyl ammonium hydroxide (TMAH) wet etching.

2 Crystallographic study of GaN nanowires using TMAH wet etching

Wet etching techniques play an important role in the semiconductor device fabrication process. Wet etching usually provides high etching selectivity that often offers an advantage in simplifying the fabrication process compared to the dry plasma etching. However, it is very difficult to etch the III-nitride semiconductors with the conventional wet solutions because these materials have strong chemical stability.¹⁵ A few chemical solutions, such as hydroxide-based solutions (e.g., NaOH or KOH) were investigated to the etching of the III-nitride semiconductors due to their ability to react with Ga atoms to form Ga₂O₃ layer. Vertical and narrow nanorod arrays were formed using a plasma dry etch followed by an anisotropic wet etch in hydroxide solution for the purpose of high efficiency light emitting diodes (LEDs).¹⁶ However, it is very rare to use NaOH or KOH solution as the GaN etchant in electronic device fabrication because it contains alkali metal ions that cause severe threshold voltage instability. On the other hand, TMAH does not suffer from the ion contamination and has been successfully utilized in GaN-based device fabrication.^{3 8–11 17} When the GaN layer is exposed to the TMAH solution, Ga-polar (0001) plane is hardly etched (near-zero etch rate), whereas N-face plane is easily etched with the highest rate. This is because the dangling bond density (DBD) of N-face facet or other planes is larger than that of the Ga-polar (0001) facet.^{16 18, 19}

The GaN NW patterns along the and were then defined by e-beam lithography using a polymethyl methacrylate (PMMA) resist and followed by transformer-coupled plasma-reactive ion etching (TCP-RIE) using a BCl₃/Cl₂ gas mixture as shown in Fig. 1(a) and (b), respectively. The cross section of the initial etched GaN layer had a trapezoidal shape with sloped sidewall surfaces as shown in the left SEM image of Fig. 1(a) and the top SEM image of Fig. 1(b). After the dry etch, the NWs were etched in TMAH (5% solution at 90 °C) for 30 min. Due to its strong anisotropic etch characteristics, the etching proceeds only in the lateral directions but not in vertical direction along <0001>. Etching along direction makes the pattern narrower but still maintains the trapezoidal shape as shown in the right SEM image of Fig. 1(a). Etching along direction, on the other hand, changes the shape from a wide trapezoid with sloped angles to a narrow rectangle with very steep side-wall surfaces as shown in the bottom SEM image Fig. 1(b). Figure 2(b) and (c) shows the GaN crystal with wurtzite structure with and crystal planes, respectively. The crystal plane has 58.4° slope (Figs 1(a) and 2(b)). On the other hand, the crystal plane consists of both Ga and N atoms with 90° angle from the (0001) plane (Fig. 1(b) and (c)). The reason for the difference of the exposed plane along the wafer direction is due to the different etching rate between along and directions. When the rectangular GaN pattern is etched by dry etching, the (0001) planes at the inside and the outside of the pattern and sidewalls of facets are exposed. The facets have higher DBD (16.0 nm⁻²) than the (0001) plane (11.4 nm⁻²), which results in a higher TMAH etch rate,^{18 19} so the TMAH-etched GaN layer has a hexagonal shape due to its wurtzite crystal structure. As shown in the schematic of Fig. 1(a), the pattern along direction consists of the bottom hexagonal (0001) plane and the sidewall facets with the trapezoidal shape. On the other hand, along the direction as shown in the schematic of Fig. 1(b), the sloped sidewall is first etched with relatively fast rate and when the vertical crystal plane is exposed, the etching slows because the DBD of plane (14.0 nm⁻²) is smaller than that of plane.^{18 19} Further etching widens the plane along direction.

To form the vertical GaN NW structure, the plasma-enhanced chemical vapor deposition (PECVD) SiO₂ mask was first patterned by e-beam lithography with width and pitch of 300 nm. Dry etching with TCP-RIE was performed to obtain the initial trapezoidal NWs with height of 300 nm as shown in Fig. 3(a). Anisotropic wet etching in TMAH solution (5% concentration at 80 °C) was then applied for 11 min to reduce the diameter of the nanowire. The TMAH solution etches the nanowire under the SiO₂ mask layer only in the lateral direction but not in the vertical direction, which results in NWs with average diameter of 100 nm and very steep sidewalls as shown in Fig. 3(b). The initial vertical GaN nanowire structure has two different planes: top (0001) c-plane and semipolar planes formed at the sidewalls. The TMAH solution can selectively etch the N-polar sidewalls while leaving the (0001) Ga-polar top surface unaffected. The N-polar facets of the GaN vertical nanowires were removed gradually accompanied with the exposure of the facets. This is because the DBD of facets (12.1 nm⁻²) is smaller than that of facets (16.0 nm⁻²).¹⁸ The GaN nanowire with facets has the nonpolar characteristics.²⁰ The corresponding atomic models matched to these crystal planes are shown in Fig. 2(b) and (d), respectively.

3 Ω-shaped-gate lateral AlGaN/GaN FETs

To fabricate the AlGaN/GaN Ω-shaped-gate nanowire FET, the GaN epitaxial layers were first grown on c-plane sapphire substrate by MOCVD. The structure consisted of 30 nm-thick low temperature-grown GaN as a nucleation layer, 2 µm-thick undoped GaN semi-insulating layer in growth sequence, followed by an 80 nm-thick undoped GaN layer and 30 nm-thick Al_0.3Ga_0.7N layer. Hall effect measurements showed that the two-dimensional electron gas (2DEG) density and mobility were 9 × 10¹² cm⁻² and 1800 cm²/V·s, respectively.

Figure 4 shows the detailed fabrication process for the Ω-shaped GaN nanowire structure. The formation of nanowire structure was achieved by obtaining the crystal plane with very steep sidewall surface as described in Fig. 1. The initial patterns along the direction were defined by e-beam lithography using PMMA, followed by TCP-RIE using a BCl₃/Cl₂ gas mixture, which resulted in trapezoidal shape with sloped sidewalls as shown in Fig. 4(a). Then, TMAH wet etching (5% solution at 90 °C) was employed for 30 min to change from a wide trapezoid to a narrow rectangular shape with very steep sidewalls (see Fig. 4(b)). The 20 nm-thick atomic layer-deposited (ALD) HfO₂ spacer mask for subsequent etching process was deposited on the steep sidewall surface as shown in Fig. 4(c). A second dry GaN etch step followed by TMAH lateral wet etching were used to etch the exposed GaN layer for 10 hours to form the Ω-shaped structure in Fig. 4(d) and (e). After removal of the sidewall HfO₂ spacer, a 20 nm-thick ALD Al₂O₃ gate insulator and 30 nm-thick TiN gate metal were deposited (see Fig. 4(f)). Finally, Fig. 4(g) shows the cross-sectional TEM image for the GaN Ω-shaped nanowire structure. The total height and width of this structure were 280 and 55 nm, respectively. The width of the neck between the structure and the buffer layer was around 13 nm.

The GaN nanowire FET fabricated on this Ω-shaped structure exhibits much better performance than the reference device, with extremely low off-state leakage current as low as 10⁻¹⁰ mA, the subthreshold swing (SS) value of 59 mV/dec, and high I_ON/I_OFF ratio (∼ 10¹⁰) as shown in the I_D–V_G curve of Fig. 5. On the other hand, the reference device had much higher off-state leakage current (10⁻⁷ mA), an SS of 74 mV/dec, and a lower I_ON/I_OFF ratio ∼10⁶. The difference in the off-state performance between two devices is because active region of the Ω-shaped structure is fully depleted and isolated from the thick GaN buffer region, comparing to the reference tri-gate structure.

4 Gate-all-around vertical GaN FETs

The epitaxial structure of Si-doped GaN/undoped-GaN/Si-doped GaN (70/120/500 nm) stack was grown by MOCVD on sapphire (0001) substrate. The doping densities of Si-doped and undoped GaN layers were 1.0 × 10¹⁹ cm⁻³ and 2.0 × 10¹⁶ cm⁻³, respectively. First, a SiO₂ mask was patterned by e-beam lithography with both diameter and pitch of 300 nm. The vertical NW pillars were defined by TCP-RIE using a BCl₃/Cl₂ gas mixture, forming NWs with slanted sidewalls and height of 300 nm. The TMAH wet etch step (5% of solution at 80 °C) was used for 11 min to reduce the diameter of the nanowire as shown in Fig. 6(a), resulting in vertical sidewalls average NW diameter of 100 nm. The TMAH wet etching not only eliminates the plasma damage but also smoothens the etched GaN surface.¹⁷ Then, the SiO₂ mask layer was removed prior to the deposition of a 10 nm-thick Al₂O₃ gate dielectric layer and a 20 nm-thick TiN gate metal by ALD. Then, a 20 nm-thick PECVD-deposited SiO₂ mask layer and a photoresist (PR) were deposited, as shown in Fig. 6(b), followed by a blanket etch to remove the PR/SiO₂/TiN/Al₂O₃ layers from the tops of the NWs as in Fig. 6(c). An SC-1 solution (NH₄OH:H₂O₂:H₂O = 1:1:5 at 70 °C) was used to define the TiN gate, with the SiO₂ mask layer protecting the TiN from being etched in the lateral direction as shown in Fig. 6(d). For the isolation of gate from the drain, an additional 100 nm-thick SiO₂ layer was deposited, followed by another blanket etch to enable the deposition of Ohmic Ti/Al contacts (Fig. 6(e)). After rapid thermal annealing at 500 °C for 30 s in N₂ ambient, Ni/Au metal layers were deposited for gate pad (Fig. 6(d)).

Figure 7 shows a schematic and the cross-sectional TEM image of GaN-based vertical NW-FET. The number of nanowires in parallel is 12; the height of the TiN gate metal and the separation between the drain end of the gate metal and the drain are 200 and 100 nm, respectively.

Figure 8(a) exhibits the transfer curve at V_D = 1 V of the fabricated GaN vertical NW-FET, which demonstrates a normally off operation with a threshold voltage of 0.6 V. The normalized maximum drain current and the maximum transconductance at V_D = 1 V, divided by the total gate width (NW diameter multiplied by the number of NWs), are 130 mA/mm and 70 mS/mm, respectively. Figure 8(b) shows the subthreshold characteristics (at V_D = 0.1 V) of device with SS of 153–163 mV/dec depending on the V_G sweep direction, good I_ON/I_OFF ratio as high as 10⁹, and excellent off-state leakage current as low as ∼10⁻¹² mA. We attribute the good off-state performance to GAA nanowire structure that eliminates the detrimental effects related to the buffer layer encountered in conventional planar-type FETs. Also, TMAH wet etching effectively smoothens and removes the plasma damage from the etched GaN surface.³

5 Conclusion

To summarize, we have proposed and demonstrated GaN-based lateral and vertical nanowire FETs for the first time using top-down approach by combining conventional e-beam lithography and dry etching technique with strong anisotropic TMAH wet etching. The AlGaN-/GaN-based omega-gate NW FETs have been fabricated using TMAH orientation-selective lateral wet etching of ALD-deposited HfO₂ sidewall spacer. The device exhibited excellent off-state performance: an SS of 62 mV/dec, close to the theoretical minimum, and an extremely low leakage current of 10⁻¹¹ mA with a very high I_ON/I_OFF ratio of 10¹⁰. We attribute these remarkable off-state characteristics to the Ω-shaped gate structure, which not only facilitates full depletion of the active region but also eliminates leakage paths between the active region and the thick GaN buffer layer. In addition, vertical GaN-based NW FETs with nanowire diameter of ∼100 nm were demonstrated by using top-down fabrication approach involving orientation-selective TMAH wet etching. The device exhibits very low off-state leakage current and high I_ON/I_OFF ratio due to the GAA layout. The top-down approach provides a viable pathway toward GAA devices for III-nitride semiconductors, which are very promising candidates for steep-switching power device applications.

Acknowledgments

This work was supported by the BK21 Plus funded by the Ministry of Education (21A20131600011), the IT R&D program of MOTIE/KEIT (10048931), and the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIP) (No. 2011-0016222, 2013R1A6A3A04057719).

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