Improved Parallelism from EPIC

The Itanium architecture uses every practical technique to increase parallelism, or the ability to execute multiple instructions during each machine cycle. Parallelism improves performance because it allows more instructions to be carried out at once. The architecture of the Itanium processor family is designed not only to take advantage of parallelism, but to do it explicitly.

The whole raison d'etre of the EPIC architecture is to make absolutely certain that as many instructions per cycle as possible are executed and to ensure that the compiler has the available resources to sustain this high rate of completion. And although all processors face penalties if an instruction is incorrectly executed or scheduled, these are minimized in the Itanium processor, reducing their effect on parallelism.

This is the design philosophy at the heart of the EPIC. The EPIC philosophy is a big reason why Itanium processors are so different from other 64-bit processors. This newly developed architecture provides much higher levels of ILP without unacceptable increases in hardware complexity.

Compilers Under EPIC

How does EPIC achieve such excellent performance? It does so by placing the burden of finding parallelism squarely on the compiler. It is true that processor hardware can pull out parallelism in a limited form. However, it is more efficient and speedier to let the compiler find the instances of parallelism explicitly. Since a compiler can see the whole code stream, it can make global optimizations as it runs through the code.

The compiler communicates this parallelism explicitly to the processor hardware. It does this by creating a three-instruction bundle that it issues to the hardware with directions on how the instructions should be executed. The hardware focuses almost entirely on executing the code as quickly as possible.