Instruction-Level Parallelism (ILP) Compilers

In the age of CISC computers, there was no significant ILP available to the user or compiler. Most compilers of the era were merely an enabler for the higher maintainability and convenience of high-level languages, but the developer had to pay a performance price for not using assembly language.

Early RISC processors first began exposing ILP. With nonstalling loads and exposed branch latencies, the role of the compiler in performance began to increase. As the RISC era progressed, instruction scheduling became increasingly important to performance.

However, the RISC architectures severely restrict the compiler's ability to express the available parallelism. With EPIC, the compiler has the architectural tools to express far more parallelism. It becomes the driving force in realizing the performance potential of the underlying hardware.