Glossary
- Architecture
This term describes the internal structures of a microprocessor and how they work individually and together. Architecture is a term for the total design and design concepts. It also describes the assembly language instruction set of the microprocessor.
- Complex Instruction Set Computer (CISC)
Intel Pentium processors are based on CISC architecture with the same elements of RISC included. CISC instructions are more complex and generally take multiple CPU clock cycles to execute. Not as many can be completed per second, but each instruction does more work in comparison to the more streamlined RISC instructions.
- Compiler
A compiler interfaces between a programmer's high-level instructions and the hardware that can execute those instructions. The programmer writes code in a language such as C or C++. It is then put through a compiler, and the compiler analyzes the language statements and builds output code in a form that can be understood and executed by the system hardware. Before the Itanium processor family, it fell on the hardware to do the work of finding parallelism opportunities and optimizing them. This meant more chip complexity with less room for improving performance. With Itanium, the compilers now do that work. Itanium processor family compilers break regular sequential code into 128-bit sections with instructions attached telling the processor how the different instructions interrelate. This explicit expression of parallelism allows the processor to concentrate on executing parallel code as fast as possible, without further optimizations or interpretations. See Implicit Parallelism.
- See also [Explicit parallelism]
- Endian
Computers store data in binary format, a series of bits that are either 0s or 1s. Numerical data is represented at the machine level as strings of bits. Numbers or letters are stored as 8 bits in a structure called a byte. In a big endian format, the most significant digit is the left-most byte (so the number is read left to right). In the little endian format, this is just the opposite, with the data read right to left. Operating systems such Windows NT are little endian; other operating systems such as HP-UX are big endian. It does not matter to the Itanium processor family architecture whether a system is little or big endian, because it is endian-agnostic and can work with both forms.
- Explicit parallelism
An Itanium processor family compiler turns sequential code into parallelized 128-bit bundles of instructions that can be directly or explicitly parallel-processed by the CPU without having to interpret it further. See Implicit Parallelism and Compilers.
- Explicitly Parallel Instruction Computing (EPIC)
EPIC is the acronym to describe the architecture behind the Itanium processor family architecture, co-developed by Hewlett-Packard and Intel. This design philosophy will eventually replace RISC and CISC.
- Implicit parallelism (RISC)
A regular (non-Itanium processor family) compiler examines and optimizes sequential code for parallelism but then has to regenerate sequential code, relying on the processor to re-extract the parallelization as the instructions are executed by the CPU. The processor then has to read this implied parallelism from the machine code, rebuild it, and run it. The parallelism is there, but more decoding work has to be done by the hardware before it can be utilized. See Compilers.
- See also [Explicit parallelism]
- Instruction set
The instructions list is assembly language used by the microprocessor. Traditionally, the two main instruction set philosophies were CISC, typified by IBM mainframes and Intel's Pentium processors, and RISC, typified by HP's PA-RISC processors and other vendors' RISC programs.
- Itanium processor family
The Itanium processor family represents the entire range of processors that are based on the EPIC architecture, co-developed by HP and Intel.
- Parallelism
For Itanium this refers to the ability to carry out many different tasks at once at the CPU or microprocessor level. Sequential events happen one after another; parallel events happen simultaneously. Modern RISC processor architectures have some capacity to do more than one operation at once.See Implict parallelism.
- See also [Explicit parallelism]
- Processor
- See [Central processing unit (CPU)]
- Sequential
Events that execute one after are sequential. For example, all computer instructions are presented sequentially to the compiler. The execution of the program is optimized for the Itanium processor by finding blocks of the program that can be executed in parallel by the microprocessor.
- Registers
A register is a temporary storage location within a processor where data can be stored for fast access. For example, when the processor needs to add two numbers, each number is stored in a register and the result of that addition is also stored. The Itanium processor family architecture specification specifies multiple sets of 64-bit registers.
- Reduced Instruction Set Computer (RISC)
CISC processors predominantly used more complex instructions that required several clock cycles to execute, but did more work. RISC processors take a different approach by relying on shorter, simpler instructions that execute in one clock cycle so that more of them can be carried out per second. The HP PA-RISC processor uses RISC instructions.