In Summary

• Early RISC processors first began exposing ILP. With nonstalling loads and exposed branch latencies, the role of the compiler in performance began to increase. As the RISC era progressed, instruction scheduling became increasingly important to performance.

• HP and Intel co-developed the Itanium architecture. The result is a high-performance, parallel, 64-bit architecture that has the performance headroom to grow in the future and can be priced at a level to ensure its widespread adoption. The Itanium architecture fulfills both of these promises and is likely to become pervasive very quickly.

• The newly developed EPIC architecture provides much higher levels of ILP without unacceptable increases in hardware complexity. EPIC achieves such excellent performance by placing the burden of finding parallelism squarely on the compiler.

• Itanium's unique EPIC architecture allows inlining of code. Speculative inlining and execution is the most common variant of this. The compiler can look at many small procedures and put them in line so that it can look at these procedures as one long block of executable code.

• EPIC has tremendous flexibility in being able to run both little-endian and big-endian applications and operating systems. There are a number of features built into the new EPIC architecture that will be of special note to developers and coders. These features start with an advanced floating-point architecture.

• The current HP compilers are extremely mature for this point the in development cycle of a new architecture. They also come with many of the qualities that make them ideal for work in the EPIC world.