Untapped Parallelism in RISC

Most of the RISC machines today are what we call '4-issue' processors. This means that in theory they can do a maximum of four things in parallel. However, because of the way the architecture of processor is set up—the hardware on the chip, and the software that controls it—this level of parallelism is rarely reached on a regular basis.

All CISC and RISC-based machines are based on the model of a Von Neumann engine. This engine is the basic computer model where the processing must appear to be done sequentially. One instruction is completed, and only then is the next picked up, and so on and so forth. It's a purely sequential architecture, and because it is set up like that, it's difficult to do anything in parallel. So you're left with a limited ability to parallelize the operations within an application.

What was done in developing an out-of-order execution RISC processor was to place control logic on the chip itself to encourage parallel running. However, in actual practice, the parallel capabilities are limited. You're left with a very basic, straight-line sequential way of doing things where more than half the processor's power is left untapped during each clock cycle. This untapped potential exists, no matter how fast your clock speed is. A graphic depiction of this is shown in Figure 7-1, shown below.