Chipset Objectives

Early market penetration will be especially high in markets where the ability to address large amounts of physical memory is important. These include the early adopter markets such as Computer Aided Engineering, Life Sciences, in-memory databases, large key or complex algorithm cryptography. In short, those who do what we defined in Chapter 4 as 'Technical Computing'.

The High Bandwidth, Low Latency Chipset

The HP zx1 Chipset is a modular three-chip solution designed by HP to enable them to provide customers with a cost-effective, high bandwidth, and low latency 1-to 4-way workstations and servers based on the next generation Itanium processor family platform. This chipset enables HP to deliver features that power users want without compromising schedule, performance or cost.

Memory bandwidth is the rate at which data can be sent/received to/from the main memory. Bandwidth is needed to get the highest level of application performance. For 1-way and 2-way systems, the HP zx1 Chipset enables 8.5 GB/s. For 4-way systems, the chipset enables 12.8 GB/s.

Latency is the amount of time from when data is requested by a processor to the time it is received. In digital designs, a typical method for increasing memory bandwidth is to increase the number of pipeline stages, which causes an increase in latency. The HP zx1 Chipset's uncompromising design provides high bandwidth and low latency for Itanium 2-based systems from HP. The result is superior applications performance.

Historically, HP's strength has been to develop and tune systems to deliver the kind of performance that professionals demand. The HP zx1 Chipset was designed to provide the best performance for demanding applications that do not fit within the processor cache. The memory system design is the key to performance in these cases. Here, the zx1 memory bandwidth has been optimized with dual memory controllers to provide up to 12.8GB/sec in a 4-CPU system and 80 nS of open page latency in a 2-CPU system.

The right functionality is provided by the optimized memory capacity. At 48GB, HP's 4-way system provides three times the memory capacity of other chipsets AGP4X support is also available, which provides for full, 3D graphics performance. HP's zx1 supports AGP4X, which enables designers to choose the parts they need, and the numbers of these parts to meet their specific system design requirements.

Clustering

Another area where this chipset will shine is in the area of clusters. We are seeing a huge appetite for dense, dual processor compute nodes with extreme floating-point performance. Most of this demand is for clusters running Linux.

The HP zx1 chipset is ideally suited for this purpose. It combines its industry leading bandwidth with the Intel Itanium processor's powerful floating-point performance. This allows it to make extremely impressive speed gains on large dual-processor clusters.

The Three Central ASICs

This chipset provides the high degree of parallel performance that ensures fast results and better time-to-market. HP is seeing demand from numerous National labs and other science and research institutions. Many of these organizations want to consume thousands of Itanium processors in zx1-based systems because of the Linux support and industry leading latency chipset layout for two of our Intel McKinley processor products. The impressive technical gains can in part be attributed to the workings of the critical three ASICs that are part of the chipset (see Figure 17-1):

The HP zx1 Memory and I/O Controller

The controller connects to the processor bus. It contains both the memory controller and the I/O cache controller. It interfaces to the Itanium 2 processor bus and provides a low latency connection to DDR memory either directly or through zx1 Scalable Memory Expanders. This component can connect up to 12 Memory Expanders for quadruple the base memory capacity at the same time that eight I/O adapters are handling 4GB/sec of I/O bandwidth.

The HP zx1 I/O Adapter

The adapter is a chip that is a scalable solution. It is designed to support PCI, PCI-X and AGP bus architectures. It provides a scalable I/O implementation for a wide variety of systems.

The HP zx1 Scalable Memory Expander

The expander is an optional component used to increase memory capacity (up to four times) and increase bandwidth to the main memory to 12.8 GB/s. Acting as a memory hub, it decreases the number of signal loads on the memory bus, thereby allowing the system to dial up its memory transfer rate. The trade-off of using the zx1 memory expander is the cost of the chips and their footprint together with a modest 25ns of additional memory latency relative to direct attach.