Floating Point Architecture

Floating-point calculations, which involve mathematical computations between numbers with large numbers of decimals, are done on a separate 'floating point' registry. In the Itanium processor's architecture, floating-point operations are performed with these registers as extended precision calculations. Since floating point can take advantage of 64-bits of precision, the Itanium processor has a natural advantage in handling numbers with a large number of decimal places, extreme amounts of precision and can reduce 'round-off' error, as discussed in Chapter 4's section on 'Early Adopters'. The 82-bit register design allows the Itanium processor to extend the calculations out to a much larger number of decimal places, thus providing a higher level of accuracy that is critical in many scientific applications.

The floating-point architecture is a perfect example of the interplay that occurs between a number of EPIC concepts. Software and hardware features blend to make a unique floating-point architecture that has both high performance and excellent accuracy. Floating point performance is key to many applications in scientific computing, life sciences, and areas of business intelligence and e-commerce where more analytical workloads are processed.

Floating-point specific instructions like the Floating Point Multiply Add (FMA) removes intermediate rounding stages, so speeding the execution of some floating-point calculations without increasing the error produced by rounding. This extra accuracy has made Itanium even more valuable in certain functions: rendering applications, simulations, and security areas such as encryption/decryption.

For these reasons, Itanium's EPIC architecture is rightly considered in two ways: the next generation of chip architecture, and also a break from the RISC tradition of processing.