Preexisting and Continuing Trends
It's something of a cliché to say that to truly see where you are going, you need to look back at where you've been. However, it also happens to be very true in this case. If you take a look at Figure 18-1, you'll get a sense of one of the reasons why we chose to go to a new architectural design for the next generation of microprocessors.
Figure 18-1. Microprocessor Performance Growth
Where Have the Speed Gains Come From?
Let's talk about what Figure 18-1 really shows. This chart is actually one driver for deciding that it was time to work on parallelism rather than clock speed to gain leverage in improving performance in the future. The observation was that up until 1993, the improvements in the performance growth came equally from clock cycle improvement, shrinking the chip die, and architectural improvements.
Speed gains from improving the architecture resulted in increasing the number of instructions that could be done per clock cycle. The gains moved from .045 from the early RISC machines in the 1970s to .92 per cycle. Note that an almost one instruction per cycle increase was reached at this time.
From the chart, it is obvious that on the hardware side and the architecture side, speed gains had increased almost 22 times. But what made us think that a new architecture was needed, and what actually led to the wholesale development of the next generation of architecture—EPIC—was that between 1993 and 1997, most of the improvements had come from the hardware side by shrinking the die and turning up the clock speed. The move from 60 MHz to 300 MHz was an almost 110-fold improvement.
The Architectural Lag—And Opportunity
On the architecture side, the gains had lagged at only a 42-fold improvement. And that was assuming that you actually could come close to having two instructions completed per cycle. This was a clear indicator to Hewlett-Packard that to attack the need for continued improvements, it needed to tackle the problem from the architectural side of things.
Hence, HP and Intel set about the development of the new architecture. Now that it has reached the point of deploying this new design in the marketplace, HP is very happy with the results. Instead of two instructions per cycle, it has pushed the boundaries to four and even six instructions per cycle. This has served to shift the dynamic of improving the chip so drastically that now it is looking at how to generate similar improvements from the hardware side again. This is where Hewlett-Packard will look to make the next breakthrough with this architecture.