Chapter 8. Key Architectural Changes in EPIC
In a very real sense what we were trying to do was go explicitly for high levels of instruction parallelism that were easily generated by a compiler and to eliminate all this hardware complexity that was growing up around the out-of-order superscalar implementations of RISC machines. And this is really—and this is really what led to EPIC.
—Bill Worley (RISC and EPIC architect)
In This Chapter:
Static and dynamic branching
The whole purpose of the Intel Itanium architecture[20] is to use every practical technique to increase parallelism so that the processor can execute as many instructions per cycle as possible and to have the resources to ensure that this rate can be sustained as best as possible. This can be accomplished because of the design philosophy at the heart of the Itanium processor family—the Explicitly Parallel Instruction Computing (EPIC) philosophy.
[20] Intel and Itanium are registered trademarks or trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
EPIC defines why Itanium-based processors are different from other 64-bit processors by enabling much higher levels of instruction level parallelism without unacceptable increases in hardware complexity. EPIC does this by placing the burden of finding that parallelism squarely on the compiler, which can review the entire code stream and make global optimizations.