Squaring the Overhead in RISC

Additionally, we also ran into an interesting result as we tried to move beyond 4-issue machines to 6 or 8 issue machines. The overhead that was placed on the chip's transistors just to keep track of what was going on when scheduling parallel operations increased exponentially as we increased linearly the number of functional units. Therefore, if you tried to move from a 4-issue to an 8-issue processor, the overhead did not increase by a factor of two—it increased by a factor of four!

From a RISC standpoint, this was an extremely frustrating and discouraging development. After all, what good did it do to try to increase the speed of a processor by adding more transistors if a greater and greater portion of the processing power you were trying to add got burned up in overhead? Overhead in this case is similar to the kind of overhead you'll find in a manufacturing organization—costs that cannot be avoided, but do not contribute to the bottom line except to soak up funds.

The overhead on a processor actually originates from the transistors whose job it is to take instructions from the compiler that are to be executed. These transistors try to organize and arrange instructions in such a way that the processor can figure out which of these can be executed at the same time (i.e., in parallel). The logic that is required to do this is the real contributor to overhead on a processor, because it demands an ever-larger number of transistors to track and determine how to run these instructions.

The increased overhead when trying to push for higher performance gave us very definitive results. Predictably, the performance curve began to flatten out as we tried to develop the chip beyond the 4-issue architecture. This made developing more powerful parallel processing RISC-based chips an expensive and unattractive option to HP. It all but proves out Moore's Second Law, where the cost of producing more powerful chips became economically unattractive.