Index

Note: Page numbers followed by f indicate figures, and t indicate tables.

0–9

0V node symbol 9, 11–12, 29, 30f, 342, 342f
$D_HI digital symbol 9, 12
$D_LO digital symbol 9, 12
⁎ (comment lines) 126, 219–220, 228–229, 235

A

A Kind Of (AKO) models, definition 220–221
Absolute sensitivity 352, 354
Accept Left 336, 344–345, 345f
AC Markers 72
AC sources 69–70, 69f, 73
AC Sweep 70–78, 170, 170f
active smoke parameters 392–395
Add File 32, 329
Add Library 32
Add New Row 255, 255f
Add New Row 80–81, 82f
Add Part(s) To Active Testbench 332, 332f
Add Part(s) To Self 333, 333f, 342, 342f
Add to Design 328–330
Add to Design 111
Add to Profile 107
Add Trace 75–76, 75f, 264
Advanced Analysis 347–349, 360, 365
circuit performance 347–348
design flow 347, 347f
libraries 349
measurement definitions 348
Monte Carlo 381
Monte Carlo analysis 348–349
Parametric Plotter 349
reliability 348
Advanced Analysis libraries 406, 406f
air core transformers 141–149 See also transformers
All markers on open schematic 160
analog behavioral models (ABMs) 133, 185–191
analog library 11, 16
Analog Operators and Functions 75f, 76
analog power supplies, templates 19
analog to digital (AtoD) 260
Analysis type 36, 48, 52, 54, 96, 97f, 123, 123f, 136–137
AND gates 259 See also NAND gates
area scaling factor 202
Ascend Hierarchy 294
Assign Tolerance window 386, 387f, 420
Assign Tolerance window 355–357, 356f, 362–363
Associate/Replace Symbol 228, 326–328, 326f, 328f
AutoConverge 135, 135f
Auto Wire 30, 30f, 261
Auto Wire Two Points 30
Available Sections 257
AWG wire standard 320
Axis Settings 66–67
Axis Settings 114f
Axis Variable 216, 216f

B

bandpass filters 152, 152f, 156–161, 157f, 160f
Bandwidth  See also Measurement Definitions
Performance Analysis 161
Base parasitic resistance thermal noise 202
Base shot and flicker noise currents 202
batteries 11
Bias Point 136–137
bias point analysis 38–45, 53, 117–118, 132
displays 43–44
Load Bias Point 45
Netlist Generation 38–42
Save Bias Point 44–45
significant digits displayed 43
suppression option 35–36, 41
Bias Point Node Voltages 172–173
bias simulation profile 108f, 136–137
binary bus signal displays 264
binocular button 339, 339–340f
bipolar transistors 393–395
Bobbin 318–320, 318f, 322–323, 323f
bobbins 311–330
bobbin-winding selection MPE step 318–320, 323
Bode and Nydquist plots 72
Boltzmann’s constant 197
bottom-up designs 283–310 See also Hierarchical Symbols
breakout library 16–18
Browse 6
Browse File 32–33, 32f
Bus Entry 261–273
buses  See also digital simulations
custom-made buses 271f
signal connections 261–262
signal displays 263–264, 268–273

C

C (capacitor) prefix, PSpice implementation definitions 219, 219t
Cadence 7
capacitors 391–392
CAPSYM library 9, 11, 47
CenterFrequency 160–164, 163f, 177 See also Measurement Definitions
Change Project Type 26, 26f
characteristic impedance, transmission lines 243–258
Chebyshev filter characteristics, ABMs 185–186
checkpoints  See also Check Points
transient analysis 118–124, 126–129
circuit errors 131–139 See also errors
Cleanup Cache 304
Clock Oscillator 279–281, 332–346
Clock Oscillator 306f, 307
coaxial cable models 244
coils of wire 313–330 See also inductors
Collating Functions 
Monte Carlo simulations 154–155, 155f
worst-case analysis 165, 168–169, 171, 171f
Collector parasitic resistance thermal noise 202
Collector shot noise current 202
Color Settings 57, 59
column format Property Editor 80, 81f
comment lines (⁎) 126, 219–220, 228–229, 235
comparators, ABMs 186, 187f, 275–281
Component Filter 411, 411f, 413, 417
component-selection MPE step 312–313
component tolerances, worst-case analysis 165–175
conditional statements, ABMs 186, 187f
conductor resistance 243–258
Configuration Files 126, 233, 329
Connect to Bus 261–262
constraints 367
control system parts ABM devices 185–191
convergence problems 117, 119 See also Simulation Profile Settings
AutoConverge 135, 135f
Core 220t
Core Details 316, 316–317f, 318, 319f, 322–323, 323f
coupling devices 141–149 See also transformers
Create a blank project 6
Create based upon an existing project 6
Create Derate File 397
Create parts for Library 239
Create PSpice Project 6, 6f, 357
Create PSpice Project 401, 406, 416
Create Test Bench 332, 336
creating a PSpice project 217–242
creating PSpice models 217–242, 311–330
creating test benches 336
cumulative distribution function (CDF) 349, 379–380, 380f, 383, 383f
curly braces 79, 219–220, 254 See also global parameters
current markers 54–67
current sources 11
cursors 11, 29, 80, 86, 86–87f, 104
icons 86, 87f
pen cursors 114
Curve-fit definitions 367, 376–377
Curve-Fit Error 376
custom-made buses 271f
Cutoff_Lowpass_3dB 183
CVN parameter 391–392

D

D (diode) prefix, PSpice implementation definitions 219, 219t
data converters 15
DATACONV library 277, 277f
DB() 76
dB level down for measurement 162–164, 162f
dB Magnitude of Voltage 98
DC analysis 54, 54–59, 59–62, 63–67, 85, 79, 141–142, 333 See also parametric…
DC Sweep 54–67, 232
Markers 54–67, 86
missing DC path to ground errors 131, 141–142, 333–334, 340, 342
DC bias point analysis 38–53
Load Bias Point 45
Netlist Generation 38–42
Save Bias Point 44–45
DC Sweep 54–67, 232, 232f
DC Sweep 83–89, 85f, 117–118
Decade 90
delay circuit diagram, ABMs 193–195, 193–194f
delay lines 259–273
Delete All Traces 76
Demo Designs 20–21
derating curve 
capacitor 391, 391f
resistor 387, 388f, 398, 398f
transistor 393, 393f
derating factor 400
Descend Hierarchy 284, 294
DeselectAll 339, 340f
Design Cache 304, 305f
design cycle, MPE 311–330
design opening 24
Design Resources 26
Design Status 321–322, 321–322f, 324
Destination Part Library 235
Destination Part Library 296
Destination Symbol Library 325, 326f
dev 168
Devices and Printers 21–22
dielectric capacitance 243–258 See also RLCG
dielectric conductance 243–258 See also RLCG
Diff and Merge 343–346
Differential 328–330
differential ABMs 185–191
digital circuits 259–273, 275–281
Digital Counter 332–346
Digital Counter 306–307, 306–307f, 309
digital devices 259–273
digital power supplies, templates 19
digital pull-up resistors 260–273, 275–281
digital simulations 30 See also buses; gates
displaying digital signals 263–264
profile 262–263, 276–281
timing hazards 262
timing violations 259, 262
warning messages 262
digital sources, Stimulus Editor 100–115
digital symbols 8–9
digital to analog (DtoA) 259
digital to analog converters (DACs) 276–281
dig_misc library 260
DigSTIM 103, 103f
DINPUT 220t
discontinuous conduction mode, flyback converters 311–330
Discrete engine 374
Discrete simulation 374
dispersion losses, transmission lines 243–258
Display 80–81, 83f
Display Properties 158, 158f, 247, 248f, 255–256, 255f, 359, 359f
Display Properties 303, 304f, 401–402
displays 72, 74–75, 145
bias point analysis 43–44
bus signals 263–264, 268–273
Property Editor 81, 83f
distributed models, transmission lines 246–258
dot convention 142
DOUTPUT 220t
downloading models from vendors 228–229
dual opamps 95–96, 95f

E

E device 185–186, 186f See also voltage-controlled voltage sources (VCVSs)
E13_6_6 core 318, 318f
E19_8_9 core 321, 322f
Edit Derate File 397, 397f, 412–413
Edit Part 238–239
Edit Properties 170
Edit Properties 358
Edit Property Values 157, 158f, 170
Edit PSpice Model 142–143, 210
Edit PSpice Model 363, 370
EditStimulus Editor 113
EFreq ABM 192, 192f
Emitter parasitic resistance thermal noise 202
Empty Project 416
encryption, PSpice models 229–230
Encrypt Library 229–230
End Mode 29
Enter bobbin 318–320
Enter Insulation Material 313, 314f
equivalent inductor circuits 165, 166f
equivalent input noise 
concepts 197–200
definition 200–202
Error Graph 375, 377
errors 41, 259, 262, 333, 342 See also mistakes; warning messages
common error messages 131–139
convergence problems 119, 131–139
floating node errors 62f, 333, 342
less than two connections at node errors 132
missing DC path to ground errors 131, 141–142, 333–334, 340, 342
Output File 41
timing hazards 262
timing violations 259, 262
voltage source or inductor loop errors 132, 138, 138f
ESR 390–392, 414
eval library 17
Evaluate Measurement 182–183, 279–281
Evaluate Measurement 359, 364, 370
EXP Attributes 106
Export 106f
Exporting Capture designs 21–22, 23f
Export to Capture Part Library 224, 238
Extract Model 142–143
Extra library work 32–33

F

F devices 185
FALL_EDGE 169
Family Name 316–318, 318f
Ferroxcube 316–318, 317–318f
filter circuits 151
F5 key, refreshed displays 44
flat designs  See also hierarchical
definition 283, 283f
flicker noise 198 See also noise; semiconductors
flip-flops 259–273, 276–281, 335 See also registers
initialization 262
mistakes 262
Floating Nets 333–335
floating node errors 62f, 333, 342
Flyback Converter 312–330
flyback converters 
MPE 311–330
testing 328–330
footprint 81, 83t
forward converters 20, 20f
frequency-related signal losses 243–258
frequency responses 
ABMs 188, 189–190f, 190
AC analysis 70–78, 96, 97f
frequency tables, ABMs 192, 192f
Functions 212
Functions and Macros list 359, 364, 370

G

G device 185–191 See also voltage-controlled voltage sources (VCVSs)
gain and phase responses 70
Gaussian distribution 380
Gaussian normal distributions 153–154, 156
Generate Part 229, 235
Generate Part 288, 289f, 296
global parameters 79–98, 85f See also parametric analysis
curly braces 79, 219–220, 254
definition 79
mathematical expressions 79
GMIN 118
goal functions 367
ground 
missing DC path to ground errors 131, 141–142, 333–334, 340, 342
symbols 61–62
gyrators 165, 166f

H

H devices 185
henry units 141–142
Heterogeneous parts per package 95–96, 96f
hexadecimal bus signal displays 264
Hide Invalid Values 402, 407, 408f, 417, 422
Hierarchical Blocks 21, 287–288 See also top-down designs
hierarchical designs 
passing parameters 289
power supplies 291
Project Manager 283–284, 284f, 292–294, 296–297, 300–301, 300f, 304, 307, 333, 333f, 336–343, 338–339f
schematic folders 283–284, 283f, 288, 300f, 307
test benches 332–346
testing oscillators 300–302
hierarchical netlists 290
Hierarchical Pin 284, 288
Hierarchical Symbols 287–288 See also bottom-up designs
definition 288
saving to libraries 287
Hierarchy 333, 333f, 336–343, 338f
Hierarchy 284–285, 294, 296, 300–302
Histogram Divisions 164
histograms 152, 161, 163, 163f
HI symbols 260
Homogeneous parts per package 95–96, 96f
hysteresis curves 142–143, 143f

I

I (current source) prefix, PSpice implementation definitions 219, 219t
I/V Source 199
IBIS Translator 231
ideal transmission lines 243–244 See also transmission lines
Implementation 235
Implementation name 235
Implementation name 287, 293
Implementation type 287, 288f, 293
Import Measurement(s) 360, 365
inductance  See also RLCG
transmission lines 243–258
inductors 2, 18, 18f, 132, 219, 219–220t, 311–330, 389–390
concepts 132
definition 132, 141
MPE 311–330
parameters 18
single switch forward converter topology 20f, 311–330
temperature analysis 209–210
voltage source or inductor loop errors 132, 138
inductor thermal resistance 405
initial conditions (ICs) 117, 125, 181
Initialize all flip-flops 264–272, 277–279, 278f
input noise  See also noise
concept 197–200
install path 7–8, 32–33, 235, 327
Instance List 363
Insulation 313–314
insulation materials, transformers 313–314
interface nodes 276–281 See also mixed simulations
intervals, noise analysis 200
inverters 259–273
IO_LEVEL 260
IPWL 120, 121f, 122 See also PWL (piecewise linear), Stimulus Editor
IRF.lib 226
ISWITCH 220t
ITL 118

J

JFET 220t
Johnson noise 197

K

K_Linear coupling devices 141–149 See also transformers

L

L (inductor) prefix, PSpice implementation definitions 219, 219t
Laplace ABMs 189
LEN property 246–247
less than two connections at node errors 132
library 11, 16, 32–33, 157, 231, 325–330
Library Encryption 229–230
Linear sweep 70–72
Linear sweep 60, 65
linear transformers 141–149 See also transformers
LITZ winding 320
Load Bias Point 45
load resistors 83–89
load terminations, transmission lines 247–258
Logarithmic sweep 70–78
Log File 360, 361f
look-up tables, ABMs 185–191
lossy transmission lines 243–247 See also transmission lines
LO symbols 260–261
lot 168
lumped line segment models 243–244, 245f

M

M (MOSFET) prefix, PSpice implementation definitions 219, 219t
Macros 212
magnetic 142
magnetic core models 311–330 See also transformers
Magnetic Parts Database 311–330
Magnetic Parts Editor (MPE) 311–330
bobbin-winding selection MPE step 318–320, 323
component-selection step 312–313
core-selection step 315–318, 321–322
creating a transformer model 325–328
design cycle 311–330
electrical-parameters step 314
errors 321, 321f
results-view step 320–325
testing flyback converters 328–330
Major Grid 67
Major Spacing 67
Make Active 341
Mark Data Points 123–124
Markers 54–67, 86, 328–330, 343
master designs, test benches 331–346
mathematical expressions 
ABMs 185–191
global parameters 79
mathematical functions 186, 187t
MAX 154–155, 169
Max function 371
maximum operating conditions (MOCs) 385–386
Maximum step size 124
Max measurement 353–354
MC Load/Save, Monte Carlo simulations 154
mean value (μ) 380
Measurement Definitions 
list 177, 178f, 178t
Performance Analysis 177–184
Measurement Expression 161, 348
Measurement expression 359–360, 359–360f
Measurement Results 280, 280f
Measurement Results 370–371, 416, 421, 421f
Measurements 177–184, 280, 280f
MHz/mHz confusions, mistakes 71
microphones 83–89
Min 155
Minimum Severity level 273
Minor Grid 67
Mirror 96
Mirror Vertically 96
missing DC path to ground errors 131, 141–142, 333–334, 340, 342
missing PSpice Template 139, 140f
mixed-mode power supplies, templates 19
mixed simulations 275–281
MLSQ engine 377
Model Editor 217–218, 223–231, 363
Model Import Wizard 224–228, 238–239, 325–328
Model parameter values 172–173
Models List 234, 238
Model Text pane 363
Model View 324
modified component values, test benches 331, 336
modified LSQ engine 372
modulus 3 synchronous counters 264–267, 306–310, 307f, 332–346
Monte Carlo 379–383
analysis 348–349, 375, 379
component and model tolerance values 379
distribution curve 380
tolerance value distributions 381
Monte Carlo simulations 168, 379–380
adding tolerance values 168
Collating Functions 154–155, 155f
filter circuits 151
Number of runs 153
Performance Analysis 152
Simulation Settings 152–155, 159f, 160
Monte Carlo/Worst-Case 158, 159f, 171
More Settings 
Monte Carlo simulations 154–155
worst-case analysis 171
Murata inductor 408–411, 408f, 411f
myIRF540 226
myTransistors.lib 228, 235, 237–238, 238f

N

Name and Value 81, 83t
Name of trace to search 161
NAND gates 259–273 See also AND gates
NegTol 363
nested sweeps 53f, 63, 65, 66–67f
Net Alias 31, 60, 60f, 265
NE555 timer 279–281
netlists 218, 229, 235, 290, 331
Netlist/source file 229, 235
Netlist/source file 288, 296
New Column 84, 84f
New Model 223–224, 224f, 240–242
New Page 292, 300
New Project 2–3, 3f, 27
New Property 410–411
New Row 80–81, 81–82f, 255, 255f
New Schematic 292, 300
New Simulation Profile 36, 47–48, 50, 54, 60, 65, 328–330
New Stimulus 104
New Stimulus 104, 104f
Newton-Raphson iteration method 131
NFIB 198, 198–199t
NJF 220t
NOBIAS 41, 49–50
No Connect 260
nodes 54–67, 333, 342
floating node errors 62f, 333, 342
interface nodes 276–281
less than two connections at node errors 132
Markers 54–67
0V node symbol 9, 11–12, 29, 30f
noise current spectral density 200
noise power spectral density 201
noise voltage spectral density 201
non-linear transformers 141–149 See also transformers
normalized line length, transmission lines 243–258
notch filters 70–78
NRB 198, 198–199t
NRC 198, 198–199t
NRE 198, 198–199t
NSIB 198, 198–199t
NSIC 198, 198–199t
NTOT 198, 198–199t
Number of Runs 382, 382f
Number of runs, Monte Carlo simulations 151–153

O

olb files 32–33, 224, 327, 329
open circuit transmission lines 
RL replaced with an open circuit 252–253
SWR 258
Open Demo Designs 20
operational amplifiers (opamps) 15, 92–94, 221, 224–226
Optimizer 367–377
circuit performance 367
circuit specifications 368–377
curve fitting 376–377
goal function 367
measurement expressions 368
optimization engines 367–368
Options 5, 31, 57, 59, 65, 158, 164 See also ABSTOL; CHGTOL; GMIN; ITL.; RELTOL; TNOM; VNTOL
OrCAD 2, 7, 21, 24
OrCAD Capture Marketplace 15
osc125Hz 290, 294, 294f, 296–298, 297–302f, 300–306, 305f
oscillators 117
Output File 41
errors 41
noise analysis 207, 207f
Output File Options 42f, 49f
output noise 198–199 See also noise
Outputs folder 297
Output variable 
Monte Carlo simulations 153
worst-case analysis 168, 171
Output Window 132, 132f

P

Packaging 95–96
PARAM 83–98, 255
Parameter Descriptions 390, 390f
Parameter name 97, 97f
PARAMETERS 70–71
Parameters Selection Component Filter 371
parametric analysis 83–98
Parametric Plotter 349
Parametric Sweep 97, 97f
2N3904 parameterized PSpice model 381, 381f
Part 93, 93f
Part Editor 298–300, 304
Partial Design 332–346 See also test benches
Partial Encryption 230–231
parts 7, 10–12, 16, 31, 31f, 79–98, 304
Part Search 93, 93f
Parts per Package 95–96
passing hierarchical parameters 289, 290f
passive inductor model 18f
passive smoke parameters 387–392
capacitor 391–392
inductor 389–390
resistor 387–389
Password protection 25
Path and filename 293, 293f, 309
PCB footprints 96–98
PC Board Wizard 3
PCB projects 3
PDML parameter 390
Peak Detector 125, 127
peak detector circuits, transient analysis 125–127, 125f, 128f
pen cursors 114
Performance Analysis 
Bandwidth 161
Monte Carlo simulations 152
Period and Duty Cycle 348
phase responses, AC analysis 70–78
Pin Numbers Visible 299
Pin Properties 299, 299f
pins 11, 44, 54–67, 219, 219t, 221–223, 226, 228, 228f, 230–231
PJF 220t
Place 60, 62, 212
Place Net 269
Place Part 8, 10–12, 10–11f, 29, 32–33, 34f, 93, 93f
Place Part menu 33, 33–34f
play button 37
Plot 273
polyethylene terephthalate (PET) capacitor 414
PORTRIGHT-R 286, 286f, 292, 294, 308
PosTol 363
Postscript (PS) 21–22
Postscript to PDF converter (PDD) 21–22
pot 96
potential dividers 59, 61, 292, 292f
potentiometers 17t, 92–98 See also notch filters; resistors
Power 76, 80, 96
Power Derating Factor (PDF) 400, 403
Power Dissipation 83–88, 84f
curves 86
power supplies, hierarchical designs 291, 294
power symbols 80, 83–89
power transformers, MPE 311–330
predefined transformers 144 See also transformers
Pressure sensors 15
primary coils 141–149, 314, 320–321
Primary Sweep 65, 97, 97f
printed circuit boards (PCBs) 3–4, 11–12, 26, 96–98, 96f
probabilities 151–164
probability density function (PDF) 349, 379–380, 380f, 383f
Probe 106, 111, 153–154, 161, 164, 275
Probe 54–57, 59, 59f, 61
Probe Cursor 75, 75f
Probe Window 160
Profile Settings 373–374, 377, 396–397, 412–413
programmable logic arrays 259
Project Manager 6–7, 7f, 328–330
project name 4, 7
propagating velocities, transmission lines 243–258
Properties 57
Property Editor 141–149, 152, 155–157, 163, 359 See also parametric analysis
Property Editor 83–98, 198–199, 401 See also parametric analysis
Property Name=Value 334–335, 334–335f
Propose Part 317, 321
PSpice Advanced Analysis 402, 417
PSpice digital parts 17t
PSpice discrete parts 16, 17t
PSpice Environment Window 39–40
PSpiceFiles 331
PSpice Model 142–143, 217–242
PSpice Model Editor 394, 420
PSpice Modeling Application 18–19
PSpice Model Library 229, 235–238
PSpice models 142–143, 210, 217–242, 311–330
adding 217–242
copying existing models 239
creating 217–242, 311–330
directories 234–237
downloading models from vendors 228–229
edits 217–218, 223–242
encryption 229–230
exercises 231–242
implementation 311–330
Model Editor 217–218, 223–242
Model Import Wizard 224–228, 325–328
MPE 311–330
subcircuits 218, 219t, 221–222, 324, 325f, 327
types 311–330
2N3904 PSpice model parameters 356–357, 357f
PSpiceOnly 331
PSpice Probe waveform 349
PSpice Runtime Settings 133, 133f
PSpice source parts 17t
PSpice Template 218, 221
PULSE 
Attributes 105, 106f, 113
Stimulus Editor 104
PWL (piecewise linear), Stimulus Editor 104

Q

Q (transistor) prefix, PSpice implementation definitions 238
quadratic temperature coefficients 209, 214, 214f
Quick Place of PSpice Components 16–17, 17t

R

R 29, 155
R (resistor) prefix, PSpice implementation definitions 219, 219t
Random number seed, Monte Carlo simulations 154
Rbreak 155–156, 210
RC 244
rectifier, ABMs 193, 193f
REFDES 218–219, 221
Reference 287, 293, 293f
reflected signals 243–258
registers 259–273 See also flip-flops
Regular Expression 334–335, 334–335f
Relative sensitivity 353–354, 361, 362f, 365
Relaxed limit 135
RELTOL 118, 134, 166–167, 172–173, 172–173f
Remove Library 33
Remove Part(s) From Self 333, 333f, 342, 342f
repeats forever  See also IPWL; VPWL
transient analysis 129
Replace Cache 304
resistor body temperature 398–400, 403
resistors 7, 27, 27f, 387–389
Restart At, checkpoints 119
Restart Simulation 119
Restore 214
Results Spreadsheet 320–321, 321f, 324, 324f
results-view MPE step 320–325
Reverse Breakdown 232
rich text format (RTF) 235
RISE_EDGE 169
RLCG lumped line segment models 244, 245f
root mean square (RMS) 197, 200–202, 314
row format Property Editor 80, 81f
RTOL tolerance property 362

S

safe operating limits (SOL) 395
power dissipation 403, 403f
resistor with 404, 404f
Sallen and Key filters 183–184, 184f
Save Bias Point 44–45
Save Check Points 119 See also checkpoints
Save data from, Monte Carlo simulations 154
saved designs 24
Save Symbol 228, 327
Saving a project 23–25
SCHEDULE 118–119, 124
SCHEDULE 118–119
Schematic Editor 224, 225f, 238
Schematic to Schematic utility (SVS) 331
Schematic View 287, 293
Search 64–66f, 333–334, 334f
search commands 179
Search For 93–94f, 94
Search for Parts 12–15, 13f, 60f, 64–66f, 93, 93f
Search Online 15
secondary coils 320–321
Secondary Sweep 65, 214, 215f
Select derating type 397
Select Matching 327
self-heating effect 398
semiconductor PSpice models 394
semiconductors 165
convergence problems 133–134
MOSFETs 198–199t, 226, 238
noise analysis 198
temperature analysis 209
Sensitivity Analysis 351–365
components 352, 352f, 354–357
log file 360, 361f
parameter tolerances 354–357
Worst Case analysis 351, 365
sensitivity analysis 165–167, 174–175, 348–349 See also worst-case analysis
Sensitivity Component Filter 361
Session Log 136
SFFM Attributes 106f
SFFM (single-frequency FM), Stimulus Editor 105–106
Shape 299
short circuit transmission lines 
RL replaced with a short circuit 250–252
SWR 254–257
shot noise 198–199
noise; semiconductors 
sigma (σ) 380
signal power loss 243–258
simple library 6
Simulation Output Variables 76, 212
Simulation Profile Settings 44, 54, 134–138
Simulation Status window 132
SIN Attributes 105f
sinewaves 105, 108f
SIN (sinusoidal) 105, 108f
single switch forward converter topology 20f, 311–330
SIN (sinusoidal), Stimulus Editor 105, 108, 108f
Skip the initial transient bias point calculation 118
small signal response of a circuit 70–78
Smoke analysis 349, 375, 385–423, 386f
Assign Tolerance window 386, 387f
bipolar transistors 393–395
capacitor 391–392
derating files 395–398
inductor 389–390
log file 408, 409f, 410, 411f
maximum operating conditions (MOCs) 385–386
resistor 387–389, 399, 399f
Smoke_Inductor 406
software install path 7–8, 235, 327
SPB 7
Spice voltage-controlled sources 186 See also analog behavioral models (ABMs)
Split Part Section Input spreadsheet 297
spreadsheets 
results-view MPE step 320–325
Split Part Section Input spreadsheet 297
Standard Derating 403
standing wave ratio (SWR) 254–258
open circuit loads 258
short circuit loads 254–257
Start Menu 394
Start saving data after 118
Start value 97, 97f
stationary waves 254–258
statistical analysis, Monte Carlo simulations 151–164
Statistical Information 383
step-down/up transformers 144–148 See also transformers
Stimulus Editor 100–115
stimulus files 100–115
stl files 107, 111
Stop time 117
subcircuits 218, 219t, 221–222, 324, 325f, 327
Subparam 289, 290f, 302
Sweep type 65, 97, 97f
Sweep Variable 54, 60, 65, 97, 97f
SWG wire standard 320
switched-mode power supplies, templates 19
symbols 326–328, 326–328f
Hierarchical Symbols 283–310
Symbol Viewer 15

T

T_ABS 221
TBFiles 331
temperature coefficients (TCs) 39, 209–210, 212f, 214, 214f
temperatures 79
Test Bench 306
test benches 306
comparing/updating master design differences 335–336, 343–346
creating 336
Diff and Merge 343–346
Digital Counter hierarchical design 306
errors 333, 342
modified component values, test benches 331, 336
selection of parts 332–333
unconnected floating nets 333–335
TestBenches folder 337–338
Test_Clock/Test Bench 332–346, 332–333f
Test_Counter 332, 332f, 341–342, 341–342f
Test Osc125Hz 300–301, 302f, 305
Text Editor 235
text files, time–voltage text files 120–122
Text to Search Box 333, 334f, 339, 339f
thermal noise 198–199 See also noise
thermal resistances (RTH) 419–420
Time Domain (Transient) 248, 248f
Time Domain (Transient) 110, 118, 118f, 123, 123f
time steps 117, 122–124, 124f, 247 See also transient analysis
time-voltage data 
Stimulus Editor 107
transient analysis 106, 120–122
timing hazards, digital simulations 262
Timing Mode 262
timing violations, digital simulations 259, 262
Tip for New Users 3
TKNEE 399, 410–411, 410f, 415
Tline distributed models 243–258
TLOSSY PSpice device 246, 246f
TLUMP lumped line segment models 243
T_MEASURED 221
TNOM 221
TOLERANCE property 359
Tolerances 165–175
tolerances 348–349
SPICE model 379
subcircuit parameter 379
top-down designs 283–310 See also Hierarchical Blocks
topologies 19, 311–330
Toroid 315–318
total noise contributions, noise analysis 198–199
Total Points 256, 256f
Total Points 70–72
Trace 74–76
Trace Expressions 264, 376
traces 54–67, 74, 76, 86
transfer functions 
ABMs 185–191
noise analysis 208
transformers 141–149, 311–330
transient 329
transient analysis 36, 45, 79, 118–124, 126–129, 340, 342, 359
transient sweeps 79
transistor-transistor logic (TTL) 259–273
transmission line delay (TD) 243–258
transmission lines 243–258
different load terminations 247–258
ideal transmission lines 243–244
lossy transmission lines 243–247
matched load for RL 247–250
RLCG lumped line segment models 244, 245f
RL replaced with an open circuit 252–253
RL replaced with a short circuit 250–252
SWR 254–258
SWR for open circuit loads 258
SWR for short circuit loads 254–257
types 243–247
T_REL_GLOBAL 221
T_REL_LOCAL 221
TRN 220t
twin T notch filters, AC analysis 70, 70f, 72–78, 73f, 92, 92f
twisted wire pair models 244
txt files 
saved bias point data 44–45, 45f
time–voltage text files 120–122
Type 299, 308

U

UADC 220t
UDAC 220t
UDLY 220t
UEFF 220t
UGATE 220t
UIO 220t
unconnected floating nets, test benches 333–335
Undo Warning 37, 37f
Update Cache 305
Update Schematic 112
Use Device Characteristic Curves 223, 240
Use distribution 153–154
User Defined 66
User Properties 299–300, 299f
Use Template 223, 240–241
UTGATE 220t
UU 315–318

V

V (voltage source) prefix, PSpice implementation definitions 219, 219t
Variables part 355–356, 355f, 416
Variables symbol 362
variance 151–152
VCC_CIRCLE symbol 8–9
VCC_CIRCLE symbol 96
Vendor Name 315–318
Vendor Part 318, 318f
V(INOISE) 199
V(ONOISE) 199
VNTOL 122
voltage-controlled current sources (VCCSs) 185–191 See also analog behavioral models; G device
voltage-controlled voltage sources (VCVSs) 185–191 See also analog behavioral models; E device
voltage pairs, transient analysis 120–122
voltage regulators 221
voltage source or inductor loop errors 132, 138
Vpulse 112
VPWL 104 See also PWL (piecewise linear), Stimulus Editor
VPWL 120–122, 121–122f, 127, 128f, 129
VSIN 145
VSS 260
VSTIM 100–115
VSWITCH 220t

W

warning messages 46, 46f, 56f, 139, 262 See also errors; mistakes
Waveform 54–55, 57, 126–128
websites, downloading models from vendors 228–229
Width 288
wildcards 93–94f, 94
Wire Drag 31
world icon 233
Worst Case All Devices 174–175
worst-case analysis 165–175
Sensitivity Analysis 351, 365
Worst Case Direction 171
Worst Case Summary 175, 175f

X

X Axis 216
XFRM_LINEAR linear transformer 144, 144f
XFRM_NONLINEAR 327, 327f
XGrid 67
X (subcircuit) prefix, PSpice implementation 238

Y

YAxis 66, 115
YGrid 67
YMAX 154–155, 168

Z

zener diodes 231–234, 233–234f
Zetex library 423–424
Z (IGBT) prefix, PSpice implementation definitions 219, 219t
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