List of Figures
2.1 Bus architecture with a separate I/O bus
2.2 Bus architecture for Memory Mapped I/O
2.3 Bus architecture with two PCI buses and one SCSI bus
2.5 The Virtual Memory address translation
2.6 The usage of virtual address translation to avoid memory conflicts
2.7 Sharing data via static variable on systems which do not support Virtual Addresses
2.9 r and è representation of a line
2.10 (r, è) relationship for points (x0, y0) and (x1, y1)
2.11 Circles drawn around points over the circumference intersect in the circle center
2.12 A sample image with a circular shape
2.13 The image of 2.12 after edge detection
2.14 The content of the voting matrix generated from the edge pixels of 2.13
2.15 The detected center in the original image
3.2 Process Interleaving and SystemTiming
3.5 Process State withMultithreading
4.2 A simple resource allocation graph
5.1 Incrementing a shared variable
5.3 Another,more complex race condition
5.4 Problems with lock variables
5.5 Hardware-assisted lock variables
5.6 Peterson’smutual exclusion
5.7 Concurrency in Peterson’s algorithm
5.8 Unbounded priority inversion with busy wait
5.9 Bounded priority inversion with passive wait
5.10 Process State Diagram with Semaphores
5.11 Mutual exclusion semaphore
5.12 Producers–consumerswith semaphores
5.13 Semaphores may be difficult to use
5.14 Race condition after wait/signal
5.15 Brinch Hansen’s semantics for signal
5.16 Hoare’s semantics for signal
5.17 POSIX semantics for signal
5.18 Producers–consumerswith monitors
6.1 Direct versus indirect naming
6.2 Asynchronousmessage transfer
6.3 Synchronousmessage transfer
6.4 Remote invocation message transfer
6.5 Producer–Consumer with synchronous message passing
6.6 Producer–Consumer with asynchronous message passing
7.1 Process and Thread contexts
8.1 Relative vs. absolute delay
9.1 Network frames: Ethernet, IP, and TCP/IP
10.1 Concurrent read and write operations may be dangerous
10.2 An example of concurrent read and write operations
10.3 A lock-free solution to the readers/writer problem
10.4 Basic lock-free transformation of a sequential object
10.5 Race condition with a careless memory management approach, part 1
10.6 Race condition with a careless memory management approach, part 2
10.7 Universal construction of a lock-free object
11.1 Real-time scheduling notation
11.2 An example of cyclic executive
11.3 An example of secondary schedule
11.4 Task split in a cyclic executive
12.1 Scheduling sequence for tasks τ1, τ2, and τ3
12.2 Interference to τm due to higher-priority tasks τi
12.3 Tasks τ1 and τ2 not scheduled under RM
12.4 Situation in which all the instances of τ1 are completed before the next release of τ2
13.1 Upper Bounds and Least Upper Bound for scheduling algorithm A
13.2 Necessary schedulability condition
13.3 No overlap between instances of τ1 and the next release time of τ2
13.4 Overlap between instances of τ1 and the next release time of τ2. 300
13.5 Schedulability conditions for Rate Monotonic
13.6 RM scheduling for a set of tasks with U = 0.900
13.7 RM scheduling for a set of tasks with U =1
13.8 Ulub value versus the number of tasks in the system
13.9 A sample task set where an overflowoccurs
13.10 Utilization based schedulability check for EDF
14.1 Scheduling sequence of the tasks of Table 14.1 and RTA analysis for task τ3
14.2 RM scheduling fails for the tasks of Table 14.3
14.3 DM scheduling succeeds for the tasks of Table 14.3
15.1 Unbounded priority inversion
15.2 Priority Inheritance Protocol
15.4 Transitive Priority Inheritance
15.5 A schedule with unbounded priority inversion
15.6 A schedule with priority inheritance
15.7 A schedule with priority inheritance
16.1 Self-suspension and the critical instant theorem
16.2 Self-suspension and task interaction
17.1 FreeRTOS scheduler-related data structures
17.2 FreeRTOS context switch, part 1
17.3 FreeRTOS context switch, part 2
17.4 FreeRTOS context switch, part 3
17.5 FreeRTOS context switch, part 4
17.7 FreeRTOS context switch on a Cortex-M3
18.1 Data organization of the Linux O(1) scheduler
18.2 Latency due to non-preemptible kernel sections
18.3 The evolution of kernel preemption in Linux
18.5 The Xenomai domains in the Adeos pipeline
20.2 Tank–pump system controlled in feedback mode
20.3 Tank–pump system response when controlled in feedback mode
20.4 Flow request to the pump using feedback control with proportional gain
20.5 Graphical representation of the transfer function for the tank–pump system
20.6 Graphical representation of tank–pump system controlled in feedback
20.7 The module of the transfer function for the tank–pump system. 453
20.8 Zeroes and poles of the transfer function for the tank–pump system
20.11 Sampling a continuous function
20.13 The approximation of a square function considering 1 and 10 harmonics
20.14 The components (amplitude vs. frequency) of the harmonics of the square function
20.15 Representation of a complex number in the re–im plane
20.17 The spectrum of the signal shown in Figure (20.16)
20.18 The signal of Figure 20.16 after low-pass filtering
20.19 The spectrum of the signal shown in Figure 20.18
20.20 Frequency response of an ideal filter with cut-off frequency fc. 469
20.21 Frequency response of the filter used to filter the signal shown in Figure 20.16
20.22 Frequency response shown in Figure 20.21 expressed in decibel. 470
20.24 The Fourier representation of the tank–pump transfer function
20.25 The poles of a Butterworth filter of the third-order
20.29 A frequency spectrum limited to fc/2
20.30 The discrete time Fourier transform corresponding to the continuous one of Figure 20.29