28

Motorola M6800 Microprocessor

Pin description of 6800

Programmer's view of 6800

Addressing modes of 6800

Immediate addressing

Implied or inherent addressing

Direct addressing

Extended addressing

Indexed addressing

Relative addressing

Instruction set of 6800

Data transfer group

Arithmetic group

Logical group

Branch group

Miscellaneous instructions

Interrupts of 6800

Programming examples

Addition of multi-byte numbers

Exchange of blocks

Block movement without overlap

Questions

In the previous chapters Intel 8085 and Zilog Z-80 microprocessors were dealt with in depth. In this chapter Motorola M6800, another very popular 8-bit microprocessor will be discussed. This will provide the reader with a comparison of the most popular 8-bit microprocessors.

28.1 PIN DESCRIPTION OF 6800

Motorola 6800 is another popular 8-bit microprocessor, with which, the following chips are normally used to provide the required functions in a microcomputer.

• —6870 Clock generator;
• —6830 ROM or 68708 EPROM;
• —6810 RAM;
• —6820 Peripheral interface adapter (similar to 8255 PPI in 8085 system);
• —6850 Asynchronous communications interface adapter (similar to 8251 USART);
• —6828 Priotity interrupt controller (similar to 8259 PIC).

The 6800 is available as a 40-pin DIP and its actual pin diagram is shown in Fig. 28.1. The functional pin diagram is shown in Fig. 28.2.

Fig. 28.1 pin diagram of 6800

Fig. 28.2 Functional pin diagram of 6800

28.2 PROGRAMMER's VIEW OF 6800

From a programmer's point of view the 6800 is a very simple microprocessor. The programmer's view is indicated in Fig. 28.3a. The simplified internal architecture of 6800 is provided in Fig. 28.3b.

From a programmer's viewpoint the 6800 has:

• Two 8-bit accumulators—A and B;
• Three 16-bit address registers—IX, SP and PC;
• Eight-bit flags register—CCR.

IX register is used as index register. It is shown as X in an instruction mnemonic.

SP is the stack pointer. It is shown as S in an instruction mnemonic.

PC is the program counter.

Fig. 28.3a Programmer's view of 6800

Fig. 28.3b Simplified architecture of 6800

Both A and B registers have almost the same prominence in the instruction set. This was not the case with 8085 where A register was more important than other 8-bit registers. In 6800 there are only a few operations that can be done with A, but not by B. The following list shows the exceptions.

Flags register: The flags register in 6800 is termed CCR that stands for condition code register. The flags register contents are indicated in the following. It contains only six flags in the LS position, of which five are status flags and the remaining one is a control flag. The other two bits in the MS bit positions of the CCR are always in the 1 state.

The status flags are affected based on the result of execution of an instruction. The five status flags are:

Note that the P flag of 8085 is omitted here, as it is not a useful flag.

The control flag in CCR is the IM flag. IM stands for interrupt mask. If this flag is set to 1, then IRQ* interrupt will be masked or disabled. It implies that, the 6800 will not be interrupted even if the IRQ* pin is activated by a peripheral. If reset to 0, the IRQ* interrupt will be unmasked or enabled. That is, if the IRQ* pin is activated by a peripheral, the 6800 will be interrupted, provided of course, the higher priority NMI* is not active at the same time.

The IM bit is reset to 0 by the execution of the instruction CLI that stands for CLear Interrupt mask bit. The CLI instruction is functionally the same as the EI instruction of 8085. The IM bit is set to 1 by the execution of the instruction SEI that stands for SEt Interrupt mask bit. The SEI instruction is functionally the same as the DI instruction of 8085. The CCR register is indicated as P in an instruction mnemonic for brevity. For example, the mnemonic TAP stands for transfer from A register to P (CCR) register.

28.3 ADDRESSING MODES OF 6800

There are six addressing modes in 6800. They are:

The following conventions are used in the assembly language programming of 6800.

28.3.1 IMMEDIATE ADDRESSING

In this addressing, the data to be used in the execution of the instruction is provided in the instruction itself, immediately after the opcode of the instruction. Some examples follow.

28.3.2 IMPLIED OR INHERENT ADDRESSING

If the operands used in the instruction are within the 6800, the addressing mode is called implied or inherent addressing mode in 6800 terminology. Thus in this addressing mode, the operands will not be in memory. Some examples follow.

28.3.3 DIRECT ADDRESSING

In this mode the operand will be in memory. This mode is sometimes called page 0 addressing because the operand in memory is restricted to be in the address range of 0000H to 00FFH that happens to be page 0 of memory. Memory in 6800 system can be thought of as made up of pages of size 100H = 256 bytes. Some examples follow.

Direct addressing is a very powerful addressing mode provided by 6800. This was not present in 8085 or Z-80. Instructions that use direct addressing will be only 2-byte long compared to the 3-byte length of instructions that use extended addressing. As such, direct addressing instruction occupies less space in memory. And more importantly, it takes less time to fetch and execute an instruction that uses direct addressing.

In a 6800 system it is advantageous to have the frequently accessed data stored in the memory range 0000H–00FFH. The data can hence be accessed very fast using direct addressing. To facilitate this, RAM generally starts from location 0000H and grows towards higher addresses in the memory space of 6800. ROM or EPROM is provided the last part of the memory space, and ends with the address FFFFH. This is shown in Fig. 28.4.

Fig. 28.4 Memory Space In 6800

28.3.4 EXTENDED ADDRESSING

It is the same as the absolute addressing of 8085. However, it is much more powerful here. In this mode the operand will be in memory. The address of the operand is provided after the opcode in the instruction using 16 bits. Because of the 16-bit address, the operand could be anywhere in the memory space in the range 0000H to FFFFH. Some examples follow.

It may be noted that none of these instructions were present in the absolute addressing mode of 8085. This demonstrates the power of extended addressing in 6800.

If the user writes in assembly language an instruction like COM $0056, the 6800 assembler automatically generates a 2-byte instruction code treating the instruction as COM $56 in direct addressing mode. As such, the practical addressing range for extended addressing could be indicated as 0100H to FFFFH.

28.3.5 INDEXED ADDRESSING

In this mode the operand will be in memory. A part of the address is provided in the IX register and the other part of size 8 bits is provided directly in the instruction. The sum of these two parts provides the complete memory address for the operand. This mode is already described in Z-80. However, in 6800 there is a single IX register compared to the two present in Z-80. Some examples follow. In these instructions, the IX content is assumed to be 1234H.

28.3.6 RELATIVE ADDRESSING

The relative addressing mode is used in the branch group of instructions. The branch group of instructions that use relative addressing will be only 2-byte long and will be executed faster compared to those that use extended addressing. In relative addressing, a signed 8-bit number will follow the opcode byte. This number indicates whether the branch is to a forward location or to a backward location. The range for branching is 127 locations forward or 128 locations backward from the next instruction. This mode is already described in Z-80. Some examples follow.

28.4 INSTRUCTION SET OF 6800

Some statistics about the instruction set of 6800 are shown in the following.

• Instruction types: 72;
• Number of opcodes: 197;
• Instruction length: 1, 2, or 3 bytes.

Although 6800 has only 197 opcodes compared to the 246 of 8085, it is more powerful than 8085. Its branch group of instructions are more powerful than even Z-80 with about 700 opcodes. The instruction set of 6800 is easy to master considering its simplicity. The power of 6800 instruction set will be demonstrated by some programming examples later. The instructions of 6800 could be classified under the following groups.

The following convention is used in the description of the instruction set of 6800.

28.4.1 DATA TRANSFER GROUP

There are 38 opcodes in this group under 14 instruction types.

28.4.2 ARITHMETIC GROUP

There are 55 opcodes in this group under 15 instruction types.

28.4.3 LOGICAL GROUP

There are 73 opcodes in this group under 14 instruction types.

28.4.4 BRANCH GROUP

There are 23 opcodes in this group under 21 instruction types. The conditional branch instructions of even Z-80 performed branch based on the value of a single flag, except V flag. For example, ‘JR NC, r8’ of Z-80 performed a branch only if Cy flag were 0. In 6800, conditional branch instructions that test V flag are also provided. They are very useful when working with signed numbers and are shown as follows:

In addition, there are conditional branch instructions that test more than one flag also in 6800. Such instructions are useful in the comparison of two unsigned or two signed numbers.

In 6800 terminology, ‘higher’ and ‘lower’ are used when comparing unsigned numbers. ‘Greater than’ and ‘less than’ are used when comparing signed numbers. Consider the numbers 85H and 45H as an example. 85H is a negative number (as the MS bit is 1) and 45H is a positive number (as the MS bit is 0) when interpreted as signed numbers. Thus, all the following statements are perfectly true in 6800 terminology.

BHI (branch if higher) and BLS (branch if lower or same) are used with unsigned numbers. BHI and BLS are generally used after a compare operation like ‘CMP B, #$25’. These instructions perform a branch based on the value of Cy flag and Z flag.

BGT (branch if greater than), BGE (branch if greater or equal), BLT (branch if less than) and BLE (branch if less than or equal) are used with signed numbers. They are generally used after a compare operation like ‘CMP B, #$25’. These instructions perform a branch based on the value of sign flag, V flag, and Z flag.

The other instructions under the branch group are:

Note that there are no conditional branches to a subroutine and conditional returns from a subroutine. They are not implemented, as it is possible to manage without such instructions. If it is required to branch to subroutine at symbolic memory location SUBR only if Cy flag is 0, it is managed as follows.

BCS NEXT

BSR SUBR

NEXT: next instruction

If it is required to return from subroutine only if V flag is 0, it is managed as follows.

BVS SKIP

RTS

SKIP: next instruction

28.4.5 MISCELLANEOUS INSTRUCTIONS

There are eight opcodes in this group under eight instruction types.

WAI (wait for interrupt) is functionally the same as the HLT instruction of 8085. There are instructions to clear or set the Cy, IM, and V flags. CLC stands for clear carry, SEC stands for set carry and so on.

6800 instruction set summary

Speed of instruction execution: The typical clock frequency used in 6800 is 1 MHz. The one used in 8085 is 3 MHz. This gives a wrong impression that 8085 is three times faster than 6800. A simple example is provided to prove it to be a wrong impression.

Consider the execution of the 6800 instruction ‘LDA A, #$F3’. Its equivalent in 8085 is ‘MVI A, F3H’. In 8085 this instruction takes a total of seven clock cycles for the opcode fetch, decode and execute portion. It works out to 2.33μs if the 8085 is operating at 3 MHz. In 6800 this instruction takes a total of two clock cycles only—one for fetching and decoding, and the other for execution. It works out to 2 μs if the 6800 is operating at 1MHz. Thus 6800 working at 1 MHz is slightly faster than 8085 processor working at 3MHz.

28.5 INTERRUPTS OF 6800

There are two hardware interrupt pins in 6800 which are NMI* and IRQ*. These are active low interrupt input pins of which NMI* is non maskable. Thus the 6800 gets interrupted whenever the NMI* pin is activated. IRQ* is maskable. It is masked or disabled if the IM flag of CCR register is set to 1 using the SEI instruction. It is also automatically masked whenever the 6800 enters an ISS. In such a case, the 6800 is not interrupted even if the IRQ* pin is activated.

IRQ* is unmasked or enabled if the IM flag of CCR register is reset to 0 using the CLI instruction. In such a case, whenever the IRQ* pin is activated, the 6800 is interrupted, provided NMI* is not active at the same time. This is because, NMI* has a higher priority over IRQ*. When NMI* pin is activated half way through an instruction, the action performed by 6800 is as follows:

If the contents of locations FFFCH and FFFDH are 56H and 78H as shown in Fig. 28.5, then the NMI* ISS starts from 5678H and ends with RTI instruction. The execution of this instruction results in the following.

Fig. 28.5 Interrupt vectors of 6800 and saving of registers on the stack

As there is no explicit need for saving and restoring registers in the ISS, the interrupt response is much faster than in 8085. In the ISS of 8085, the user had to explicitly save and restore the registers in the ISS, thereby slowing down the interrupt response.

When IRQ* pin is activated half way through an instruction, the action performed by 6800 is very much similar to the activation of NMI*. In this case the 6800 jumps to the ISS whose address is provided in locations FFF8H and FFF9H. If the contents of locations FFF8H and FFF9H are 9AH and BCH as shown in Fig. 28.5, then the IRQ* ISS starts from 9ABCH and the ISS ends with RTI instruction.

In addition to the two hardware interrupts, there is also an SWI (software interrupt) in 6800. This instruction has the mnemonic SWI. When this instruction is executed by the 6800 in a program, the action taken is as follows.

If the contents of locations FFFAH and FFFBH are 22H and 33H as shown in Fig. 28.5, then the ISS for SWI instruction starts from 2233H and it ends with RTI instruction.

The activation of Reset* pin also interrupts the working of 6800. The 6800 always responds to activation of Reset* signal in the following way.

If the contents of locations FFFEH and FFFFH are E0H and 00H as shown in Fig. 28.5, then the jump takes place to E000H. At this location the system initialization program begins.

PROGRAMMING EXAMPLES

28.6.1 ADDITION OF MULTI-BYTE NUMBERS

Write a 6800 assembly language program to add two multi-byte numbers. The size in bytes of the two multi-byte numbers is provided in location 8910H. The first multi-byte number starts from location 8920H with the LS byte and the second one from location 8940H with the LS byte. The result is to be stored from location 8970H starting with the LS byte. For the result, one extra location is provided to account for the carry generated.

A typical input and the expected output are indicated in Fig. 28.6.

Fig. 28.6 Addition of two multi-byte numbers

Program
CLC
                         LDX #$8920
AGAIN: LDA A $0, X
       ADC A $20, X
       STA A $50, X!

       INX
       DEC $8910
       BNE AGAIN

       CLR $50, X
       BCC EXIT
       INC $50, X
EXIT: WAI

The reader is urged to compare this program with the one in Section 14.2 that used 8085 processor. A shortage of registers was felt while using 8085 processor. The number of registers in 6800 is much less than in 8085. In spite of this, in the above program, register B of 6800 is still available for use. This is because, the usage of indexed addressing in 6800 has resulted in a more compact program, which amply demonstrates the power of indexed addressing mode.

28.6.2 EXCHANGE OF BLOCKS

Write a 6800 assembly language program to exchange contents of two blocks in memory. The number of elements in the block is provided in location 8910H. The two blocks start at locations 8920H and 8940H, respectively.

Typical memory contents before and after program execution are indicated in Fig. 28.7.

Fig. 28.7 Exchange of blocks

Program
LDX #$8920
                REPEAT: LDA A 0, X
                         LDA B $20, X

                         STA A $20, X
                         STA B 0, X

                         INX
                         DEC $8910
                         BNE REPEAT

                         WAI

The reader is urged to compare this program with the one in Sect. 14.1 that used 8085 processor. The usage of indexed addressing in 6800 has resulted in a more compact program, which once again demonstrates the power of indexed addressing mode.

28.6.3 BLOCK MOVEMENT WITHOUT OVERLAP

Write a 6800 assembly language program to perform block movement. The blocks are assumed to be non overlapping. The block starting at location 8920H is to be moved to the block starting at location 8940H. The block size is provided in location 8910H.

Typical memory contents before and after program execution are indicated in Fig. 28.8.

Fig. 28.8 BLOCK MOVEMENT

Program

LDX #$8920
                AGAIN:   LDA A 0, X
                         STA A $20, X

                         INX
                         DEC $8910
                         BNE AGAI
                         WAI

The reader is urged to compare this program with the one in Sect. 14.4 that used 8085 processor. Once again, the use of indexed addressing in 6800 has resulted in a more compact program.

1. With a neat functional pin diagram, explain the pins of 6800.
2. With a neat diagram describe the programmer's view of 6800.
3. Explain the flags available in 6800.
4. Write a note on the addressing modes of 6800 with an example for each addressing mode.
5. List the various instruction types available in the data transfer group of instructions.
6. List the various instruction types available in the arithmetic group of instructions.
7. List the various instruction types available in the logical group of instructions.
8. Write a note on the branch group of instructions.
9. Comment on the speed of execution of instructions in 6800 and 8085.
10. Write a note on the interrupts of 6800.
11. Describe the internal architecture of 6800 with a neat diagram.