Real-Time Hardware and Systems Design Considerations
In general, vision involves huge amounts of computation, as images are two-dimensional and in real-time applications are liable to be delivered at rates of 10 to 20 per second. Although humans can easily cope with these data rates, they are often beyond the processing capabilities of conventional computers. This chapter explores the situation and demonstrates how, using special computational hardware, the processing problems can be addressed and alleviated.
• how parallel processing can radically improve the speeds at which vision algorithms run.
• the concept of an SIMD (single instruction stream, multiple data stream) computer, with one processor per pixel in a 2-D array.
• Flynn’s classification of sequential and parallel computers.
• how a vision algorithm may optimally be partitioned between hardware and software.
• modern real-time hardware options.
• the increasingly important status of the FPGA (field-programmable logic array) in realtime hardware design.
• vision systems design considerations and the optimization process.
Much of this volume has been devoted to the systematic design of vision algorithms and of necessity has tended to focus on a large variety of subproblems such as edge detection. However, when embarking upon design of a complete vision system, the situation is much less “clean,” and indeed is subject to myriad financial and marketing constraints, as well as fiercely nonideal data. In this context, vision system design is as much an art as a science and is more subject to cyclic improvement than in an ideal world—as the last few sections of this chapter have attempted to indicate. Suffice it to say here that the situation must be viewed realistically with an eye to improvement.