Index

4-bit Microprocessors 4

8-bit Microprocessors 4

16-bit Microprocessors 4

32-bit Microprocessors 5

74138 Decoder IC 120

advantage of multiple chip select lines 122

use of 74138 to generate chip select logic 121

8051 Microcontroller 546

8255 Programmable Peripheral Interface Chip 323

architecture of 8255 325

interface with Microprocessor 326

interface with I/O Devices 327

pin diagram of 8255 324

port selection of 8255 325

A

Addressing of I/O ports 125

comparison of I/O port chips and memory chips 126

comparison of memory-mapped I/O and I/O-mapped I/O 129

IN and OUT instructions 127

I/O-mapped I/O 129

memory-mapped I/O 128

need for I/O Ports 125

Addressing modes of 6800 533

Direct addressing 534

Extended addressing 535

Immediate addressing 534

Implied or inherent addressing 534

Indexed addressing 535

Page 0 addressing 534

Relative addressing 536

Addressing modes of 8051 557

advantage of SFR 559

direct addressing 558

immediate addressing 558

implied addressing 560

indexed addressing 559

register addressing 558

register indirect addressing 559

Addressing modes of 8085 59

absolute addressing mode 61

immediate addressing mode 61

implied addressing mode 61

instruction type LDAX rp 62

instruction type STAX rp 62

instruction type LHLD a16 63

instruction type SHLD a16 63

need for addressing mode 60

Register addressing mode 61

Register codes 59

Register indirect addressing mode 61

Addressing modes of Z-80 499

bit addressing 505

bit SET instruction 505

bit RES instruction 505

bit instruction 506

flags registers F 502

indexed addressing 504

opcode size for Z-80 instructions 503

overflow flag 502

relative Addressing 500

ALS-SDA-85M Kit 122

Application of 8212 315

Application of 8212 in mode 0 315

as supplier of eight RST instructions 318

bi-directional bus driver 315

Intel 8212 as gated buffer 315

interrupting input port and

Rst n interrupt instruction port 316

Application of 8212 in mode 1 321

Intel 8212 as low-order address latch 321

Intel 8212 as an interrupting output port 321

Arithmetic Group of Instructions 65

Architecture of 8259 439

Architecture of 8085 133

address/data buffers 138

Address latch enable signal (ALE) 136

Arithmetic Logic Unit (ALU) 134

Connection of register to the internal bus 139

control signal RD*, WR*, and INTA* 136

incrementer/decrementer 139

internal address latch 139

instruction Register (IR) 138

multiplexer/demultiplexer 138

ready input pin 137

Status Signals IO/M*, S1 and S0 136

Temporary (Temp) Register 138

timing and control unit 134

W and Z registers 138

X1,X2, and Clk out pins 134

Asynchronous Reception 481

Asynchronous Transmission 478

number of bits per character 479

number of clocks for transmitting or receiving a bit 480

parity bit 479

start and stop Bits 480

B

Branch group of instructions 99

IR-Instruction register 101

PC-Program counter 101

W and Z registers 101

C

Chip selection 117

RAM chip-pin details and address range 118

Classification of 8085 instructions 53

Conditional Call Instructions 109

CC a16—Call if carry 110

CM a16—Call if Minus 111

CNC a16—Call if not carry 109

CNZ a16—Call if not zero result 110

CP a16—Call if Positive 110

CPE a16—Call if parity Even 110

CPO a16—Call if parity Odd 110

CZ a16—Call if Zero result 110

Conditional jump instructions 104

call instruction 107

difference between call and jump instructions 107

JC a16—Jump if carry 105

JM a16—Jump if Minus 107

JNC a16—Jump if not carry 104

JNZ a16—Jump if not zero Result 105

JPE a16—Jump if Parity Even 106

JP a16—Jump if Positive 106

JPO a16—Jump if Parity Odd 106

JZ a16—Jump if Zero result 106

RET instruction 107

Conditional Return Instructions 111

RC—Return if carry 112

RM—Return if minus 113

RNC—Return if not carry 111

RNZ—Return if not zero result 112

RPO—Return if party odd 112

RPE—Return if party even 113

RP—Return if positive 113

RSTn—Restart Instruction 113

RZ—Return if zero result 112

Control Port of 8255 328

Interrupt-driven Bi-Directional operation 341

Interrupt-driven input operation 333

Interrupt-driven output operation 335

Interrupt-driven and Status check data transfers 332

Mode 1 – Strobed I/O 331

Mode 2 – bi-directional I/O 340

Mode Definition Control Word 329

Port C bit set/reset control word 330

Status check bi-directional operation 342

Status check input operation 338

Status check output operation 339

D

Data memory structure 551

8051 stack 553

internal data memory organization 552

internal RAM organization 552

programmer's view of 8051 556

PSW register 555

SFR Area 554

Data Transfer group of instructions 52 53

Instruction type LDA a16 57

Instruction type LXI rp, d16 56

Instruction type MOV r1, r2 54

Instruction type MOV r, M 55

Instruction type MOV M, r 56

Instruction type MVI M, d8 57

Instruction type STA a16 58

Instruction type MVI r, d8 54

Instruction type XCHG 58

Number of instructions in 8085 53

Data transfer schemes 278

about 8085 Interrupts 283

action taken by 8085 when INTR pin is activated 288

action taken when 8085 is interrupted due to a vector interrupt 295

basic or simple data transfer 278

EI and DI instructions 285

execution of ‘DAD rp’ Instruction 296

handshake data transfer 281

Interrupt- driven data transfer 282

Intr and IntA* Pins 288

Rest-IN* and Reset-Out pins 285

Rst5.5 and Rst6.5 Pins 291

Rst7.5 Pin 292

Status check data transfer 279

Trap Interrupt Pin 293

Decimal addition in 8085 75

BCD numbers 75

DAA instruction 75

Description of 8085 Pins 29

A_15-8 Pins 31

AD_7-0 Pins 30

ALE Pin 33

IO/M* Pin 33

RD* and WR* Pins 31

V_CC and V_SS Pins 30

Description of Matrix keyboard interface 383

program to display scancode of key pressed 382

F

Flags register 66

auxiliary carry flag (AC) 68

instruction type ADI d8 68

instruction type ACI d8 70

instruction type ADC R 69

instruction type INR R 69

parity flag (P) 68

sign flag (S) 68

zero flag 68

Functional blocks of Intel 8051 548

Program Memory Structure 550

G

Generation of .HEX file using a Linker 197

command mode 198

data file mode 198

downloading the machine code to the kit 199

prompt mode 197

running the downloaded program on the kit 201

Generation of .OBJ file using a cross-assembler 195

translation in command mode 197

translation in prompt mode 196

I

Instruction cycle 140

Comparison of different machine cycles 152

I/O Write (IOW) machine cycle 150

I/O Read (IOR) machine cycle 151

Memory Read (MR) machine cycle 144

Memory Write (MW) machine cycle 146

Opcode Fetch (OF) machine cycle 142

Instructions to Perform Addition 66

Instruction type ADD R 66

Instructions to perform ‘AND’ operation 78

Instruction type ANA R 78

Instruction type ANI d₈ 79

Instructions to perform compare operation 83

Instruction type CMP R 83

Instruction type CPI d₈ 84

Instructions to perform ‘Exclusive OR’ operation 80

Instruction to complement accumulator 82

Instruction type CMC 82

Instruction type STC, 82

Instruction type XRA R 81

Instruction type XRI d₈ 81

Instructions to perform ‘OR’ operation 79

Instruction type ORA R 80

Instruction type ORI d₈ 80

Instructions to perform subtraction 70

Instruction type SUB R 70

Instruction type SUI d₈ 71

Instruction type DCR R 72

Instruction type SBB R 72

Instruction type SBI d₈ 73

Instruction type DCX rp 74

Instruction type DAD rp 74

Instruction type INX rp 73

Instruction to rotate accumulator 85

Instruction type RLC 85

Instruction type RAL 86

Instruction type RRC 86

Instruction type RAR 87

Instruction set of 6800 536

6800 instructions set summary 540

arithmetic group 537

branch group 538

data transfer group 537

interrupts of 6800 540

logical group 538

miscellaneous instructions 539

Instruction set of 8051 560

arithmetic group 562

bit-processing group 564

data transfer group 560

logical group 563

program branch group 566

Intel 8251A–Universal Synchronous AsynchroNous Receiver Transmitter (USART) 477

Intel 8253–Programmable Interval Timer 461

Control port 464

Description of 8253 timer 462

Internal architecture of a counter 465

Mode 0—interrupt on terminal count 467

Mode 1—re-triggerable mono-stable multi 468

Mode 2—Rate generator 469

Mode 3—Square Wave generator 471

Mode 4—Software-triggered strobe 472

Mode 5—Hardware-triggered strobe 473

Programming the 8253 463

Read on the fly 465

Use of 8253 IN ALS-SDA-85 kit 475

Intel 8257—Programmable DMA Controller 442

Concept of Direct Memory Access (DMA) 442

Description of 8257 DMA Controller chip 444

Need for DMA Data Transfer 443

Intel 8259 A–Programmable Interrupt Controller 416

Interrupt mask register 423

Interrupt request register 423

in-service register 423

need for an interrupt controller 417

overview of the working of 8259 419

pins of 8259 421

registers used in 8259 422

slave register 424

Intel 8279 Keyboard and Display Controller 384

clear Command 400

decoded mode of operation 389

display write inhibit/blanking command 401

end interrupt/error mode set command 402

encoded mode of operation 392

keyboard/display mode set command 399

keyboard interface considerations 388

Interfacing matrix of switch sensors 393

interface strabed input port 394

LED connection details on the ALS kit 394

left entry mode of display 398

pins of 8279 387

program clock command 391

N-key rollover mode 391

status register 390

two-key lockout mode 390

read from display RAM Command 396

read from FIFO/sensor RAM Command 393

right entry mode of display 399

write to display RAM Command 395

Interfacing 7-Segment Display 370

display interface using serial transfer 374

implementation of moving display 375

Interfacing a matrix keyboard 380

Interfacing a simple keyboard 377

Interrupts in 8085 277

Interrupt structure in Z-80 519

int* Interrupt 519

interrupt mode 0 (IM 0) 519

interrupt mode 1 (IM 1) 520

interrupt mode 2 (IM 2) 521

NMT* Interrupt 522

Interrupt structure of 8051 575

external interrupts 576

IE (Interrupt Enable) Register 575

IP (Interrupt Priority) Register 576

interrupt handing in 8051 578

serial port interrupt 578

timer interrupts 577

L

Logical group of instructions 77

M

Main features of intel 8051 547

Main memory 9

Random access memory (RAM) 9

Sequential access 9

Random access 10

Memory speed requirement 153

27128-20 Compatibility check with 8085AH 158

assessing compatibility of 27128-20 with 8085AH-2 159

earliest data output time considering t_ACC 156

earliest data output time considering t_CE 158

earliest data output time considering t_OE 158

wait state generation 160

Microcontrollers and Digital Signal Processors 5

Input devices 8

Output devices 8

Microprocessor Kit 41

Functions performed by a microprocessor kit 41

changing the contents of a memory location 45

Checking contents of a memory location 45

entering the data 48

entering the program 46

executing the program in single step mode 49

Major components of a kit 41

Major components of ALS-SDA-85m kit 41

Opcode of an Instruction Mnemonic 42

Sign-on message 45

Motorola M6800 Microprocessor 529

pin description of 6800 530

programmer's view of 6800 531

Multiple memory address range 119

O

Operational modes of 8255 327

bi-directional handshake I/O 328

Mode 0 327

Mode 1 327

Simple I/O or basic I/O 327

Strobed I/O or handshake I/O 327

P

Power saving modes of 8051 595

Power down mode 596

Programming examples 524 542 568

additional of multi-byte numbers 524 542

BCD to binary conversion 569

Binary to BCD conversion 569

bit manipulation program 571

block movement without overlap 526 544

exchange of blocks 525 543

instruction set summary 527

conversion of four-digit Hex to ASCII 572

hex to ASCII conversion 571

shift a multi-byte BCD number to the right 569

Programming of EPROM in 8751 BH 597

EPROM security 598

Erasure of EPROM 600

Program verification 599

Programming the 8251 488

command instruction 490

identifying the command in the control port 490

mode instruction 488

status port of 8251 491

use of sod pin of 8085 for serial transfer 492

Programming the 8257 446

address registers 446

Auto load 450

block chaining operation 451

cycle stealing data transfer 457

control register (mode set register) of 8257 449

count registers 448

description of the pins of 8257 452

enabling/disabling of DMA channels 449

extended write 450

first/last flip-flop 447

long-burst mode 457

repeat block operation 450

rotating priority 449

short-burst mode 457

single-byte transfer 456

state diagram of 8085 457

status register of 8257 451

stop on terminal count (TCS bit) 450

Working of the 8257 DMA Controller 456

Programming the 8259 with slaves 436

buffered mode of 8259 437

fully nested mode 438

Initialization Command Word 3 (ICW3) 436

Initialization Command Word 4 (ICW4) 437

special fully nested mode of 8259 437

use of 8259 in an 8086-based system 439

Programming the 8259 with no slaves 424

Initialization Command Word 1 (ICW1) 425

Initialization Command Word 2 (ICW2) 425

Initialization Command Word 3 (ICW3) 428

Initialization Command Word 4 (ICW4) 429

Operation Command Word 1 (OCW1) 430

Operation Command Word 2 (OCW2) 430

Operation Command Word 3 (OCW3) 434

polled mode 434

read status of IRR or ISR 435

Special Marked Mode (SMM) 435

Program using 8279 402

ADRDISP Routine 406

BLANK Routine 407

DATDISP Routine 406

Display characters on the kit 408

DISPLAY routine 403

Display scan code of key 408

KBD_RD routine 403

Program to Alternately display and blank 412

Program to blank display 407

Program to change the contents of a memory location 409

Program to check for the availability of display 413

Use of ADRDISP Routine in a program 409

Use of BLANK Routine in a program 409

Use of DATDISP Routine in a program 408

XPAND Routine 405

Program using interface modules 344

decimal counter using logic controller 348

Digital to Analog converter interface 359

Dual slope ADC interface 356

Evaluation of Boolean Expression 346

Generation of rectangular wave using DAC interface 361

Generation of Triangular Wave using DAC interface 362

Logic Controller Interface 344

Simulation of 4-bit ALU 349

Simulation of 8 to 1 multiplexer 351

Stepper Motor Interface 363

Successive Approximation ADC interface 353

Programs using interrupts 302

clear monitor routine 309

Find square of a number using look up table 305

GTHEX monitor routine 308

HXDSP monitor routine 310

Program for adding 2 number input from keyboard 308

Program for adding 4 hex digits of a 16-bit number 309

Program for Decimal Down Counter 306

Program for simulation of throwing a die 302

Program for simulating a stopwatch 303

Programmer's View of 8085 34

Accumulator or Register A 35

Registers B,C,D,E,H and L 36

R

Read Only Memory (ROM) 10

Arithmetic Logic Unit (ALU) 11

Assembly Language Program 14

Central Processing Unit (CPU) 11

EPROM 10

EEPROM or EAPROM 11

High-Level Language Program 15

Input and Output Ports 11

Machine Language Program 13

Mask-Programmed ROM 10

Microcontroller 13

Secondary memory 11

PROM 10

Running the program using the PC as a terminal 201

Add contents of N word locations 266

Bubble sort in ascending/descending order as per choice 259

Check for ‘2 out of 5’ code 212

Check for palindrome 228

Compute the HCF of two 8-bit numbers 210

Compute the LCM of two 8-bit numbers 230

Continuing with single step after checking registers/memory 203

Convert 16-bit binary to BCD 250

Convert ASCII to binary 214

Convert binary to ASCII 216

Convert BCD to binary 218

Convert binary to BCD 221

Display alternately 00 and FF in the data field 241

Display memory command 203

Do an operation on two numbers based on the value of X 252

Do an operation on two BCD numbers based on the value of X 255

Examine registers command 203

Find the smallest number 208

Generation of time delay 239

Multiply two 2-digit BCD numbers 270

Multiply two 16-bit binary numbers 272

Multiply two 8-bit numbers (shift and add method) 268

Running the entire program in a single operation 202

Running the program in single-step mode 202

Search for a number using linear search 206

Selection sort in ascending/descending order as per choice 263

Simulate decimal up counter 237

Simulate decimal down counter 240

Simulate a real-time clock 243

Sort numbers using bubble sort 233

Sort numbers using selection sort 235

Subtract multi-byte BCD numbers 248

S

Serial Interface 584

Architecture of 8051 589

Mode 0 of UART 584

Mode 1 of UART 587

Mode 2 of UART 588

Mode 3 of UART 588

Use of Mode 0 to expand I/O Port capability 585

Signed Binary Integers 18

1's complement notation 20

2's complement fraction 24

2's complement notation 21

sign magnitude notation 18

SIM and RIM instructions 297

HLT instruction 302

Interrupt enable status 300

Mask status of interrupts 300

Need for Masking 297

Pending interrupt status 301

Reset RST7.5 flip-flop 298

SIM Instruction 297

Serial input of data and SID pin 301

Serial output of data and SOD pin 299

Simple assembly language programs 165

add N numbers of size 8 bits 178

add two multi-byte BCD numbers 171

add two multi-byte numbers 169

block movement with overlap 175

block movement without overlap 174

check the fourth bit of a byte 181

divide a 16-bit number by an 8-bit number 187

exchange 10 bytes 165

monitor routines 180

multiply two numbers of size 8 bits 184

subtract two multi-byte numbers 182

UPDDT routine 189

UPDAD routine 180

Special instruction types 506

CPD instruction 509

CPDR instruction 510

CPI instruction 509

CPIR instruction 509

DAA instruction 506

LDD instruction 508

LDDR instruction 508

LDI instruction 507

LDIR instruction 507

IND instruction 511

INDR instruction 511

INI instruction 510

INIR instruction 511

IN reg, (C) instruction 510

OTDR instruction 512

OTIR instruction 512

OUT (C), reg instruction 511

OUTD instruction 512

OUTI instruction 512

Pins of Z-80 517

RLD and RRD instructions 513

RLD instruction 514

Rotate and shift instructions 513

RRD instruction 514

SRA instruction 514

SRL instruction 515

Stack and the stack pointer 90

instruction type DAD sp 96

instruction type DCX sp 96

instruction type INX sp 95

instruction type LXI, sp, d16 94

instruction type NOP 96

instruction type POP rp 92

instruction type PUSH rp 93

instruction type SPHL 95

instruction type XTHL 95

reading from the stack 91

writing to the stack 92

Steps needed to run an Assembly Language Program 191

Assembly Language Program 192

assembler directives 193

comments 195

creation of .ASM file using a text editor 195

DB directive 193

DW directive 193

END directive 194

EQU directive 194

Labels 195

ORG directive 193

Symbolic address 195

Structure and operation of ports 591

General structure of posts 591

Internal structure of P0 592

Internal structure of P1 594

Internal structure of P2 593

Internal structure of P3 594

Synchronous Reception 484

Pin description of 8251 USART 484

Synchronous Transmission 483

T

Timers of 8051 579

Mode 0 operation of Timer/Counter 581

Mode 1 operation of Timer/Counter 582

Mode 2 operation of Timer/Counter 582

Mode 3 operation of Timer/Counter 587

TMOD Register 580

U

Unconditional jump instructions 102

JMP a16-unconditional direct jump 103

PCHL-unconditional indirect jump 103

Unsigned binary integers 17

W

Working of 8212 311

Intel 8212 in mode 0 314

Intel 8212 in mode 1 314

Pin diagram of 8212 311

Z

Zilog Z-80 Microprocessor 495

comparison of Intel 8080 with Intel 8085 496

programmer's view of Z-80 497

special feature of Z-80 498