14.5 DECIMATOR DAG FOR s₁ = [1 0]

The DAG corresponding to s₁ is shown in Fig. 14.4. The equitemporal planes are indicated by the gray lines, and the time index values are indicated by the grayed numbers associated with the equitemporal planes. We note from the figure that a maximum of 12 tasks or nodes is active at any time step, which corresponds to the anti-aliasing filter length N. It should also be noted that the time values are associated with the high data rate of the decimator input.

Figure 14.4 M-to-1 decimator DAG for the case when M = 3, N = 12, and s₁ = [1 0].

We have three possible valid projection vectors:

(14.10)

(14.11)

(14.12)

These projection directions correspond to the projection matrices

(14.13)

(14.14)

(14.15)

We consider only the design corresponding to d_1a since the other two designs will be more complex and will not lead to a better task workload. A point in the DAG given by the coordinates p = [n k]^t will be mapped into the point in given by

(14.16)

Output sample calculations are all performed at the same time step. In that sense, the input samples are pipelined and the output samples are broadcast. We note, however, that each task is active once every M time steps. In order to reduce the number of threads or processors, we modify the linear projection operation above to employ a nonlinear projection operation

(14.17)

Figure 14.5 shows the reduced or projected architecture for Design 1a. Figure 14.5a shows the where input samples are pipelined between the tasks and the partial results for the output samples are broadcast among the tasks. Note that the number of tasks required is N/M. Figure 14.5b shows the task detail. Each task has a simple processing and control structure. Each task accepts input samples and forwards the inputs to the next task after a delay of M time steps. During each M time step, each task accumulates the partial results then loads the accumulated data to the parallel adder using a software barrier or hardware tristate buffer as shown on the left of the figure. All tasks pipeline the incoming data x(n) at the high data rate T and perform the filtering operation at the high data rate T also. The output is obtained from the rightmost task at time iMT.

Figure 14.5 for Design 1a for s₁, d_1a, N = 12, and M = 3. (a) Resulting . (b) Task processing detail.