9.6 DESIGN 2: PIPELINED INPUT AND BROADCAST OUTPUT

In this design, we apply the delay operator to the input data samples to obtain delayed input data that we use to obtain our output:

(9.16)

The above equation can be converted to the iterative expressions

(9.17)

Figure 9.3a shows the resulting DAG for an output sample y. The figure can be replicated to show the different DAGs for other output samples. When these tasks are implemented in hardware, this DAG becomes the systolic array structure that implements the FIR filter. This structure is actually one of the classical canonic realizations of Eq. 9.7. Figure 9.3b shows the details of a processor element in case of hardware implementation of the DAG. Note that only the input is pipelined between the PE stages and the output is pipelined between the tasks. A problem with this design is that the output is not stored in a register between the PE stages. For a large filter order, the design slows down since the adders evaluating the outputs are all working in parallel.

Figure 9.3 FIR digital filter software/hardware implementation with pipelined inputs. (a) DAG for FIR digital filter. (b) Processor element details.