9.4 SOFTWARE AND HARDWARE IMPLEMENTATIONS OF THE z-TRANSFORM
By using different polynomial evaluation techniques, the filter expression is converted to a set of recursive expressions that can be evaluated using multithreads or hardware systolic arrays. The z-domain technique is used for mapping the IIR filter algorithm onto tasks. These tasks, in turn, can be implemented by concurrent threads in software or by systolic arrays in hardware. The identification of tasks is described using the following steps:
1. The z-domain expression for the algorithm is converted to a set of recursive expressions. The data type in the recursive expressions determines the algorithm granularity. This will ultimately determine the computation load of the software tasks or the hardware complexity of the systolic array processing elements (PEs).
2. Each iteration in the recursive expression is assigned a task or a thread. In the case of hardware implementation, each iteration is assigned a PE.
3. The RHS of each expression defines the operations to be performed by each PE on the input variables.
4. The LHS of each expression defines the corresponding processor output.
5. The delay operators attached to each variable dictate the size of the buffers (amount of delay) within each processor.
6. The number of tasks, threads, or PEs is determined by the number of iterations required to produce the final result.
7. By ordering the shift and functional operators in the filter equations, different recursive expressions and, consequently, different structures are derived.
In the following sections, we illustrate how different FIR structures are obtained through the use of different techniques to evaluate the expression in Eq. 9.7.