Glossary
A
absolute address An address of an exact location in memory (Section 2.5).
AC0-AC3 The four accumulators available in the C55x (Section 2.5).
accumulator A register that is used as both the source and destination for arithmetic operations, as in accumulating a sum (Section 2.5).
ack Short for acknowledge, a signal used in handshaking protocols (Section 4.3).
ACPI Advanced Configuration and Power Interface, an industry standard for power management interfaces (Section 6.8).
activation record A data structure that describes the information required by a currently active procedure call (Section 2.3).
active class A UML class that can create its own thread of control (Section 6.4).
ADC Analog/digital converter (Section 4.2).
ADPCM Adaptive differential pulse code modulation (Section 6.10).
analog/digital converter A device that converts an analog signal into digital form.
AND/OR table A technique for specifying control-oriented functionality (Section 7.4).
application layer In the OSI model, the end-user interface (Section 8.4).
ASIC Application-specific integrated circuit.
aspect ratio In a memory, the ratio of the number of addressable units to the number of bits read per request (Section 4.7).
assembler A program that creates object code from a symbolic description of instructions (Section 5.4).
atomic operation An operation that cannot be interrupted (Section 6.5).
auto-indexing Automatically incrementing or decrementing a value before or after using it (Section 2.3).
average-case execution time A typical execution time for typical inputs (Section 5.6).
B
bank A block of memory in a memory system or cache (Section 4.4).
base-plus-offset addressing Calculating the address by adding a base address to an offset; the offset is usually contained in a register (Section 2.3).
basis paths A set of execution paths that cover the possible execution paths (Section 5.10).
Bayer pattern An arrangement of colors in a color filter array with two greens, one red, and one blue in a 2 × 2 pattern (Section 5.12).
Bayer pattern interpolation See demosaicing.
best-case execution time The shortest execution time for any possible set of inputs (Section 5.6).
best-effort routing The Internet routing methodology, which does not guarantee completion (Section 8.4).
big-endian A data format in which the low-order byte is stored in the highest bits of the word (Section 2.2).
black-box testing Testing a program without knowledge of its implementation (Section 5.10).
block motion estimation A video compression algorithm that estimates one frame by another by analyzing the motion of blocks in the frames (Section 8.6).
block repeat In the C55x, a set of instructions that are executed several times in a row (Section 2.5).
board support package A set of Windows CE software that enables use of a particular hardware platform.
boot-block flash A type of flash memory that protects some of its contents (Section 4.4).
bottom-up design Using information from lower levels of abstraction to modify the design at higher levels of abstraction (Section 1.3).
branch table A multiway branching mechanism that uses a value to index into a table of branch targets.
branch target The destination address of a branch (Section 2.3).
branch testing A technique to generate a set of tests for conditionals (Section 5.10).
breakpoint A stopping point for system execution (Section 4.5).
bridge A logic unit that acts as an interface between two buses (Section 4.3).
BSP See board support package.
bundle A collection of logically related signals.
burst transfer A bus transfer that transfers several contiguous locations without separate addresses for each (Section 4.3).
bus Generally, a shared connection. CPUs use buses to connect themselves to external devices and memory (Section 4.3).
bus bandwidth The bits per unit time that can be transmitted over a bus (Section 4.7).
bus grant The granting of ownership of the bus to a device (Section 4.3).
bus master The current owner of the bus (Section 4.3).
bus request A request to obtain ownership of the bus (Section 4.3).
busy-wait I/O Servicing an I/O device by executing instructions that test the device’s state (Section 3.2).
C
cache A small memory that holds copies of certain main memory locations for fast access (Section 3.5).
cache hit A memory reference to a location currently held in the cache (Section 3.5).
cache miss A memory reference to a location not currently in the cache (Section 3.5).
cache miss penalty The extra time incurred for a memory reference that is a cache miss (Section 3.6).
CAN bus A serial bus for networked embedded systems, originally designed for automobiles (Section 8.4).
Capability Maturity Model A method developed at the Software Engineering Institute of Carnegie Mellon University for assessing the quality of software development processes (Section 7.6).
capacity miss A cache miss that occurs because the program’s working set is too large for the cache (Section 3.5).
CAS See column address select.
CDFG See control/data flow graph.
central processing unit The part of the computer system responsible for executing instructions fetched from memory (Section 2.2).
certification A legal process for determining the safety of a system (Section 8.4).
changing In logic timing analysis, a signal whose value is changing at a particular moment in time (Section 4.3).
channel A separate data transfer path in a memory system (Section 4.4).
chrominance A signal related to color (Section 5.12).
circular buffer An array used to hold a window of a stream of data (Section 5.2).
circular buffer start address register In the C55x, a register used to define the start of a circular buffer (Section 5.2).
CISC Complex instruction set computer. Typically uses a number of instruction formats of varying length and provides complex operations in some instructions (Section 2.2).
class A type description in an object-oriented language (Section 1.3).
class diagram A UML diagram that defines classes and shows derivation relationships among them (Section 1.4).
clear-box testing Generating tests for a program with knowledge of its structure (Section 5.10).
CMM See Capability Maturity Model.
CMOS Complementary metal oxide semiconductor, the dominant VLSI technology today.
code motion A technique for moving operations in a program without affecting its behavior (Section 5.7).
cold miss See compulsory miss.
collaboration diagram A UML diagram that shows communication among classes without the use of a timeline (Section 1.4, Section A.3). See also sequence diagram.
color filter array An array of color filters over an image sensor, one for each pixel (Section 5.12).
color space A mathematical representation of a set of colors (Section 5.12).
color space conversion Conversion of color from one representation to another, such as from RGB to YCrCb (Section 5.12).
color temperature A measure of the color of light (Section 5.12).
column address select A DRAM signal that indicates the column part of the address is being presented to the memory (Section 4.4).
compare-and-swap An instruction that swaps a register and memory location and performs a comparison. The operation is performed atomically (Section 6.5).
component bandwidth The bits per unit time transferred by a component (Section 4.7).
compulsory miss A cache miss that occurs the first time a location is used (Section 3.5).
computational kernel A small portion of an algorithm that performs a long function (Section 8.5).
computing platform A hardware system used for embedded computing (Section 4.1).
concurrent engineering Simultaneous design of several different system components (Section 7.2).
conflict graph A graph that represents incompatibilities between entities; used in register allocation (Section 5.5).
conflict miss A cache miss caused by two locations in use mapping to the same cache location (Section 3.5).
control dependency A constraint on the order of execution of statements in a program based on control flow (Section 2.3).
control/data flow graph A graph that models both the data and control operations in a program (Section 5.3).
controllability The ability to set a value in system state during testing.
co-kernel A specialized kernel for real-time processes (Section 6.9).
co-processor An optional unit added to a CPU that is responsible for executing some of the CPU’s instructions (Section 3.4).
Cortex A family of ARM processors for compute-intensive applications (Section 2.4).
counter A device that counts asynchronous external events.
CPSR Current program status register in the ARM processor (Section 2.3).
CPU See central processing unit.
CRC card A technique for capturing design information (Section 7.5).
critical instant In RMA, the worst-case combination of process (Section 6.5).
critical section A section of code that must be executed without interference (Section 6.5).
critical timing race Two operations are in a critical timing race if the result of the operations depends on the order in which they finish (Section 6.5).
cross compiler A compiler that runs on one architecture but generates code for a different architecture (Section 4.5).
cycle-accurate simulator A CPU simulation that is accurate to the clock-cycle level (Section 5.6).
cyclomatic complexity A measure of the control complexity of a program (Section 5.10).
D
DAC Digital/analog converter (Section 4.2).
data dependency A constraint on the order of execution of statements in a program based on data calculations and assignments (Section 2.2).
data flow graph A graph that models data operations without conditionals (Section 5.3).
data flow testing A technique for generating tests by examining the data flow representation of a program (Section 5.10).
data link layer In the OSI model, the layer responsible for reliable data transport (Section 8.4).
DaVinci A media-oriented heterogeneous multiprocessor (Section 8.5).
DCT See discrete cosine transform.
DCT block In JPEG, a block of two-dimensional DCT coefficients.
DDR DRAM See double data rate DRAM.
dead code elimination Eliminating code that can never be executed (Section 5.5).
deadline The time at which a process must finish (Section 6.3).
decision node A node in a CDFG that models a conditional (Section 5.3).
def-use analysis Analyzing the relationships between reads and writes of variables in a program (Section 5.10).
delayed branch A branch instruction that always executes one or more instructions after the branch, independent of whether the branch is taken (Section 3.6).
demosaicing The process of interpolating the colors not captured at a given pixel by a color filter array (Section 5.12).
dense instruction set An instruction set designed to provide compact code (Section 5.9).
dequeue To remove something from a queue (Section 5.2).
design flow A series of steps used to implement a system (Section 7.2).
design methodology A method of proceeding through levels of abstraction to complete a design (Section 7.2).
design process See design methodology.
digital signal processor A microprocessor whose architecture is optimized for digital signal processing applications (Section 2.1).
DIMM Dual inline memory module, a small printed circuit board containing RAM chips on both sides (Section 4.4).
direct-mapped cache A cache with a single set (Section 3.5).
direct memory access A bus transfer performed by a device without executing instructions on the CPU (Section 4.3).
discrete cosine transform An image processing transform from the pixel domain to the spatial frequency domain.
distributed embedded system An embedded system built around a network or one in which communication between processing elements is explicit (Section 8.4).
DMA See direct memory access.
DMA controller A logic unit designed to execute DMA transfers (Section 4.3).
DNS See domain name service.
Domain Name Service An Internet service that translates names to Internet addresses (Section 8.4).
DOS Generically, a disc-based operating system. Often used as shorthand for MS-DOS.
DOS FAT file system A file system compatible with the MS-DOS file system.
downsampling A filtering operation that reduces the sampling rate of a signal.
Double data rate DRAM Dynamic RAM that uses advanced clocking methods to increase transfer rates (Section 4.4).
DPOF Digital Print Order Format, a standard for generating information used to control printing of images (Section 5.12).
DRAM See dynamic random access memory.
DSP See digital signal processor.
dual-kernel An operating system architecture that uses two kernels, one for real-time operation and another for non-real-time computation (Section 6.9).
dynamic power management A power management technique that looks at the CPU activity (Section 3.7).
dynamic random access memory A memory that relies on stored charge (Section 4.4).
dynamically linked library A code library that is linked into the program at the start of execution (Section 5.4).
E
earliest deadline first A variable priority scheduling scheme (Section 6.5).
EDF See earliest deadline first.
EDO RAM Extended–data-out RAM, a memory that provides looser constraints on data timing (Section 4.4).
EEPROM Electrically erasable programmable random access memory (Section 2.4).
effective address An address that can be used to fetch a memory location.
effective address calculation The process of calculating an effective address.
embedded computer system A computer used to implement some of the functionality of something other than a general-purpose computer (Section 1.2).
energy The ability to do work.
enq Short for enquiry, a signal used in handshaking protocols (Section 4.3).
enqueue To add something to a queue (Section 5.2).
entropy coding A form of lossless data compression. Huffman coding is one form of entropy coding.
entry point A label in an assembly language module that can be referred to by other program modules (Section 5.4).
error injection Evaluating test coverage by inserting errors into a program and using your tests to try to find those errors (Section 5.10).
Ethernet A local area network (Section 8.4).
evaluation board A printed circuit board designed to provide a typical platform (Section 4.5).
exception Any unusual condition in the CPU that is recognized during execution (Section 3.3).
executable binary An object program that is ready for execution (Section 5.4).
execute packet In the C64x, a set of instructions that execute together (Section 2.6).
EXIF Exchangeable Image File Format, a file format that combines image, audio, and other information (Section 5.12).
expression simplification Rewriting an arithmetic expression (Section 5.5).
external reference A reference in an assembly language program to another module’s entry point (Section 5.4).
F
fast Fourier transform An algorithm for computing a Fourier transform (Section 4.9).
fast page mode DRAM Dynamic RAM that supports a high-performance page mode (Section 4.4).
fast return In the C55x, a procedure return that uses some registers rather than the stack to store certain values (Section 2.5).
federated architecture An architecture for networked embedded systems that is constructed from several networks, each corresponding to an operational subsystem (Section 8.4).
fetch packet In the C64x, a set of instructions that are fetched together (Section 2.6).
FIR filter See finite impulse response filter.
FFT See fast Fourier transform.
field-programmable gate array An integrated circuit that can be programmed by the user and that provides multilevel logic.
file register In the PIC architecture, a location in a general purpose register file (Section 2.2).
finite impulse response filter A type of digital filter in which the output does not depend on the previous outputs (Section 5.2).
first-level cache The cache closest to the CPU (Section 3.5).
flash file system A file system specially designed for flash memory storage (Section 4.6).
flash memory An electrically erasable programmable read-only memory (Section 4.4).
FlexRay A network designed for real-time systems (Section 8.4).
fork A POSIX call that makes a copy of a process (Section 6.9).
four-cycle handshake A handshaking protocol that goes through four states (Section 4.3).
FPGA See field-programmable gate array.
FPM DRAM See fast page mode DRAM.
frame pointer Points to the end of a procedure stack frame (Section 5.5).
function In a programming language, a procedure that can return a value to the caller (Section 2.3).
functional requirements Requirements that describe the logical behavior of the system (Section 7.3).
G
glue logic Interface logic or logic that has no particular structure.
glueless interface An interface between components that requires no glue logic.
GPIO General-purpose input/output, a term for uncommitted pins that can be used as inputs or outputs.
H
HAL See hardware abstraction layer.
handshake A protocol designed to confirm the arrival of data (Section 4.3).
hardware abstraction layer Low-level software that provides drivers and support for basic elements of a hardware platform (Section 4.2).
hardware platform A hardware system used as a component in a larger system (Section 4.2).
hardware/software co-design The simultaneous design of hardware and software components to meet system requirements (Section 8.5).
Harvard architecture A computer architecture that provides separate memories for instructions and data (Section 2.2).
heterogeneous multiprocessor A multiprocessor with several different types of processing elements.
histogram In signal processing, the number of samples over a given interval in each of several ranges (Section 5.12).
hit rate The probability of a memory access being a cache hit (Section 3.5).
host system Any system that is used as an interface to another system (Section 4.5).
Huffman coding A method of data compression (Section 3.8).
I
I2C bus A serial bus for distributed embedded systems (Section 8.4).
ICE See in-circuit emulation.
IEEE 1394 A high-speed serial network for peripherals also known as Firewire.
IIR filter See infinite impulse response filter.
immediate operand An operand embedded in an instruction rather than fetched from another location (Section 2.3).
in-circuit emulation A method for debugging software running on a hardware platform (Section 4.5).
induction variable elimination A loop optimization technique that eliminates references to variables derived from the loop control variable (Section 5.7).
infinite impulse response filter A type of digital filter in which the output depends on previous values of the output.
initiation time The time at which a process becomes ready to execute (Section 6.3).
instruction-level simulator A CPU simulator that is accurate to the level of the programming model but not to timing (Section 5.6).
instruction set The definition of the operations performed by a CPU (Section 2.1).
intellectual property An intangible form of property such as software or hardware designs (Section 4.5).
Internet A worldwide network based on the Internet Protocol (Section 8.4).
Internet appliance An information system that makes use of the Internet.
Internet-enabled embedded system Any embedded system that includes an Internet interface.
Internet Protocol A packet-based protocol (Section 8.4).
interpreter A program that executes a given program by analyzing a high-level description of the program at execution time.
interprocess communication A mechanism for communication between processes (Section 6.6).
interrupt A mechanism that allows a device to request service from the CPU (Section 3.2).
interrupt handler A routine called upon an interrupt to service the interrupting device (Section 3.2).
interrupt latency The time from the assertion of an interrupt to its service (Section 6.7).
interrupt priority Priorities used to determine which of several interrupts gets attention first (Section 3.2).
interrupt service handler Software that performs the minimal operations required to respond to a device interrupt (Section 6.7).
interrupt service routine Software that handles an interrupt request (Section 6.7).
interrupt service thread In Windows CE, a user-mode thread that performs most of the work related to an interrupt (Section 6.9).
interrupt vector Information used to select which segment of the program should be used to handle the interrupt request (Section 3.2).
I/O Input/output (Section 3.2).
IP See Internet Protocol; see also intellectual property.
ISH See interrupt service handler.
ISO 9000 A series of international standards for quality process management (Section 7.6).
ISR See interrupt service routine.
IST See interrupt service thread.
J
Jazelle A set of ARM instruction set extensions for direct execution of Java bytecodes (Section 2.3).
JFIF JPEG File Interchange Format, a data format for representing JPEG data (Section 5.12).
JIT compiler A just-in-time compiler; compiles program sections on demand during execution.
jog memory In a compact disc player, memory used to buffer in the event of physical disturbances that disrupt reading (Section 8.7).
JPEG 1. A widely used image compression standard. 2. Joint Photographic Experts Group.
L
L1 cache See first-level cache.
L2 cache See second-level cache.
label In assembly language, a symbolic name for a memory location (Section 2.2).
layer diagram A diagram showing the software components. A layer can call the layer(s) immediately below it (Section 4.2).
lightweight process A process that shares its memory spaces with other processes.
line replaceable unit In avionics, an electronic unit that corresponds to a functional unit, such as a flight instrument (Section 8.4).
linker A program that combines multiple object program units, resolving references between them (Section 5.4).
Linux A well-known, open-source version of Unix (Section 6.9).
little-endian A data format in which the low-order byte is stored in the lowest bits of the word (Section 2.2).
loader A program that loads a given program into memory for execution (Section 5.4).
load map A description of where object modules should be placed in memory (Section 5.4).
load-store architecture An architecture in which only load and store operations can be used to access data and ALU, and other instructions cannot directly access memory (Section 2.3).
LIN Local Interconnect Network, a local area network designed for automotive electronics (Section 8.4).
logic analyzer A machine that captures multiple channels of digital signals to produce a timing diagram view of execution (Section 4.5).
longest path The path through a weighted graph that gives the largest total sum of weights.
loop nest A set of loops, one inside the other (Section 5.7).
loop unrolling Rewriting a loop so that several instances of the loop body are included in a single iteration of the modified loop (Section 5.5).
lossy coding Coding that changes the signal such that the decoded signal may not be identical to the original signal (Section 4.9).
LRU See line replaceable unit.
luminance A signal related to brightness (Section 5.12).
M
masking In interrupts, causing lower-priority interrupts to be held in order to service higher-priority interrupts (Section 3.2).
masking model In perceptual audio coding, a method for identifying elements of an audio signal that can be removed without being perceived by a listener (Section 4.9).
memory controller A logic unit designed as an interface between DRAM and other logic (Section 4.4).
memory management unit A unit responsible for translating logical addresses into physical addresses (Section 3.5).
memory-mapped I/O Performing I/O by reading and writing memory locations that correspond to device registers (Section 3.2).
memory mapping Translating addresses from logical to physical form (Section 3.5).
message delay The delay required to send a message on a network with no interference.
message passing A style of interprocess communication (Section 8.3).
methodology Used to describe an overall design process (Section 1.3).
microcontroller A microprocessor that includes memory and I/O devices, often including timers, on a single chip (Section 1.2).
miss rate The probability that a memory access will be a cache miss (Section 3.5).
MMU See memory management unit.
MOST Media Oriented Systems Transport, a local area network designed for automotive electronics (Section 8.4).
motion vector A vector describing the displacement between two units of an image (Section 8.6).
MP3 An audio compression standard (Section 4.9).
MPCore An ARM multiprocessor (Section 8.3).
multihop network A network in which messages may go through an intermediate PE when traveling from source to destinations.
multiprocessor A computer system that includes more than one processing element (Section 8.2).
multirate Operations that have different deadlines, causing the operations to be performed at different rates (Sections 1.2, 6.3).
N
NEON A set of ARM instruction set extensions for SIMD operations (Section 2.3).
named resource A group of shared resources controlled by a single semaphore parameterized by the resource name (Section 6.5)
network A system for communicating between components (Section 8.2).
network availability delay The delay incurred waiting for the network to become available.
network layer In the OSI model, the layer that provides end-to-end service (Section 8.4).
NMI See nonmaskable interrupt.
nonblocking communication Interprocess communication that allows the sender to continue execution after sending a message (Section 6.6).
nonfunctional requirements Requirements that do not describe the logical behavior of the system; examples include size, weight, and power consumption (Sections 1.3, 7.3).
nonmaskable interrupt An interrupt that must always be handled, independent of other system activity (Section 3.2).
O
OAL OEM Adaptation Layer, low-level software in Windows CE for interrupts, debug, and other basic functions.
object A program unit that includes both internal data and methods that provide an interface to the data (Section 1.3).
object code A program in binary form (Section 5.4).
object oriented Any use of objects and classes in design; can be applied at many different levels of abstraction (Section 1.3).
observability The ability to determine a portion of system state during testing.
operating system A program responsible for scheduling the CPU and controlling access to devices (Section 6.1).
origin The starting address of an assembly language module.
OSI model A model for levels of abstraction in networks (Section 8.4).
overhead In operating systems, the CPU time required for the operating system to switch contexts (Section 6.3).
P
P() Traditional name for the procedure that takes a semaphore (Section 6.5).
packet 1. In VLIW architectures, a set of instructions that form a unit of execution (Section 2.2). 2. In networks, a unit of transmission (Section 8.4).
page fault A reference to a memory page not currently in physical memory (Section 3.5).
page mode An addressing mechanism for RAMs (Section 4.4).
paged addressing Division of memory into equal-sized pages (Section 3.5).
partitioning Dividing a functional description into processes that can execute in parallel or modules that can be separately implemented.
PC 1. In computer architecture, see program counter. 2. Personal computer.
PC sampling Generating a program trace by periodically sampling the PC during execution.
PCI A high-performance bus for PCs and other applications.
PC-relative addressing An addressing mode that adds a value to the current PC (Section 2.3).
PE See processing element.
peek A high-level language routine that reads an arbitrary memory location (Section 3.2).
performance The speed at which operations occur (Section 1.3).
period In real-time scheduling, a periodic interval of execution (Section 6.3).
physical layer In the OSI model, the layer that defines electrical and mechanical properties (Section 8.4).
pipe A POSIX interprocess communication mechanism (Section 6.9).
pipeline A logic structure that allows several operations of the same type to be performed simultaneously on multiple values, with each value having a different part of the operation performed at any one time (Section 3.6).
pixel A sample in an image (Section 5.12).
PLC See program location counter.
platform Hardware and associated software that is designed to serve as the basis for a number of different systems to be implemented.
poke A high-level language routine that writes an arbitrary location (Section 3.2).
polling Testing one or more devices to determine whether they are ready (Section 3.2).
POSIX A standardized version of Unix (Section 6.9).
post-indexing An addressing mode in which an index is added to the base address after the fetch (Section 2.3).
power Energy per unit time (Section 3.7).
power-down mode A mode invoked in a CPU that causes the CPU to reduce its power consumption (Section 3.7).
power management policy A scheme for making power management decisions (Section 6.8).
power state machine A finite-state machine model for the behavior of a component under power management (Section 3.7).
predictive shutdown A power management technique that predicts appropriate times for system shutdown (Section 6.8).
preemptive multitasking A scheme for sharing the CPU in which the operating system can interrupt the execution of processes (Section 6.2).
presentation layer In the OSI model, the layer responsible for data formats (Section 8.2.2).
priority-driven scheduling Any scheduling technique that uses priorities of processes to determine the running process (Section 6.5).
priority inheritance An algorithm to prevent priority inversion in which a process temporarily takes on the priority of a shared resource. (Section 6.5)
priority inversion A situation in which a lower-priority process prevents a higher-priority process from executing (Section 6.5).
procedure A programming language construct that allows a single piece of code to be called at multiple points in the program (Section 2.3). Generally, a synonym for subroutine; see also function.
procedure call stack A stack of records for currently active processes (Section 2.3.3).
procedure linkage A convention for passing parameters and other actions required to call a procedure (Section 2.3).
process A unique execution of a program (Section 6.2).
processing element A component that performs a computation under the coordination of the system (Section 8.2).
producer/consumer A set of functions or processes in which one writes data to be read by the other (Section 5.2).
profiling A procedure for counting the relative execution times of different parts of a program (Section 5.6).
program counter A common name for the register that holds the address of the currently executing instruction (Section 2.2).
program location counter A variable used by an assembler to assign memory addresses to instructions and data in the assembled program (Section 5.4).
programming model The CPU registers visible to the programmer (Section 2.2).
pseudo-op An assembly language statement that does not generate code or data (Sections 2.2, 5.4).
Q
quality assurance A process for ensuring that systems are designed and built to high quality standards (Section 7.6).
quantization Assignment of a continuous sample value to a discrete value.
quantization matrix In JPEG, a set of values used to guide quantization (Section 5.12).
queue A data structure that provides first-in first-out access to data (Section 5.2).
R
race condition A set of processes whose results depend on the order in which they execute (Section 6.5).
RAM See random-access memory.
random-access memory A memory that can be addressed in arbitrary order (Section 4.4).
random testing Testing a program using randomly generated inputs (Section 5.10).
RAS See row address select.
raster scan (or order) display A display that writes pixels by rows and columns.
rate Inverse of period (Section 6.2).
rate-monotonic scheduling A fixed-priority scheduling scheme (Section 6.4).
reactive system A system designed to react to external events.
read-only memory A memory with fixed contents (Section 4.4).
real time A system that must perform operations by a certain time (Section 1.2).
real-time operating system An operating system designed to be able to satisfy real-time constraints (Section 6.1).
reentrancy The ability of a program to be executed multiple times, using the same memory image without error (Section 5.4).
refresh Restoring the values kept in a DRAM (Section 4.4).
register Generally, an electronic component that holds state. In the context of computer programming, storage internal to the CPU that is part of the programming model (Section 2.2).
register allocation Assigning variables to registers (Section 5.5).
register-indirect addressing Fetching from a first memory location to find the address of the memory location that contains the operand (Section 2.3).
regression testing Testing hardware or software by applying previously used tests (Section 5.10).
relative address An address measured relative to some other location, such as the start of an object module (Section 5.4).
relocatable Instructions and data that have not yet been assigned to particular locations in memory (Section 5.4).
repeat In instruction sets, an instruction that allows another instruction or set of instructions to be repeated in order to create low-overhead loops (Section 2.4).
requirements An informal description of what a system should do (Section 1.3). A precursor to a specification.
reservation table A hardware technique for scheduling instructions (Section 5.5).
response time The time span between the initial request for a process and its completion (Section 6.5).
RISC Reduced instruction set computer (Section 2.2).
RMA Rate-monotonic analysis, another term for rate-monotonic scheduling.
rollover Reading multiple keys when two keys are pressed at once.
ROM See read-only memory.
row address select A DRAM signal that indicates the row part of the address is being presented (Section 4.4).
RTOS See real-time operating system.
S
saturation arithmetic An arithmetic system that provides a result at the maximum/minimum value on overflow/underflow.
scheduling Determining the time at which an operation will occur (Section 8.5.4).
scheduling overhead The execution time required to make a scheduling decision (Sections 6.2.1, 6.3.3).
scheduling policy A methodology for making scheduling decisions (Section 6.3.3).
SDE See software development environment.
SDL A software specification language (Section 7.4.1).
SDRAM See synchronous DRAM.
second-level cache A cache after the first-level cache but before main memory (Section 3.5.1).
segmented addressing Dividing memory into large, unequal-sized segments (Section 3.5.2).
semaphore A mechanism for coordinating communicating processes (Section 6.5).
sequence diagram A UML diagram type that shows how objects communicate over time using a timeline (Section 1.3). See also collaboration diagram.
session layer In the OSI model, the layer responsible for application dialog control (Section 8.4).
set-associative cache A cache with multiple sets (Section 3.5).
set-top box A system used for cable or satellite television reception.
shared memory A communication style that allows multiple processes to access the same memory locations (Section 8.3).
shared resource A resource, such as an I/O device or a memory location, that is used by more than one process (Section 6.5).
sharpening In image processing, a filtering process that produces edges that appear to be sharper (Section 5.12).
signal 1. A Unix interprocess communication method (Section 6.6). 2. A UML stereotype for communication (Section 6.4).
SIMM Single inline memory module, a small printed circuit board containing RAM chips on one side (Section 4.4).
single-assignment form A program that writes to each variable once at most (Section 5.3).
single-hop network A network in which messages can travel from one PE to any other PE without going through a third PE.
slow return In the C55x, a procedure return that uses the stack to restore return address and loop context; compare to fast return that uses registers (Section 2.5).
software development environment A set of tools for developing software, often including an editor, compiler, linker, and debugger (Section 4.5).
software interrupt See trap.
software pipelining A technique for scheduling instructions in loops.
software platform Software used as a component in a larger system (Section 4.3).
spatial frequency A frequency representation of a modulated visual intensity (Section 5.12).
special function register In the PIC architecture, registers for I/O and other special operations (Section 2.4).
specification A formal description of what a system should do (Section 1.3). More precise than a requirements document.
speedup The ratio of system performance before and after a design modification (Section 8.5).
spill Writing a register value to main memory so that the register can be used for another purpose (Section 5.5).
spiral model A design methodology in which the design iterates through specification, design, and test at increasingly detailed levels of abstraction (Section 7.2).
SRAM See static random-access memory.
stack pointer Points to the top of a procedure call stack (Section 5.5).
Statecharts A specification technique that uses compound states (Section 7.4).
state machine Generally, a machine that goes through a sequence of states over time. May be implemented in software (Sections 1.3, 5.2).
state mode A logic analyzer mode that provides reduced timing resolution in return for longer time spans (Section 4.5).
static power management A power management technique that does not consider the current CPU behavior (Section 3.7).
static random-access memory A RAM that consumes power to continuously maintain its stored values (Section 2.4).
static scheduling A scheduling policy in which process priorities are fixed (Section 6.5).
streaming data A sequence of data values that is received periodically, such as in digital signal processing.
strength reduction Replacing an operation with another equivalent operation that is less expensive (Section 5.7).
subroutine A synonym for procedure (Section 2.3).
successive refinement A design methodology in which the design goes through the levels of abstraction several times, adding detail in each refinement phase (Section 7.2).
superscalar An execution method that can perform several different instructions simultaneously using dynamically scheduled instructions (Section 2.2).
supervisor mode A CPU execution mode with unlimited privileges (Section 3.3). See also user mode.
symbol table Generally, a table relating symbols in a program to their meaning; in an assembler, a table giving the locations specified by labels (Section 5.4).
synchronous DRAM A memory that uses a clock (Section 4.4).
system-on-silicon A single-chip system that includes computation, memory, and I/O.
T
tag The part of a cache block that gives the address bits from which the cache entry came (Section 3.5).
target system A system being debugged with the aid of a host (Section 4.5).
task graph A graph that shows processes and data dependencies among them (Section 6.3).
TCP See Transmission Control Protocol.
testbench A setup used to test a design; may be implemented in software to test other software (Section 4.5).
testbench program A program running on a host used to interface to a debugger that runs on an embedded processor (Section 4.5).
thread See lightweight process.
thumbnail A small version of an image (Section 5.12).
TIFF Tagged Image File Format, an image file format (Section 5.12).
timer A device that measures time from a clock input.
timing mode A logic analyzer mode that provides increased timing resolution (Section 4.5).
TLB See translation lookaside buffer.
top-down design Designing from higher levels of abstraction to lower levels of abstraction (Section 1.3).
trace A record of the execution path of a program (Section 5.6).
trace-driven analysis Analyzing a trace of a program’s execution (Section 5.6).
translation lookaside buffer A cache used to speed up virtual-to-physical address translation (Section 3.5).
Transmission Control Protocol A connection-oriented protocol built upon the IP (Section 8.4).
transport layer In the OSI model, the layer responsible for connections (Section 8.4).
trap An instruction that causes the CPU to execute a predetermined handler (Section 3.3).
TrustZone A set of ARM instruction set extensions for security operations (Section 2.3).
U
UART Universal Asynchronous Receiver/Transmitter, a serial I/O device.
UML See Unified Modeling Language.
unified cache A cache that holds both instructions and data (Section 3.5).
Unified Modeling Language A widely used graphical language that can be used to describe designs at many levels of abstraction (Section 1.3.6).
upsampling A filtering operation that increases the sampling rate of a signal.
usage scenario A description of how a system will be used (Section 7.6).
USB Universal Serial Bus, a high-performance serial bus for PCs and other systems.
user mode A CPU execution mode with limited privileges (Section 3.3). See also supervisor mode.
utilization In general, the fractional or percentage time that we can effectively use a resource; the term is most often applied to how processes make use of a CPU (Section 6.5).
V
V() Traditional name for the procedure that releases a semaphore (Section 6.5).
very long instruction word A style of computer architecture in which multiple instructions are statically scheduled. Compare to superscalar (Section 2.2).
virtual addressing Translating an address from a logical to a physical location (Section 3.5).
VLIW See very long instruction word.
VLSI Acronym for very large scale integration; generally means any modern integrated circuit fabrication process (Section 1.2).
von Neumann architecture A computer architecture that stores instructions and data in the same memory (Section 2.2).
W
wait state A state in a bus transaction that waits for the response of a memory or device (Section 4.3).
watchdog timer A timer that resets the system when the system fails to periodically reset the timer.
waterfall model A design methodology in which the design proceeds from higher to lower levels of abstraction (Section 7.2).
way A bank in a cache (Section 3.5).
white-box testing See clear-box testing.
word The basic unit of memory access in a computer (Section 2.3).
working set The set of memory locations used during a chosen interval of a program’s execution (Section 3.5).
worst-case execution time The longest execution time for any possible set of inputs (Section 5.6).
write-back Writing to main memory only when a line is removed from the cache (Section 3.5).
write-through Writing to main memory for every write into the cache (Section 3.5).
Z
zig-zag pattern In JPEG, the order in which DCT coefficients are read from the matrix. The zig-zag pattern starts at the upper left and moves in diagonals to the lower right (Section 5.12).
Zynq An FPGA with an on-board multiprocessor (Section 8.5).