Further reading
Shanley and Anderson [Min95] describe the PCI bus in detail. Dahlin [Dah00] describes how to interface to a touchscreen. Collins [Col97] describes the design of microprocessor in-circuit emulators. Earnshaw et al. [Ear97] describe an advanced debugging environment for the ARM architecture.
Questions
Q4-1 Name three major components of a generic computing platform.
Q4-2 What role does the HAL play in the platform?
Q4-3 Draw UML state diagrams for device 1 and device 2 in a four-cycle handshake.
Q4-4 Describe the role of these signals in a bus:
Q4-5 Draw a UML sequence diagram that shows a four-cycle handshake between a bus master and a device.
Q4-6 Define these signal types in a timing diagram:
Q4-7 Draw a timing diagram with the following signals (where [t1,t2] is the time interval starting at t1 and ending at t2):
a. signal A is stable [0,10], changing [10,15], stable [15,30]
b. signal B is 1 [0,5], falling [5,7], 0 [7,20], changing [20,30]
c. signal C is changing [0,10], 0 [10,15], rising [15,18], 1 [18,25], changing [25,30]
Q4-8 Draw a timing diagram for a write operation with no wait states.
Q4-9 Draw a timing diagram for a read operation on a bus in which the read includes two wait states.
Q4-10 Draw a timing diagram for a write operation on a bus in which the write takes two wait states.
Q4-11 Draw a timing diagram for a burst write operation that writes four locations.
Q4-12 Draw a UML state diagram for a burst read operation with wait states. One state diagram is for the bus master and the other is for the device being read.
Q4-13 Draw a UML sequence diagram for a burst read operation with wait states.
Q4-14 Draw timing diagrams for
Q4-15 Draw a timing diagram that shows a complete DMA operation, including handing off the bus to the DMA controller, performing the DMA transfer, and returning bus control back to the CPU.
Q4-16 Draw UML state diagrams for a bus mastership transaction in which one side shows the CPU as the default bus master and the other shows the device that can request bus mastership.
Q4-17 Draw a UML sequence diagram for a bus mastership request, grant, and return.
Q4-18 Draw a UML sequence diagram that shows a DMA bus transaction and concurrent processing on the CPU.
Q4-19 Draw a UML sequence diagram for a complete DMA transaction, including the DMA controller requesting the bus, the DMA transaction itself, and returning control of the bus to the CPU.
Q4-20 Draw a UML sequence diagram showing a read operation across a bus bridge.
Q4-21 Draw a UML sequence diagram showing a write operation with wait states across a bus bridge.
Q4-22 Draw a UML sequence diagram for a read transaction that includes a DRAM refresh operation. The sequence diagram should include the CPU, the DRAM interface, and the DRAM internals to show the refresh itself.
Q4-23 Draw a UML sequence diagram for an SDRAM read operation. Show the activity of each of the SDRAM signals.
Q4-24 What is the role of a memory controller in a computing platform?
Q4-25 What hardware factors might be considered when choosing a computing platform?
Q4-26 What software factors might be considered when choosing a computing platform?
Q4-27 Write ARM assembly language code that handles a breakpoint. It should save the necessary registers, call a subroutine to communicate with the host, and upon return from the host, cause the breakpointed instruction to be properly executed.
Q4-28 Assume an A/D converter is supplying samples at 44.1 kHz.
a. How much time is available per sample for CPU operations?
b. If the interrupt handler executes 100 instructions obtaining the sample and passing it onto the application routine, how many instructions can be executed on a 20-MHz RISC processor that executes 1 instruction per cycle?
Q4-29 If an interrupt handler executes for too long and the next interrupt occurs before the last call to the handler has finished, what happens?
Q4-30 Consider a system in which an interrupt handler passes on samples to an FIR filter program that runs in the background.
a. If the interrupt handler takes too long, how does the FIR filter’s output change?
b. If the FIR filter code takes too long, how does its output change?
Q4-31 Assume that your microprocessor implements an ICE instruction that asserts a bus signal that causes a microprocessor in-circuit emulator to start. Also assume that the microprocessor allows all internal registers to be observed and controlled through a boundary scan chain. Draw a UML sequence diagram of the ICE operation, including execution of the ICE instruction, uploading the microprocessor state to the ICE, and returning control to the microprocessor’s program. The sequence diagram should include the microprocessor, the microprocessor in-circuit emulator, and the user.
Q4-32 Why might an embedded computing system want to implement a DOS-compatible file system?
Q4-33 Name two example embedded systems that implement a DOS-compatible file system.
Q4-34 We are given a 1-word-wide bus that supports single-word and burst transfers. The overhead of the single-word or dual-word transfer is 2 clock cycles (O = 2). Plot the breakeven point between single-word and burst transfers for several values of burst overhead—for each value of overhead, plot the length of burst transfer at which the burst-transfer is as fast as a series of single-word transfers. Plot breakeven for burst overhead values of 0, 1, 2, and 3 cycles.
Q4-35 We are given a 2-word-wide bus that supports single-word, dual-word (same clock cycle) and burst transfers. The overhead of the single-word or dual-word transfer is 2 clock cycles (O = 2) and a data transfer takes one clock cycle per single or dual word (D = 1). Plot the breakeven point between dual-word and burst transfers for several values of burst overhead—for each value of overhead, plot the length of burst transfer at which the burst-transfer is as fast as a series of single-word transfers. Plot breakeven for burst overhead values of 1, 2, and 3 cycles.
Q4-36 We are given a 2-byte-wide bus that supports single-byte, dual-word (same clock cycle) and burst transfers. The overhead of the single-byte or dual-byte transfer is 1 clock cycle. You want to send a 1080P video frame at a resolution of 1920 # 1080 pixels with three bytes per pixel. Compare the difference in bus transfer times if the pixels are packed vs. sending a pixel as a 2-byte followed by a single-byte transfer.
Q4-37 Determine the design parameters for an audio system:
a. Determine the total bytes/sec required for an audio signal of 16 bits/sample per channel, two channels, sampled at 44.1 kHz.
b. Given a clock period P = 20 MHz for a bus, determine the bus width required assuming that nonburst mode transfers are used and D = O = 1.
c. Given a clock period P = 20 MHz for a bus, determine the bus width required assuming burst transfers of length four and D = O = 1.
d. Assume the data signal now contains both the original audio signal and a compressed version of the audio at a bit rate of 1/10 the input audio signal. Compute the total data bandwidth and the bus bandwidth for burst transfers of length four with P = 20 MHz and D = O = 1.
Q4-38 You are designing a system a bus-based computer: the input device I1 sends its data to program P1; P1 sends its output to output device O1. Is there any way to overlap bus transfers and computations in this system?
Lab exercises
L4-1 Use a logic analyzer to view system activity on your bus.
L4-2 If your logic analyzer is capable of on-the-fly disassembly, use it to display bus activity in the form of instructions, rather than simply 1s and 0s.
L4-3 Attach LEDs to your system bus so that you can monitor its activity. For example, use an LED to monitor the read/write line on the bus.
L4-4 Design logic to interface an I/O device to your microprocessor.
L4-5 Use a data dump program to study the format of data on a flash memory card used as a file system.
L4-6 Have someone else deliberately introduce a bug into one of your programs, and then use the appropriate debugging tools to find and correct the bug.
L4-7 Identify the different bus transaction types in your platform. Compute the best-case bus bandwidth.
L4-8 Construct a simple program to access memory in widely separated places. Measure the memory system bandwidth and compare to the best-case bandwidth.
L4-9 Construct a simple program to perform some memory accesses. Use a logic analyzer to study the bus activity. Determine what types of bus modes are used for the transfers.