14.13 INTERPOLATOR DAG FOR s₂ = [1 −1]

The DAG corresponding to s₂ is shown in Fig. 14.15. The equitemporal planes are indicated by the gray lines and the time index values are indicated by the grayed numbers associated with the equitemporal planes. We note from the figure that a maximum of four nodes is active at any time step. It should also be noted that the time values are associated with the high data rate of the interpolator input. We have three possible valid projection vectors:

(14.44)

(14.45)

(14.46)

Figure 14.15 1-to-L interpolator DAG for the case when L = 3, N = 12, and s₂ = [1 −1].

These projection directions correspond to the projection matrices

(14.47)

(14.48)

(14.49)

We consider only the design corresponding to d_2a since the other two designs will be more complex and will not lead to better processing element (task) designs. A point in the DAG given by the coordinate p = [n k]^t will be mapped into the point

(14.50)

Input samples are supplied to the array at the same time step. In that sense, the input samples are broadcast and output samples are pipelined. We note, however, that each task is active once every L time steps. In order to reduce the number of nodes, we modify the linear projection operation above to employ a nonlinear projection operation:

(14.51)

Figure 14.16 shows the hardware architecture for Design 2a. Figure 14.16a shows the pipeline where input samples are broadcast between the tasks and the partial results for the output samples are pipelined among the nodes. Note that the number of tasks required is N/L. Figure 14.16b shows the task detail. Each task is simple in hardware and in control structure. Each task accepts an input sample every L time steps and forwards the input to the next task after a delay of L time steps. All tasks pipeline the incoming data x(n) at the low data rate and perform the filtering operation at the high data rate. The output is obtained from the leftmost task at each time step.

Figure 14.16 Design 2a for s₂, d_2a, N = 12, and L = 3. (a) . (b) Task detail for hardware systolic array implementation.