Note 53. Multistage Decimators

When large reductions in sampling rates are required, the design of adequate decimation filters becomes more difficult, usually resulting in filters with a prohibitively large number of taps. This note introduces multistage decimators that accomplish large reductions in sampling rate as a sequence of several smaller reductions. In a properly designed multistage approach, the filters for all the stages have a total tap count that is significantly lower than the filter tap count needed to obtain similar performance from a single-stage implementation.

When the desired decimation factor, M, can be expressed as a product of I positive integer factors

M = M₁ M₂ ... M_I

the desired decimation can be realized as a cascade of I decimators, each decimating by one of the factors, M_i. Compared to a single-stage decimator design, a design that adopts a multistage approach usually results in a reduced total computational burden, reduced memory usage, simpler filter designs, and reduced sensitivity to finite word-length effects in the implementation of the filters.

In lowpass FIR filter designs, the number of required taps, N, is approximately inversely proportional to the normalized transition bandwidth

53.1

where f_p is the passband edge fequency in Hz, f_s is the stopband edge frequency in Hz, and F_S is the sampling rate in samples per second. To reduce N, we need either to decrease F_S or to increase the difference between f_s and f_p. In a single-stage decimator we don’t have the freedom to make either change. However, in a two-stage decimator, there is some flexibility in the choice of the first-stage stopband edge frequency, f_s1.

Figure 53.1 illustrates the important frequency relationships in a two-stage decimator design. The folding frequency of the first stage of the decimator is equal to half the sample rate, F₁, at the first-stage output.

Figure 53.1. Crtical frequency relationships for a two-stage decimator

As shown in the figure, all frequency content above F₁/2 remaining in the signal after the first-stage filter is aliased into frequencies below F₁/2 once downsampling by M₁ is performed. Frequencies from 0 to f_S2 (which comprise the ultimate output spectrum) must be protected from aliasing. However, we do not care about aliasing in frequencies from f_S2 up to F₁/2, because all these frequencies will be removed by the second-stage filter. Therefore, to avoid aliasing of first-stage transition-band frequencies into the output of the second-stage decimator, the stopband edge for the first-stage filter, f_S1, must be set to a value that does not exceed F₁– f_S2. Figure 53.2 shows the limiting case in which f_P1 = f_P2 and f_S1 = F₁– f_S2.

Figure 53.2. Limiting case for critical frequency relationships for a two-stage decimator

The width of the transition band for the first-stage filter can be as wide as ΔF₁ = F₁– f_S2 – f_P2, which, in most cases, is significantly larger than the transition width of ΔF = f_S – f_P for a single-stage implementation. From Eq. (53.1), it is clear that a larger transition width results in a lower number of required taps.

For the second stage of a two-stage inplementation, the edges of the transition band are the same as they would be for a single-stage design:

f_P2 = f_P and f_S2 = f_S

Because the sample rate going into the second-stage filter has already been reduced by a factor of M₁, that is, F₂ = F₁/M₁, we can conclude from Eq. (53.1) that, except for changes to ripple specifications that may be needed due to multiple stages, the number of taps needed for the second stage can be approximated by

In most practical cases, N₁ + N₂ is significantly smaller than N.

Because a total of N multiplications would be needed in the single-stage design to generate each decimator output sample, the average required multiplication rate can be approximated as

53.2

In comparison, the average required multiplication rate for the two-stage design would be

53.3

A specific case of two-stage decimator design is provided in Example 53.1.