Index

Page numbers followed by f indicates a figure and t indicates a table.

A

Absolute addresses, 82, 229, 235
Accelerators, 10, 47, 431, 432–434, 454
performance analysis, 434–438
video, see Video accelerators
Accumulator, 75, 78, 84, 86
architecture, 77–78
C55x DSP, 77–78
value of, 85
Active rangefinding approach, 286
Adaptive differential pulse code modulation (ADPCM), 361
coding scheme, 361f
compression system, 362f
Address, 58, 66, 82, 118, 161, 172, 230, 233, 358, 423
bus, 162
data byte, 32
Internet, 430
modes, 65, 75, 81–83
range, for PIC16F microprocessor, 73
spaces, in TMS320C55x, 81f
translation, 123–128
transmission, 424
types, 86
Advanced configuration and power interface (ACPI), 351–352
Aircraft electronics, 421–422
Airplanes, distributed computing in, 419–422
Alarm clock, system design
class diagram for, 195f
component design and testing, 200
requirements, 193–194
scan-keyboard, 196, 198f
specification, 194–196
system architecture, 197–199
system integration and testing, 200
update-time, 196, 197f
Allocating processes, on distributed embedded systems, 438–441
AMBA high-performance bus (AHB), 171
AMBA peripherals bus (APB), 172
Analog physical objects, in train control system, 35f
AND/OR tables, 393
Anti-lock braking system (ABS), 4, 419, 420
Aperiodic process, 312
Application interface, 425
Application layer, 415
Application-specific integrated circuits (ASIC), 386
AR indirect addressing, 82
Architecture design, 17–19, 383
system analysis and, 396–400
Arithmetic expression, 238
address translation, 127f
AMBA bus system, elements of, 171f
assembly language, example of, 54, 55f
caches, 122
co-processors in, 116
data processing instruction, format of, 54, 55, 55f
evaluation module, 176, 178f
execution time of for loop, 131
memory-mapped I/O, 98
MPCore architecture, 413
processor, 51, 57–73
and memory organization, 58
condition codes in, 66, 67f
flow of control in, 66–72
instructions, 63f
models of, 72–73
procedure calls in, 71
programming model, 59, 59f
supervisor mode, 114
ARM7, 58, 112–113
pipeline, 128
ARM Cortex™-A8, 176
ARM Procedure Call Standard (APCS), 71
Array padding, 264–265, 266
Assemblers, 54–55, 229–233
Assembly languages, 58, 230, 240–242, 253, 321
for C55x DSPs, 77
features of, 54–55
program, 229, 233
Assembly source code, 230
Asynchronous input, 309
Asynchronous interrupts, 113
latency of, 114
Audio
compression, 200–201
decompression, 200
playback, state diagram for, 203, 205f
Audio player, system design
classes in, 203f
component design and testing, 206
operation theory and requirements, 200–202, 203f
specification, 202–204
system architecture, 204–206
system integration and debugging, 206
Auto-indexing, 65–66
Automatic stability control system, 4
Automobile, 3, 4, 414
engine controllers, 4, 311
network, 420f
Automotive engine control, 310
Automotive networks, 419
Auxiliary data pointer registers, 79
Average-case execution time, 255, 348
Avionics, 421–422

B

Backup flight control system (BFS), 314
Bandwidth, 444
and memory access times, 191
as performance, 189
bus, 189, 444
component, 190
Base class, 24
Baseline packet, 32
Base-plus-offset addressing, 65, 68
Basic block, 224, 224f, 225f, 226, 260
Baud rate, 97, 282
Bayer pattern, 286, 287f
interpolation, 286
BeagleBoard, 176, 177f
intellectual property, 179
Best-case execution time, 255
Big-endian mode, vs. little-endian mode, 54, 58f
Bit manipulations, 148
Black-and-white display, 23
Black-box testing, 278–279
Block motion estimation, 441, 442f
Block motion search parameters, 444f
Block repeat registers, 79
Blocks, cache, 118
BLT instruction, 132
Bluetooth, 419
BMW 850i, microprocessors used in, 4
Boolean expression, 393
Boot block flash, 174
Bottom-up design, 11
Branches, 57, 66, 76–77, 84, 242, 254
penalty, 129, 130f
testing, 275
Breakpoint, 181
Buffer class, 140
Bugs, 19, 20, 280, 404, 405f, 406
Burst access, 173
Bus, 159–172, 178
arbitration, 417, 425
bandwidth, 189
bridges, 170
burst transfers, 165, 166f
times and data volumes in, 190f
components of, 161
disconnected transfers, 166
grant, 167
interface module, 447
master, 160, 167
operations, 162f
organization and protocol, 160–167, 160f
reads and writes, 162
request, 167
signals, bundle of, 160
state diagrams for read transaction, 166, 167f
timing diagram, 162, 163, 163f, 164f
transaction, 424
on I2C bus, 425f
transfers, times and data volumes in, 190f
with DMA controller, 168f
Bus-based system, performance bottlenecks in, 188, 192
Busy-wait I/O devices, 99–100
Byte, 32
format, 425, 425f
organizations, within ARM word, 58f, 60

C

C programming language
assignments, in ARM instructions, 64
coding guidelines, 86–87
functions, 69
Cache, 116–117, 267
ARM, 122
controllers, 117
direct-mapped vs. set-associative, 121
effect, 259
hit, 117
in memory system, 117f
performance, 117
microprocessor architectures, 116
miss, 117
penalty, 132
optimizations, 264–265
organization, 118
performance in CPU, 132
set-associative, 120, 120f
two-level system, 118, 118f
Call event, 26f, 27, 28
Capability maturity model (CMM), 403–404
Capacitive toggling, 133
Capacity miss, 117, 132
Car subsystems, 419
interactions, 420
Carrier Sense Multiple Access with Arbitration on Message Priority (CSMA/AMP), 417
Carrier Sense Multiple Access with Collision Detection (CSMA/CD), 427, 427f
CDP indirect addressing, 83
Central office, 362
Central processing unit (CPU), 54
internal registers of, 52
Certification process, 421
Chrominance, 285, 287
Circular buffers, 79, 216–221, 216f
Cirrus CS7410, 204
Classes, responsibilities and collaborators (CRC) cards, 396–400, 397f, 418
Clear-box testing
branch testing, 275
control/data flow graph, 271
data flow testing, 276
def-use pair, 277
domain testing, 277f
execution path, 272
graph, matrix representation of, 130–132, 254–256, 258, 268, 274f
incidence matrix, 274
loops, testing, 278
Code generator, 237
Code modules, 234
data compressor, 139
Code motion, 262, 263f
Coding
alphabet, 361
bug, 404
Coefficient data pointer registers, 79
Coefficient indirect addressing, 83
Coefficient matrix, in zig-zag pattern, 289, 290f
Cold miss, 117
Collision avoidance system (CAS), 394–396
Color
channels, 288
filter array, 286, 287f
spaces, 288
temperature, 287
Common intermediate format (CIF), 444
Common object file format (COFF), 233
Communications, 185
Compact disc (CD), 449
disks and data, 450, 450f
mechanism, 451, 451f
player, system architecture of, 453, 453f
servo control, 452
writable, 454
Compare instruction, 84
Compilation, 180, 245
methods
arithmetic expression, 238
control flow diagram, 240, 240f
data structures, 244
linkage mechanism, 242
stack pointer (sp), 243
two-dimensional arrays, 245f
process, 228, 236–237, 237f
Compiler, 56, 66, 71
optimizations
graph coloring, 249, 249f
loop fusion, 246
loop tiling, 247f
loop unrolling, 245
register allocation, 247, 249
reservation table, instruction scheduling, 251, 252f
template matching, code generation by, 252, 253f
Complementary metal oxide semiconductor (CMOS), power characteristics, 133
Complex instruction set computers (CISC), vs. RISC, 53
Component bandwidth, 190
Component design, testing and, 19, 200, 206, 284, 296, 368, 373, 449
Compression module, 367
Compulsory miss, 117, 132
Computational kernels, 432
Computer architecture taxonomy, 52–54
implementations of, 54
Computer-aided design (CAD), 339, 383
Computing platforms, 44, 155–159
choosing, 176–179
designing with, 176–185
hardware components, 156–158, 176
software components, 158–159, 179
Concurrent engineering, 386, 388
Condition codes, in ARM, 66, 67f
Conflict miss, 117, 132
Console class, 34
Consumer electronics devices
functional requirements of, 185
hardware architecture of, 187, 187f
nonfunctional requirements of, 186
use cases of, 186, 186f
Context switching mechanism, 321
Contrast detection, 286
Control algorithm, 311, 452
Control channel, 419
Control flow diagram, 240, 240f
Control flow–oriented testing, 275
Control stall, 129
Control/data flow graph (CDFG), 45, 223, 226–228, 228f, 271
Controller Area Network (CAN) bus, 414, 416–419, 416f, 418f
Controller class, 35, 39, 40f, 202, 293
Controller operate behavior, 41f
Controls activate behavior, 364, 366f
Co-processors, 115–116, 150, 432
Core processor modules (CPMs), 421
Cortex, 73
CPU, 54, 87
accelerator, 432, 433f
bus, see Bus
cache performance, 132
DMA bus transaction on, 168
internal registers of, 52
pipeline
ARM7, 128, 129f
PIC16F, 130
RISC machines, 128
stalls, 129
power consumption
energy vs. power, 133
power state machine, 135, 135f
PowerPC 603, 134
static vs. dynamic power management, 134
StrongARM SA-1100, 136, 136f
utilization, 329
Cross-compiler, 180
Current program status register (CPSR), 60, 114
Current-bit behavior, 140
C55x
caches, 122
interrupts in, 113
pipeline, 128
C55x DSPs, 51, 77–87
and memory organization, 78–80
memory map, 79, 81f
C64x DSPs, 51
Cyber-physical considerations, 410
Cyber-physical system, 7–8
Cycle-accurate simulator, 260
Cyclic redundancy check (CRC), 417
Cyclomatic complexity, 274, 275f

D

Data
access system, 53
buffers, 270
dependencies, 56, 56f, 57f, 315f
frames, 416
CAN, 417, 417f
instructions, in PIC16F microprocessor, 75
link layer, 415, 423
operations, 83–84
in ARM processor, 59–66, 59f, 61f
in PIC16F microprocessor, 73–76
page pointers, 79
pointer registers, auxiliary and coefficient, 79
ready signal, 164
registers, 96
space for PIC16F microprocessor, 74
stall, 129
storage
on compact disc, 450, 450f
and management, 185
stream style, 216
structures, 244
queues, 223
transmission, 419
types in video accelerator, 445, 445f
Data compressor
program design
non–object-oriented implementation, 146
OO design in C++, 142
requirements and algorithm, 137–139
specification, 140–141
testing, 148–149, 149f
Data-buffer, 140
Data-dependent program paths, 256–257
Data flow
graphs, 224, 224–226, 225f
nodes, 226
testing, 276
Dead code, 246, 247
Deadline, 5, 185, 312, 312f
meeting, 8–9
Debugging, 20, 44, 206
challenges, 183–185
interrupt code, 106
techniques, 181–183
Decision nodes, 226
Decompression module, 367
Definition-use analysis, 276
Delay slots, 89
Delayed branch, 130
Demosaicing, 286
Dense instruction sets, 270
Dequeueing, 222
Derived class, 23–24
Design
flows, 383–389
methodologies
example of, 383
product metrics, 382
process, 381
review format, 406
Design rule for Camera File (DCF) standard, 291
Desktop processors, power requirements of, 411
Detector classes, 35, 36
Device driver, 101, 112
Diamond-shaped nodes, 226
Digital Command Control (DCC), 30–32, 31f
Digital Command Control Communication Standard, 31
Digital Command Control Electrical Standard, 31
Digital filters, 218, 223
Digital media processor, 431
Digital signal processors (DSPs), 51, 53, 56, 72
Digital still camera (DSC), 45
architecture of, 293
design of, 285–296
file formats for, 290
image compression, 287, 288f
imaging algorithms, 285
integration and testing, 296
operation and requirements, 285–289, 290f, 292
Digital system, 6
Direct addresses, 82
Direct memory access (DMA), 157
controller, 167, 168, 168f
request, cyclic scheduling of, 169f
Directed acyclic graph (DAG), 315
Direct-mapped cache, 118, 119, 119f
vs. set-associative cache, 121
Discrete cosine transform (DCT), 441
coefficients, 288–289
Display class, 22
Distributed embedded systems, 414
CAN bus, 416–419
Ethernet, 426–429
in cars and airplanes, 419–422
I2C bus, 422–426
scheduling and allocation, 438–441
Distributed system, 414
system-on-chip vs., 412
Documents, DCC, 30
Domain Name Server (DNS), 430
Domain testing, 277f
Dominant, 414, 416
DOS file systems, 187
Double in-line memory modules (DIMMs), 174
DRAM, see Dynamic RAM
Dual AR indirect addressing, 83
Dual-kernel approach, 352
Dynamic power management mechanism, 134, 349
Dynamic programming, 252
Dynamic RAM (DRAM)
organization of, 172
types of, 173
Dynamically linked libraries (DLLs), 235, 358

E

Earliest deadline first (EDF), 333–337, 344
8-bit microcontroller, 3, 342
Eight-to-fourteen (EFM) encoding, 452
Elastic buffer, 103, 104, 221, 223, 341
Electrical interface to I2C bus, 422, 423f
Electronic control units (ECUs), 414
Embedded computing
multiprocessor system-on-chip for, 413
platform, 44
systems, 2, 177, 308, 385, 410, 411
challenges in design, 8–9
characteristics of applications, 4–5
design process, 381
multirate, 310
performance of, 9–10
VLIW processors and, 57
Embedded multiprocessor, 410, 412–413, 432
Embedded programs
components for
circular buffers and stream-oriented programming, 216–221
queues and producer/consumer systems, 221–223
state machines, 214–215
design, 44–45, 120
Embedded system
based on computing platform, 176–185
design flow for, 387f
design process, 10
architecture design, 17–19
behavioral description, 25–28
formalisms for, 20–21
hardware and software components, 19
requirements, 12–16
specification, 16–17
structural description, 21–25
software layer diagram for, 159, 159f
Encode, 140
behavior, 141, 142f
encode() method, 146, 147
Energy consumption, 5, 8, 56, 133, 266, 267f, 269, 452
Energy optimization, 267, 269
Energy vs. power consumption, 133
Engine control unit (ECU)
component design and testing, 373
specification, 370
system
architecture, 371–373
integration and testing, 374
theory of operation and requirements, 369–370
Engine controller, 46, 310–311, 369–371, 373–374, 419–420
Enhanced modular IO subsystem (eMIOS), 373
Enqueueing, 222
Entry point, 233, 234f
Environmental development, embedded systems, 9
Error correction code (ECC), 28, 202
in compact disc, 452
Error correction data byte, 32
Error delimiter field, 418
Error handling, 418
Error injection, 280
Ethernet, 180, 185, 426–429, 426f
packet format, 428, 428f
Evaluation board, 176, 180, 181
Exceptions, 90, 115, 123, 150
Exchangeable Image File Format (EXIF), 291, 291f
Executable binary file, 229
Execute packet, 89
Execution path, 130, 254, 256, 258–259, 272
Execution time, 130–132, 254–256, 254f, 258, 268
accelerator, 435, 436f
execv() function, 353
External memory interface (EMIF), 89
External reference, 233, 234f

F

Fast Fourier transform (FFT), 201
Fast interrupt requests (FIQs), 112
Fast-return mode, 113
Fax machine, 2
Federated network, 422
Fetch packets, 89
Field-programmable gate arrays (FPGAs), 19, 433, 444, 446
designing of, 449
File allocation table (FAT), 187
File display/selection, state diagram for, 203, 204f
File systems, 187–188, 202
File Transport Protocol (FTP), 430
FileID class, 202
Finite impulse response (FIR) filter, 68, 216, 218
for ARM, 68
in C, 219–220
on C55x, 87
on PIC16F microprocessor, 76
Finite-state machine, 214
First-level cache, 118
Flash file systems, 188, 202
Flash memory, 158, 174, 187, 188
FlexRay network, 419
Floating-point operations, 255
Flow of control, 240, 240f
in ARM processor, 66–72
instructions, 84–86, 130
in PIC16F microprocessor, 76–77
Flush, 140
Foreground program, 102, 105, 107, 198
fork() function, 352, 353
Formatter class, 34, 37, 38f, 39
Four-cycle handshake, 160, 161f, 167
Fragmentation, 124
Frame, 64, 71, 202
Frame pointer (FP), 64–65, 71, 243
Freescale MPC5676R, 421
Frequency-shift keying (FSK), 280, 281f
Front panel module, 366
Functional requirements, 12, 185–186, 390, 405
Functional tests
code coverage of, 280f
evaluating, 279–280

G

Generalization relationship, UML, 24
General-purpose computer, 2, 58
performance in, 9
Genesis Platform, 422
Global Interrupt Enable (GIE) bit, 113
Global Positioning System (GPS), 5
moving map, 15, 16t, 17f, 18f
receiver, 19
specification of, 17
Graph
coloring, 249, 249f
matrix representation of, 274f
theory, 274

H

H1 standard, 429
Hardware, 8
block diagram, 18
co-design, 432
design methodology, 386f
designing components, 19
Hardware abstraction layer (HAL), 159
Harvard architectures, 52, 52f, 53
HD video coprocessor subsystem (HDVICP2), 431
HD video processing subsystem (HDVPSS), 432
Heterogeneous shared memory multiprocessors, 431–432
Hierarchical design flows, 386, 387
High Speed Ethernet (HSE), 429
High-level programming language, 224, 320
High-performance processors, 6
Hit rate, 117, 118, 120
Host, 432
system, 179, 180f
use case of synchronizing with, 186f
HP-35, 2
Huffman coding, 289
for text compression, 138
technique, 137
Hypertext Transport Protocol (HTTP), 430

I

I2C bus, 422–426, 422f, 424f
Idle mode, power, 136
if statement, ARM, 66
Image sensors, 286
Immediate operands, 60
Incidence matrix, 274
In-circuit emulator (ICE), 182
Indirect addresses, 82
Induction variable, 262, 263
Initiation interval, 313
Initiation time, 312, 312f
Input and output (I/O) programming
busy-wait devices, 99–100
devices, 96–98, 96f, 178
interrupts
and buffers, 103
and subroutines, 107
basics, 101–107
debugging code, 106
in ARM, 112–113
in C55x, 113
in PIC16F, 113–114
overhead, 111–112
power-down, 109
priorities and vectors, 107–111, 108f, 111f
primitives, 98–99
with prioritized interrupts, 110
Input symbols, data compressor, 137
input_handler, 105
Insert behavior, 141, 142f
insert method, 149
Instruction data byte, 32
Instruction execution, 54, 88, 130
Instruction scheduling, reservation table for, 251, 252f
Instruction sets, 43, 96, 115, 116, 123
characteristics of, 53
Instruction space, PIC16F microprocessor, 73, 74f
Instruction-level simulator, 260
INT External Interrupt Enable bit, 114
INTCON register, 113
Integrated project management, 387
Intel 4004, 2
Intel Strong ARM SA-1100 and SA-1111, system organization of, 158
Intellectual property (IP), 179
Interconnection network, see Networks
Interface, 22, 36f
ACPI, 351
CPU, 433
electrical, 422
EMIF, 89
I2C, 425, 426
motor, 35, 36f, 37
PCI, 449
telephone, 366
user, 5, 15, 202, 206, 366
Inter-instruction dependencies, 56
Internal consistency of requirements, 14
International Standards Organization (ISO), 402, 414
Internet, 429–430
Internet Protocol (IP), 429, 429f, 430f
Internetworking, 429
Interprocess communication mechanisms
mailboxes, 343–344
message passing, 341–342
shared memory communication, 340–341
signals, 342–343
Interrupt requests (IRQs), 112
Interrupt service routine (ISR), 345, 347
Interrupts, 79, 86, 90, 352, 426
acknowledge signal, 101
and buffers, 103
and subroutines, 107
basics, 101–107
debugging code, 106
handler, 184, 200
routine, 101
in ARM, 112–113
in C55x, 113
in PIC16F, 113–114
overhead, 111–112
power-down, 109
priorities and vectors, 107–111, 108f, 111f
registers control, 79
request signal, 101
WinCE, 360
I/O programming, see Input and output programming
io_buf, 105

J

Jitter, 313
Jog memory, 453
Joint Photographic Experts Group (JPEG) images, compression process for, 288, 288f
Jump instruction, 228

L

L1 cache, 118
L2 cache, 118
Large-scale embedded system design, 46
Laser focus, compact disc, 451, 451f, 452f
Latency, 114, 128, 344, 345, 352, 436
LDMIA, 129
Leakage, CMOS, 133
Light-emitting diodes (LEDs), 182
Line replaceable units (LRUs), 421
Linkage mechanism, 242
Linker, 233
Linking process, 233–235
Links, 25, 25f
Linux, 352
Little-endian mode vs. big-endian mode, 54, 58f
Load behavior, 141
Load map file, 234
Loader, 229
Local Interconnect Network (LIN) bus, 419
Logic analyzer, 182, 183, 183f, 255, 260
Loop fusion, 246
Loop tiling, 246, 247f
Loop-back testing, 285
Loops, 85
distribution, 297
nest, 264
optimizations, 262–264
testing, 278
unrolling, 245
Lossless compression methods, 287
Lossy compression algorithm, 287
Luminance, 285–286

M

Machine-independent optimizations, 237
Macroblocks, 441
Manufacturing cost, 5, 12, 14
MAPS_SHARED parameter, 356
Masking, 109, 201
Measurement-driven performance analysis, 259–261
Mechanical systems of car, 419
Media Oriented Systems Transport (MOST) bus, 419
Memory
access times, 190
aspect ratio, 190, 191f
channels and banks in, 174, 175f
controllers, 174, 174f
devices, 172–175
map, C55x DSPs, 79
mapping, 123
organization, 172, 172f, 174–175
ARM processor and, 58
C55x DSPs and, 78–80
PIC16F microprocessor and, 73
system performance, 117
Memory management units (MMUs), 116
and address translation
ARM, 117, 127
memory mapping, 123
segments and pages, 124, 124f, 125, 125f
TLB, 126
Memory system mechanisms
cache
ARM, 122
controllers, 117
direct-mapped vs. set-associative, 121
in memory system, 117f
memory system performance, 117
microprocessor architectures, 116
organization, 118
set-associative, 120, 120f
two-level system, 118, 118f
MMUs, 116
Memory-mapped I/O, ARM, 98
Message passing, 341–342
shared memory vs., 412
Methodological techniques, 280
Microcontroller, 3, 53, 157, 310, 426
I2C bus interface on, 425, 426f
Microprocessor, 1, 6–7, 44, 255
architectures, 116, 270
bus, 160, 170
busses, 160
cost of, 410
cyber-physical system, 7–8
embedding computers, 2–4
ICE, 182
in-circuit emulator, 182
system bus configurations, 170–172
Miss rate, 117
Mock-up, 13
Model train controller, 28, 29f
conceptual specification, 32–35
DCC, 30–32
detailed specification, 35–41
requirements for, 29–30
Motion estimator, architectures for, 446, 447, 447f
Motion vector, 443, 447
Motion-based coding, 441
Motor interface class, 35
Motor speed controlling, pulse-width modulation, 36f
Move instruction, 83
Moving map, block diagram for, 17, 17f
MP3 player, see Audio player
MPC5676R, 421
MPEG Layer 1
decoder, 202, 202f
encoder, 201, 201f
MPEG-2 video compression, 441, 442f
Multimedia, 185
operations, 72
use case for playing, 186f
Multiple inheritance, UML, 24, 24f
Multiple processes, 308–310
timing requirements on, 311–315
Multiple tasks, 308–310
Multiple timers, 318
Multiple-issue instruction, 54
Multiply instructions, 84
Multiprocessor, 10, 47, 409–411, 412f
categories of, 412–414
Multiprocessor system-on-chip (MPSoC), 412, 431–441
Multirate behavior, 5
Multirate communication, 315
Multirate systems, 310–319
Multitasking system, 10
Multithreaded system, 434, 435f, 438f

N

Named resources, 331
NEON, 72
Nested function calls and stacks, 70, 70f
Nested loop, 262
Networks, 47, 409–411
abstractions, 414–416
New-symbol-table, 140
Nodes, 218, 226, 239, 249, 414, 416, 422
Ethernet, 427
Nonfunctional requirements, 12, 186, 390
Nonmaskable interrupt (NMI), 109
Non–object-oriented implementation, 146
Nonrecurring engineering (NRE) costs, 12
Nonrepeatable instructions, 85

O

Object-oriented design, 20, 21
processes and, 324–325
using C++, 142
Object-oriented modeling language, 20
Object-oriented programming, 21
Object-oriented specification, 20, 21
Objects
code, 228
design, 235–236
file format, 233
UML notation, 21, 21f
Off-hook, 362
On-chip memory, 89
One-byte transmissions, 424
One-dimensional array, 244f
On-hook, 362
Open source platforms, 176
Open Systems Interconnection (OSI) models, 414–415
Operating system (OS), 45–46, 159, 179, 187, 307, 316
performance evaluating
interrupt latency, 345
ISH, 346
ISR, 345, 347
POSIX, 352–357
RTOS, 347
process and scheduling states, 316–317
Optical disc technology, 449
Optimization techniques, 214, 236
ORG statements, 230
Outgoing message (OGM), 363
Output pulse width and frequency modulation buffered mode (OPWFMB), 373
Output symbols, data compressor, 137
output_handler, 105
Overhead interrupt, 111–112
Oxygen sensor (OX), 311, 371

P

Packet transmission rates, 32
Packets, 32
Internet, 429
VLIW, 56
Page fault, 123
Page mode access, 173, 190
Page pointers, data and peripheral, 79
Page table, 125, 126f
Pages, address translation, 124, 124f, 126f
Panel class, 36
Panel-activate behavior, 40f
PCI interface, designing of, 449
peek function, 99
busy-wait I/O, 100
read/write operation, 100
Perceptual coding, 201
Performance measures, 255
Performance optimization strategies, 265–266
Periodic processes, 317–319
Peripheral Interrupt Enable (PEIE) bit, 113
Peripheral page pointers, 79
Personal computers (PCs), 7
Phase detection, 286
Physical address, 125
Physical interface classes, 364
Physical layer, 415, 416, 422
Physical performance measurement, 260
PIC16F, 51, 73–77
interrupts in, 113–114
pipeline, 130
PIC16F882 microcontroller, system organization of, 157
PIC16F microprocessor, 51
and memory organization, 73
FIR filter on, 76
flow of control in, 76–77
Picture-taking process, 292, 293f
sequence diagram for, 293, 295f
pipe() function, 356
Pipeline, 254
ARM7, 128, 129f
PIC16F, 130
RISC machines, 128
stalls, 129
Platform-level performance analysis, 188–192, 188f
Platforms, 7, 10, 44
smartphones as, 7
Playback-msg behaviors, 367f
Pointer registers, auxiliary and coefficient data, 79
poke function, 99
busy-wait I/O, 100
read/write operation, 100
Polled processes, 339
Polling, 99, 109f
POSIX, 352–357
message queues, 357
pipes, 356
real-time scheduling in, 354
semaphores, 355
Post-indexing, 65, 66
Power consumption, 5, 8, 13, 15, 19, 266, 349
CPU, 133–137
Power embedded computing, multiprocessing for, 410
Power management policy, 349, 351
Power state machine, 135
Power supply voltage, 28, 133
Power vs. energy consumption, 133
Power-down interrupts, 109
Power-down mode, 134–135
Power-managed system, 350f
PowerPC 603, energy efficiency, 134
Predictive shutdown, 349
Preexisting systems, 405, 406
Presentation layer, 415
Primary avionics software system (PASS), 314
Prioritized interrupts, 108, 108f
I/O with, 110
Priority inversion, 332–333
Priority-based scheduling, 325–340, 354
EDF, 333–337
priority inversion, 332–333
RMS, 326–330, 337
shared resources, 330–332
Procedure calls, in ARM, 71
Procedure linkage, 70, 242, 243–244
Process priorities, 321
Process states, 316–317
Processing element (PE), 409, 410, 431, 432
Processor interrupt latency, 345
Producer/consumer systems, 221–223, 223f
Product metrics, 382
Profiling, 260
Program counter (PC), 52, 59, 60, 64, 73, 74, 78, 230, 260
and control flow, 78
Program execution time, 256, 265
Program generation, compilation, 229f
Program location counter (PLC), 230
Program performance, 43, 255
elements of, 256–259
Program size, analysis and optimization, 270–271
Program trace, 259
Program-level energy, 266–269
Program-level performance analysis
execution time, 254, 254f
measurement-driven performance analysis, 259–261
performance measures, types of, 255
program performance, elements of, 256–259
Programmability of microprocessors, 7
Programming model, 59–60
Programs, 10
controlling and observing, 272–273
embedded, 214–223
models of, 223–228
performance measures on, 255
Prototypes, 405, 406
Prototyping languages, 405
Pseudo-ops, 55
Pulser class, 35–36
Pulse-width modulation, 36f
PWR_EN signal, 136

Q

Quality assurance (QA), 400–407
techniques, 402–404
Quantization matrix, 289
Queues, 221–223, 342

R

RAM set, 122
Random tests, 279
Random values, 279
Random-access memory, 172
Rate-monotonic analysis (RMA), 326–330
Rate-monotonic scheduling (RMS), 326–330, 337
Reachability analysis, 246
read_handler, 107
Read-only memories (ROMs), 174
Real time performance, 5, 7, 10, 189, 410, 430
Real-time code, timing error in, 183–184
Real-time computing, 9
Real-time operating systems (RTOS), 45, 307, 339
example of, POSIX, 352–357
preemptive operating system, 319–325
basic concepts, 320–321
object-oriented design, 324–325
processes and context, 321–324
Real-time operations, 2
Ethernet, 428
Real-time performance, 410
Receiver class, 34, 37, 37f
Recessive, 416
Record-msg behaviors, 367f
Reduced instruction set computers (RISC)
machines, 128
vs. CISC, 53
Reed-Solomon coding, 452
Reentrant, 235
Register allocation, 247
problem solving, 249
Register indirect addressing, in ARM, 62, 63f
Registers
control interrupts, 79
of C55x DSPs, 78, 80f
Regression tests, 279
Relative addresses, 229
Relative code, 233
Reliability, 9
Relocatable program, 236
Remote frames, 418
Remote transmission request (RTR) bit, 417
Requirements analysis, 389–390
Requirements form, 13, 13f
Reservation table, instruction scheduling, 251, 252f
RETFIE instruction, 114
Round nodes, 224
Round-robin scheduling, 325
Router, 429
Row major, 244
Run mode, power, 136

S

Saved program status register (SPSR), 114–115
Scaffolding code, 149
SCHED_OTHER, 354
SCHED_RR, 354
Scheduling overhead, 309f, 317, 411f
Scheduling policy, 317, 327, 337, 344, 354, 374
Scheduling processes, 438–441
Scheduling states, 316–317
Second-level cache, 118
Segments, address translation, 124–125, 124f, 125f
Semaphores, 331, 344, 355
Send-command method, 37
Sender classes, 34
Sequence diagram, 27, 28f, 41f, 162f, 293, 295f, 320f, 321f, 345f, 360f, 446f
for control input transmitting, 38f
in UML, 27, 28f
Serial clock line (SCL), 422
Serial communications program, parameters for, 97
Serial data line (SDL), 422
language, 391
Servo control algorithms, 452
Session layer, 415
Set-associative cache, 120, 120f
direct-mapped vs., 121
Set-speed command, 41f
SGS Thomson chip, 3
Shared memory multiprocessors, 431
heterogeneous, 431–432
Shared memory vs. message passing, 412
Sharpening algorithms, 287
Signal flow graph, 218, 218f, 219
Signal, in UML, 26, 26f
Signal processing algorithms, 279
Simple Mail Transfer Protocol (SMTP), 430
Simple Network Management Protocol (SNMP), 430
Single in-line memory modules (SIMMs), 174
Single repeat registers, 79
Single threaded system, 434, 435f, 438f
Single-assignment form, 224, 224f
Single-chip
computer, 54
CPUs, 2, 3
platform, 157
Single-instruction multiple-data (SIMD) operations, 72
Single-issue processor, 54
16-bit DSP processor, 204
16-bit microcontroller, 3
Skip-if instructions, 130
Sleep mode, power, 136–137
Slow-return mode, 113
Smartphones as platforms, 7
Society of Automotive Engineers (SAE), 373
Software
block diagram, 18
co-design, 432
design methodology, 386f
designing components, 19
interrupt, 115
physics of, 8
pipelining, 251
scaffolding, 259
Software engineers, 382
Software modem, 45
architecture of, 283–284
class diagram for, 283f
component design and testing, 283–284
design of, 280–285
integration and testing, 285
operation and requirements, 280–282
Software performance optimization
cache optimizations, 264–265
loop optimizations, 262–264
strategies, 265–266
Software testing, techniques, 400, 403
Source code, 45, 224, 230, 271
types of, 223
SP, see Stack pointer
Space shuttle software error, 314
Speaker module, 366
Specification languages, 405, 406
Speedup, 434, 436–437
Spiral model, 383, 384f, 385
Stack operations, 83
Stack, PC, 74
Stack pointer (SP), 71, 74, 78, 243, see also Frame pointer (FP)
Standard data flow graph, 225f
Start signal, 424
State machines, 25, 27, 27f, 214–215
State mode, 182–183
Statecharts, 391
AND state in, 393f
OR state in, 392f
Static power management mechanism, 134
Static scheduling policy, 326
Status registers, 74, 96
of C55x DSPs, 78
Stereotypes, in UML, 25
Stop signal, 424
Streaming data, 53, 428, 437
Stream-oriented programming, 216–221
Strength reduction, 263, 264
StrongARM SA-1100, power-saving modes, 136
Structural description, 21–25
Subroutines, 77, 85, 107, 270, 317
Subscriber line, 362
Successive refinement design methodology, 385, 385f
Superscalar processor, 54, 56
vs. VLIW processor, 57
Supervisor mode, 114–115
SWI, 200
interrupt, 115
Symbol table, 140, 148, 230, 230f, 231
Synchronous channels, 419
Synchronous dynamic RAM (SDRAM), 173, 173f
Synchronous interrupts, 113, 114
latency of, 114
System design techniques
design flows, 383–389
design methodologies, 381–389
design reviews, 406–407
specification, verifying, 404–406
techniques, 402–404
requirements analysis, 389–390
specifications, 390–395
advanced specifications, 394–395
control-oriented specification languages, 391–394
system analysis and architecture design, CRC cards, 396–400
System integration, 19–20
DSC, 296
testing and, 200, 206, 285, 296, 368–369, 374
System requirements
validating, 13
vs. specifications, 12
System speedup, 437, 438f
System testing, DSC, 296
System-on-chip, 54
vs. distributed system, 412

T

Table attribute, 140
Tagged Image File Format (TIFF), 290
Target system, 179, 180f
Task, 10
graph, 315
set, 315
Telephone
input modules, 366
line module, 366
output modules, 366
systems, 388
Telephone answering machine, design
component design and testing, 368
specification, 364–366
system architecture, 366–368
system integration and testing, 368–369
theory of operation and requirements, 361–364
Template matching, code generation by, 252, 253f
Temporary registers, 79
Test generation programs, 403
Testbench program, 180
Testing, 148, 149f
of embedded computer, 9
video algorithms, 449
Therac-25 medical imaging system, 401
32-bit RISC microprocessor, 3, 204
Threads, 308, 358–359
Throttle settings, 311
Thumbnail, 291
TI C64x, 43, 87–90
TI TMS320DM816x DaVinci, 431
Time quantum, 320
Time-out event, 26f, 27
Timer, 198, 200, 255, 260, 318–322
Time-sharing system, 235
Timing mode, 182–183
TMR0 Overflow Interrupt Enable bit, 113
Top down design, 11
Traffic alert and collision avoidance system (TCAS), 394
Train controller commands, 32, 33f
refining, 39, 42f
Transition registers, 79
Translation lookaside buffer (TLB), 126
Transmission Control Protocol (TCP), 430
Transmission controller, 419–420
Transmitter class, 34, 37, 37f
Transmitting node, 418
Transport layer, 415
Traps, 115, 116
TrustZone, 72
Two-dimensional arrays, 244, 245f
Type certification, 421

U

Unified cache, 122
Unified Modeling Language (UML), 20–22, 33, 34f, 324, 343, 447
active objects, 324
collaboration diagram, 33f, 138f
multiple inheritance in, 24, 24f
object in, 21f
sequence diagram, 27, 28f, 105
sequence, of DMA transfer, 169f
state and transition in, 26f
state diagram, of bus bridge operation, 171f
Universal Asynchronous Receiver/Transmitter (UART) 8251, 97–98, 341
Universal Serial Bus (USB), 157, 180, 186
port, 181
Unrolled schedules, 327, 335
Usage scenarios, 398, 400, 406
User Datagram Protocol (UDP), 430
User interface, 5, 15, 18, 186, 195, 199, 202, 206
classes for alarm clock, 195f
of MP3 player, 202
User mode, 90, 114, 358

V

Value nodes, 224
Variable data rates, 309
VDD power supply, 136
VDD_FAULT, 136
VDDX power supply, 136
Vectors interrupt, 86, 108, 111f, 235
Very large scale integration (VLSI), 2, 6, 410
Very-long instruction word (VLIW) processor, 54, 56–57
vs. superscalar, 57
Video accelerator
algorithm and requirements, 443–444
architecture, 446–447
component design, 449
compression, 441–444
specification for, 445–446
Video compression, 441–444
Virtual addressing, 123, 123f
Virtual memory, 126, 357
von Neumann architectures, 52, 52f

W

Wait states, 165, 165f, 189
Waterfall model, 383, 384f, 385, 404
While loop, 100, 199, 226, 228f, 272–273
Windows CE, 347, 357–361
architecture, 357
interrupts, 360
memory space, 357
scheduling, 359
threads and drivers, 358
Word length, 53
Working set, 117, 118
Worst-case execution time, 255, 259
analysis, 259
Writable CDs, 454
Write-back policy, 119
Write-through scheme, 119

X

Xilinx Zynq-7000 platform, 434
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