Average current-mode control of the 12-pulse rectifier

For comparison purposes, a PI-based controller structure is designed (Fig. 35.36B), taking into account that small mismatches of the line voltages or of the trigger angles can completely destroy the current share of the four paralleled rectifiers, in spite of the current equalizing inductances (l and l′). Output voltage control sensing only the output voltage is, therefore, not feasible. Instead, the slow and fast manifold approach is selected. For the fast manifold, four internal current control loops guarantee the same dc current level in each three-phase rectifier and limit the short-circuit currents. For the output slow dynamics, an external cascaded output voltage control loop (Fig. 35.36B), measuring the voltage applied to the load, is the minimum.

For a straightforward design, given the much slower dynamics of the capacitor voltages compared with the input current, the PI current controllers are calculated as shown in Example 35.6, considering the capacitor voltage constant during a switching period and r_t≈1 Ω the intrinsic resistance of the transformer windings, thyristor overlap, and inductor l. From Eq. (35.59), T_z=l/r_t≈0.044 s. From Eq. (35.62), with the common assumptions, T_p≈0.16 k_I s (p=3). These values guarantee a small overshoot (≈5%) and a current rise time of approximately T/3.

To design the external output voltage control loop, each current-controlled rectifier can be considered a voltage-controlled current source $i_{L_1}\left(s\right)/4$, since each half-wave rectifier current response will be much faster than the filter output voltage response. Therefore, in the equivalent circuit of Fig. 35.35B, the current source ${i_L}_{{}_1}\left(s\right)$ substitutes the input inductor, yielding the transfer function $v_{c_2}\left(s\right)/{i_L}_{{}_1}\left(s\right)$:

$\frac{V_{c_2}\left(s\right)}{i_{L_1}\left(s\right)}=\frac{R_o}{C_2{C}_1{L}_2{R}_o{s}^3+C_1{L}_2{s}^2+\left(C_2{R}_o+C_1{R}_o\right)s+1}$

Given the real pole (p₁=−6.7) and two complex poles (p_2,3=−6.65±j140.9) of Eq. (35.126), the PI voltage controller zero (1/T_zv=p₁) can be chosen with a value equal to the transfer function real pole. The integral gain T_pv can be determined using a root-locus analysis to determine the maximum gain that still guarantees the stability of the closed-loop controlled system. The critical gain for the PI was found to be T_zv/T_pv≈0.4 and then T_pv>0.37. The value T_pv≈2 was selected to obtain weak oscillations, together with almost no overshoot.

The dynamic and steady-state responses of the output currents of the four rectifiers $\left(i_{l_1},i_{l_2},i_{l_3},i_{l_4}\right)$ and the output voltage $V_{c_2}$ were analyzed using a step input from 2 to 2.5 A applied at t=1.1 s, for the currents, and from 40 to 50 V for the $V_{c_2}$ voltage. The PI current controllers (Fig. 35.37) show good sharing of the total current, slight overshoot (ζ=0.7), and response time 6.6 ms (T/p).

The open-loop voltage $V_{c_2}$ presents a rise time of 0.38 s. The PI voltage controller (Fig. 35.38) shows a response time of 0.4 s, no overshoot. The four three-phase half-wave rectifier output currents $\left(i_{l_1},i_{l_2},i_{l_3},\mathrm{and}{i}_{l_4}\right)$ present nearly the same transient and steady-state values, with no very high current peaks. These results validate the assumptions made in the PI design.

The closed-loop performance of the fixed-frequency sliding-mode controller (Fig. 35.39) shows that all the $i_{l_1},i_{l_2},i_{l_3},\mathrm{and}{i}_{l_4}$ currents are almost equal and have peak values only slightly higher than those obtained with the PI linear controllers. The output voltage presents a much faster response time (150 ms) than the PI linear controllers, negligible or no steady-state error, and no overshoot. From these waveforms, it can be concluded that the sliding-mode controller provides a much more effective control of the rectifier, as the output voltage response time is much lower than the obtained with PI linear controllers, without significantly increasing the thyristor currents, overshoots, or costs. Furthermore, sliding mode is an elegant way to know the variables to be measured and to design all the controller and the modulator electronics.

Modeling the PWM audio amplifier

The two half-bridge switches must always be in complementary states, to avoid power supply internal short circuits. Their state can be represented by the time-dependent variable γ, which is γ=1 when Q1 is on and Q2 is off, and is γ=−1 when Q1 is off and Q2 is on.

Neglecting switch delays, on-state semiconductor voltage drops, and auxiliary networks and supposing small dead times, the half-bridge output voltage (v_PWM) is v_PWM=γV_dd. Considering the state variables and circuit components of Fig. 35.40 and modeling the loudspeaker load as a disturbance represented by the current i_o (ensuring robustness to the frequency -dependent impedance of the speaker), the switched state-space model of the PWM audio amplifier is

$\begin{array}{l}\frac{\mathrm{d}}{\mathrm{d}t}\left[\begin{array}{c}{i}_{L_1}\\ v_{c_1}\\ i_{L_2}\\ v_o\end{array}\right]=\left[\begin{array}{cccc}-r_1/L_1& -1/L_1& 0& 0\\ 1/C_1& 0& -1/C_1& 0\\ 0& 1/L_2& 0& -1/L_2\\ 0& 0& 1/C_2& 0\end{array}\right]\left[\begin{array}{c}{i}_{L_1}\\ v_{c_1}\\ i_{L_2}\\ v_o\end{array}\right]\\ +\left[\begin{array}{cc}1/L_1& 0\\ 0& 0\\ 0& 0\\ 0& -1/C_2\end{array}\right]\left[\begin{array}{c}\gamma V_{dd}\\ i_o\end{array}\right]\end{array}$

This model will be used to define the output voltage v_o controller.

Sliding-mode control of the PWM audio amplifier

The filter output voltage v_o, divided by the amplifier gain (1/k_v), must follow a reference $v_{o_r}$. Defining the output error as $e_{v_o}=v_{o_r}-k_v{v}_o$ and also using its time derivatives (e_θ, e_γ, and e_β) as a new state vector $\mathbf{e}={\left[e_{v_o},e_{\theta },e_{\gamma },e_{\beta }\right]}^{\mathrm{T}}$, the system equations, in the phase canonical (or controllability) form, can be written in the form

$\begin{array}{l}\frac{\mathrm{d}}{\mathrm{d}t}{\left[e_{v_o},e_{\theta },e_{\gamma },e_{\beta }\right]}^{\mathrm{T}}=[e_{\theta },e_{\gamma },e_{\beta }-f\left(e_{v_o},e_{\theta },e_{\gamma },e_{\beta }\right)+p_e\left(t\right)\\ -\gamma V_{dd}/C_1{L}_1{C}_2{L}_2]{}^{\mathrm{T}}\end{array}$

Sliding-mode control of the output voltage will enable a robust and reduced-order dynamics, independent of semiconductors, power supply, filter, and load parameters. According to Eqs. (35.91) and (35.128), the sliding surface is

$\begin{array}{l}S\left(e_{v_o},e_{\theta },e_{\gamma },e_{\beta },t\right)=e_{v_o}+k_{\theta }{e}_{\theta }+k_{\gamma }{e}_{\gamma }+k_{\beta }{e}_{\beta }\\ =v_{o_r}-k_v{v}_o+k_{\theta }\frac{\mathrm{d}\left(v_{o_r}-k_v{v}_o\right)}{\mathrm{d}t}\\ +k_{\gamma }\frac{\mathrm{d}}{\mathrm{d}t}\left(\frac{\mathrm{d}\left(v_{o_r}-k_v{v}_o\right)}{\mathrm{d}t}\right)\\ +k_{\beta }\frac{\mathrm{d}}{\mathrm{d}t}\left[\frac{\mathrm{d}}{\mathrm{d}t}\left(\frac{\mathrm{d}\left(v_{o_r}-k_v{v}_o\right)}{\mathrm{d}t}\right)\right]=0\end{array}$

In sliding mode, Eq. (35.129) confirms the amplifier gain $\left(v_o/v_{o_r}=1/kv\right)$. To obtain a stable system and the smallest possible response time t_r, a pole placement according to a third-order Bessel polynomial is used. Taking t_r inversely proportional to a frequency just below the lowest cutoff frequency (ω₁) of the double LC filter (t_r≈2.8/ω₁≈2.8/(2π×21 kHz)≈20 μs) and using Eq. (35.88) with m=3, the characteristic polynomial Eq. (35.130), verifying the Routh-Hurwitz criterion, is obtained:

$S\left(\mathbf{e},s\right)=1+s{t}_r+\frac{6}{15}{\left(s{t}_r\right)}^2+\frac{1}{15}{\left(s{t}_r\right)}^3$

From Eq. (35.97), the switching law for the control input at time t_k, γ(t_k), must be

$\gamma \left(t_k\right)=sgn\left\{S\left(\mathrm{e},t_k\right)+\varepsilon sgn\left[S\left(\mathrm{e},t_{k-1}\right)\right]\right\}$

To ensure reaching and existence conditions, the power supply voltage V_dd must be greater than the maximum required mean value of the output voltage in a switching period $V_{dd}>\left(\overline{v_{\mathit{PWMmax}}}\right)$. The sliding-mode controller (Fig. 35.41) is obtained from Eqs. (35.129)–(35.131) with k_θ=t_r, $k_{\gamma }=6t_r^2/15,k_{\beta }=t_r^3/15$. The derivatives can be approximated by the block diagram of Fig. 35.41B, where h is the oversampling period.

Fig. 35.42A shows the v_PWM, $v_{o_r}$, v_o/10, and error $10\times \left(v_{o_r}-v_o/10\right)$ waveforms for a 20 kHz sine input. The overall behavior is much better than the obtained with the sigma-delta controllers (Figs. 35.43 and 35.44) explained below for comparison purposes. There is no 0.5 dB loss or phase delay over the entire audio band; the Chebyshev filter behaves as a maximally flat filter, with higher stopband attenuation. Fig. 35.42B shows v_PWM, $v_{o_r}$, and $10\times \left(v_{o_r}-v_o/10\right)$ with a 1 kHz square input. There is almost no steady-state error and almost no overshoot on the speaker voltage v_o, attesting to the speed of response (t≈20 μs as designed, since, in contrast to Example 35.12, no derivatives were neglected). The stability, the system order reduction, and the sliding-mode controller usefulness for the PWM audio amplifier are also shown.

Sigma delta controlled PWM audio amplifier

Assume now the fourth-order Chebyshev low-pass filter, as an ideal filter removing the high-frequency content of the v_PWM voltage. Then, the v_PWM voltage can be considered as the amplifier output. However, the discontinuous voltage v_PWM=γV_dd is not a state variable and cannot follow the almost continuous reference $v_{PW{M}_r}$. The new error variable $e_{\mathit{vPWM}}=v_{PW{M}_r}-k_v\gamma V_{dd}$ is always far from the zero value. Given this nonzero error, the approach outlined in Section 35.3.4 can be used. The switching law remains Eq. (35.131), but the new control law Eq. (35.132) is

$S\left({e_v}_{PVM},t\right)=k{\displaystyle \int \left(v_{PW{M}_r}-k_v\gamma V_{dd}\right)dt=0}$

The κ parameter is calculated to impose the maximum switching frequency f_PWM. Since $\mathrm{\kappa }{\int }_0^{1/2f_{{}_{PWM}}}\left({v_{PWM}}_{{}_{r\mathit{max}}}+k_v{V}_{dd}\right)\mathrm{d}t=2\varepsilon$, we obtain

$f_{PWM}=\mathrm{\kappa }\left(v_{PW{M}_{\mathit{rmax}}}+k_v{V}_{dd}\right)/4\varepsilon$

Assuming that $v_{PW{M}_r}$ is nearly constant over the switching period 1/f_PWM, Eq. (35.132) confirms the amplifier gain, since $\overline{v_{PWM}}=v_{PW{M}_r}/k_v$.

Practical implementation of this control strategy can be done using an integrator with gain κ (κ≈1800) and a comparator with hysteresis ɛ (ɛ≈6 mV) (Fig. 35.43A). Such an arrangement is called a first-order sigma-delta (ΣΔ) modulator.

Fig. 35.44A shows the v_PWM, v_or, and v_o/10 waveforms for a 20 kHz sine input. The overall behavior is as expected, because the practical filter and loudspeaker are not ideal, but notice the 0.5 dB loss and phase delay of the speaker voltage v_o, mainly due to the output filter and speaker inductance. In Fig. 35.44B, the v_PWM, $v_{o_r}$, v_o/10, and error $10\times \left(v_{o_r}-v_o/10\right)$ for a 1 kHz square input are shown. Note the oscillations and steady-state error of the speaker voltage v_o, due to the filter dynamics and double termination.

A second-order sigma-delta modulator is a better compromise between circuit complexity and signal-to-quantization noise ratio. As the switching frequency of the two power MOSFET (Fig. 35.40) cannot be further increased, the second-order structure named “cascaded integrators with feedback” (Fig. 35.43B) was selected and designed to eliminate the step response overshoot found in Fig. 35.44B.

Fig. 35.45A, for 1 kHz square input, shows much less overshoot and oscillations than Fig. 35.44B. However, the v_PWM, $v_{o{}_r}$, and v_o/10 waveforms, for a 20 kHz sine input presented in Fig. 35.45B, show increased output voltage loss, compared to the first-order sigma-delta modulator, since the second-order modulator was designed to eliminate the v_o output voltage ringing (therefore reducing the amplifier bandwidth). The obtained performances with these and other sigma-delta structures are inferior to the sliding-mode performances (Fig. 35.42). Sliding mode brings definite advantages as the system order is reduced, flatter passbands are obtained, power supply rejection ratio is increased, and the nonlinear effects, together with the frequency-dependent phase delays, are canceled out.

Modeling the three phase PWM boost rectifier

Neglecting switch delays and dead times, the states of the switches of the kth inverter leg (Fig. 35.46) can be represented by the time-dependent nonlinear variables γ_k, defined as

${\gamma }_k=\left\{\begin{array}{l}1>\mathrm{if}S{\mathrm{u}}_k\mathrm{is}\mathrm{on}\mathrm{and}S{\mathrm{l}}_k\mathrm{is}\mathrm{off}\\ 0>\mathrm{if}S{\mathrm{u}}_k\mathrm{is}\mathrm{off}\mathrm{and}S{\mathrm{l}}_k\mathrm{is}\mathrm{on}\end{array}\right.$

Consider the displayed variables of the circuit (Fig. 35.46), where L is the value of the boost inductors, R their resistance, C the value of the output capacitor, and R_c its equivalent series resistance (ESR). Neglecting semiconductor voltage drops, leakage currents, and auxiliary networks, the application of Kirchhoff laws (taking the load current i_o as a time-dependent perturbation) yields the following switched state-space model of the boost rectifier:

$\begin{array}{l}\frac{\mathrm{d}}{\mathrm{d}t}\left[\begin{array}{c}{i}_1\\ i_2\\ i_3\\ v_o\end{array}\right]=\left[\begin{array}{cccc}-R/L& 0& 0& \left(-2{\gamma }_1+{\gamma }_2+{\gamma }_3\right)/\left(3L\right)\\ 0& -R/L& 0& \left(-2{\gamma }_2+{\gamma }_3+{\gamma }_1\right)/\left(3L\right)\\ 0& 0& -R/L& \left(-2{\gamma }_3+{\gamma }_1+{\gamma }_2\right)/\left(3L\right)\\ A_{41}& A_{42}& A_{43}& A_{44}\end{array}\right]\left[\begin{array}{c}{i}_1\\ i_2\\ i_3\\ v_o\end{array}\right]\\ +\left[\begin{array}{ccccc}1/L& 0& 0& 0& 0\\ 0& 1/L& 0& 0& 0\\ 0& 0& 1/L& 0& 0\\ {\gamma }_1{R}_c/L& {\gamma }_2{R}_c/L& {\gamma }_3{R}_c/L& -1/C& -R_c\end{array}\right]\left[\begin{array}{c}{v}_1\\ v_2\\ v_3\\ i_o\\ \mathrm{d}{i}_o/\mathrm{d}t\end{array}\right]\end{array}$

$\begin{array}{l}\mathrm{where}{A}_{41}={\gamma }_1\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),A_{42}={\gamma }_2\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),A_{43}={\gamma }_3\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),\hfill \\ A_{44}=\frac{-2R_c\left({\gamma }_1\left({\gamma }_1-{\gamma }_2\right)+{\gamma }_2\left({\gamma }_2-{\gamma }_3\right)+{\gamma }_3\left({\gamma }_3-{\gamma }_1\right)\right)}{3L}\hfill \end{array}$

Since the input voltage sources have no neutral connection, the preceding model can be simplified, eliminating one equation. Using the relationship (35.136) between the fixed frames x₁, 2, 3, and x_α,β, in Eq. (35.135), the state-space model (35.137), in the α,β frame, is obtained:

$\left[\begin{array}{l}{x}_1\hfill \\ x_2\hfill \end{array}\right]=\left[\begin{array}{cc}\hfill \sqrt{2/3}\hfill & \hfill 0\hfill \\ \hfill -\sqrt{1/6}\hfill & \hfill \sqrt{1/2}\hfill \end{array}\right]\left[\begin{array}{c}{x}_{\alpha }\\ x_{\beta }\end{array}\right]$

$\begin{array}{c}\frac{\mathrm{d}}{\mathrm{d}t}\left[\begin{array}{c}{i}_{\alpha }\\ i_{\beta }\\ v_o\end{array}\right]=\left[\begin{array}{ccc}-R/L& \omega & -{\gamma }_{\alpha }/L\\ 0& -R/L& -{\gamma }_{\alpha }/L\\ A_{31}^{\alpha }& A_{32}^{\alpha }& A_{33}^{\alpha }\end{array}\right]\left[\begin{array}{c}{i}_{\alpha }\\ i_{\beta }\\ v_o\end{array}\right]\\ +\left[\begin{array}{cccc}1/L& 0& 0& 0\\ 0& 1/L& 0& 0\\ {\gamma }_{\alpha }{R}_c/L& {\gamma }_{\beta }{R}_c/L& -1/C& -R_c\end{array}\right]\left[\begin{array}{c}{v}_{\alpha }\\ v_{\beta }\\ i_o\\ \mathrm{d}{i}_o/\mathrm{d}t\end{array}\right]\end{array}$

$\begin{array}{l}\mathrm{where}{A}_{31}^{\alpha }={\gamma }_{\alpha }\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),A_{32}^{\alpha }={\gamma }_{\beta }\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),\\ A_{33}^{\alpha }=\frac{-R_c\left({\gamma }_{\alpha }^2+{\gamma }_{\beta }^2\right)}{L}\end{array}$

Sliding-mode control of the PWM rectifier

The model (35.137) is nonlinear and time-variant. Applying the Park transformation (35.138), using a frequency ω rotating reference frame synchronized with the mains (with the q component of the supply voltages equal to zero), the nonlinear, time-invariant model (35.139) is written as

$\left[\begin{array}{c}{i}_{\alpha }\\ i_{\beta }\end{array}\right]=\left[\begin{array}{cc}cos\left(\omega t\right)& -sin\left(\omega t\right)\\ sin\left(\omega t\right)& cos\left(\omega t\right)\end{array}\right]\left[\begin{array}{c}{i}_d\\ i_q\end{array}\right]$

$\begin{array}{l}\frac{d}{dt}\left[\begin{array}{c}\hfill i_d\hfill \\ \hfill i_q\hfill \\ \hfill v_o\hfill \end{array}\right]=\left[\begin{array}{ccc}\hfill -R/L\hfill & \hfill \omega \hfill & \hfill -{\gamma }_d/L\hfill \\ \hfill -\omega \hfill & \hfill -R/L\hfill & \hfill -{\gamma }_q/L\hfill \\ \hfill A_{31}^d\hfill & \hfill A_{32}^d\hfill & \hfill A_{33}^d\hfill \end{array}\right]\left[\begin{array}{c}\hfill i_d\hfill \\ \hfill i_q\hfill \\ \hfill v_o\hfill \end{array}\right]\\ +\left[\begin{array}{cccc}\hfill 1/L\hfill & \hfill 0\hfill & \hfill 0\hfill & \hfill 0\hfill \\ \hfill 0\hfill & \hfill 1/L\hfill & \hfill 0\hfill & \hfill 0\hfill \\ \hfill {\gamma }_d{R}_c/L\hfill & \hfill {\gamma }_q{R}_c/L\hfill & \hfill -1/C\hfill & \hfill -R{}_c\hfill \end{array}\right]\left[\begin{array}{c}\hfill v_d\hfill \\ \hfill v_q\hfill \\ \hfill i_o\hfill \\ \hfill d{i}_{o}dt\hfill \end{array}\right]\end{array}$

$\begin{array}{l}\mathrm{where}{A}_{31}^d={\gamma }_d\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),A_{32}^d={\gamma }_q\left(\frac{1}{C}-\frac{R{R}_c}{L}\right),\\ A_{33}^d=\frac{-R_c\left({\gamma }_d^2+{\gamma }_q^2\right)}{L}\end{array}$

This state-space model can be used to obtain the feedback controllers for the PWM boost rectifier. Considering the output voltage v_o and the i_q current as the controlled outputs and γ_d and γ_q the control inputs (MIMO system), the input-output linearization of Eq. (35.72) gives the state-space equations in the controllability canonical form (35.140):

$\begin{array}{c}\frac{\mathrm{d}{i}_q}{\mathrm{d}t}=-\omega i_d-\frac{R}{L}{i}_q-\frac{{\gamma }_q}{L}{v}_o+\frac{1}{L}{v}_q\\ \frac{\mathrm{d}{v}_o}{\mathrm{d}t}=\theta \end{array}$

$\begin{array}{l}\frac{\mathrm{d}\theta }{\mathrm{d}t}=\frac{R+R_c\left({\gamma }_d^2+{\gamma }_q^2\right)}{L}\theta -\frac{{\gamma }_d^2+{\gamma }_q^2}{LC}{v}_o\\ +\frac{{\gamma }_d{v}_d+{\gamma }_q{v}_q}{LC}-\frac{R{i}_o}{LC}-\left(\frac{1}{C}+\frac{R{R}_c}{L}\right)\frac{\mathrm{d}{i}_o}{\mathrm{d}t}\\ +\omega \left(\frac{1}{C}-\frac{R{R}_c}{L}\right)\left({\gamma }_d{i}_q-{\gamma }_d{i}_q\right)-R_c\frac{{\mathrm{d}}^2{i}_o}{\mathrm{d}{t}^2}\end{array}$

where

$\begin{array}{l}\theta =\left(\frac{1}{C}-\frac{R{R}_c}{L}\right)\left({\gamma }_d{i}_d+{\gamma }_q{i}_q\right)-\frac{R_c\left({\gamma }_d^2+{\gamma }_q^2\right)}{L}{v}_o\\ +\frac{R_c}{L}\left({\gamma }_d{v}_d+{\gamma }_q{v}_q\right)-\frac{i_o}{C}-R_c\frac{\mathrm{d}{i}_o}{\mathrm{d}t}\end{array}$

Using the rectifier overall power balance (from Tellegen's theorem, the converter is conservative, i.e., the power delivered to the load or dissipated in the converter intrinsic devices equals the input power) and neglecting the switching and output capacitor losses, $v_d{i}_d+v_q{i}_q=v_o{i}_o+R{i}_d^2$. Supposing unity power factor (i_qr≈0) and the output v_o at steady state, ${\gamma }_d{i}_d+{\gamma }_q{i}_q\approx i_o,v_d=\sqrt{3}{V}_{RMS},v_q=0,{\gamma }_q\approx v_q/v_o,{\gamma }_d\approx \left(v_d-R{i}_d\right)/v_o$. Then, from Eqs. (35.140) and (35.91), the following two sliding surfaces can be derived:

$S_q\left(e_{i_q},t\right)=k_{e_{i_q}}\left(i_{qr}-i_q\right)=0$

$\begin{array}{l}{S}_d\left(e_{v_o},e_{\theta },t\right)\approx \left[{\beta }^{-1}\left(v_{o_r}-v_o\right)+\frac{\mathrm{d}{v}_{o_r}}{\mathrm{d}t}+\frac{1}{C}{i}_o+R_c\frac{\mathrm{d}{i}_o}{\mathrm{d}t}\right]\\ \times \frac{LC}{L-CR{R}_c}\frac{v_o}{\sqrt{3}{V}_{RMS}-R{i}_d}-i_d=i_{d_r}-i_d=0\end{array}$

where β⁻¹ is the time constant of the desired first-order response of output voltage v_o (β≫T>0). For the synthesis of the closed-loop control system, notice that the terms of Eq. (35.142) inside the square brackets can be assumed as the i_d reference current $i_{d_r}$. Furthermore, from Eqs. (35.141) and (35.142), it is seen that the current control loops for i_d and i_q are needed. Considering Eqs. (35.138) and (35.136), the two sliding surfaces can be written as

$S_{\alpha }\left(e_{i_{\alpha }},t\right)=i_{{\alpha }_r}-i_{\alpha }=0$

$S_{\beta }\left(e_{i_{\beta }},t\right)=i_{{\beta }_r}-i_{\beta }=0$

The switching laws relating the sliding surfaces (35.143) and (35.144) with the switching variables γ_k are

$\left\{\begin{array}{l}\begin{array}{l}\mathrm{if}{S}_{\alpha \beta }\left(e_{i{}_{\alpha \beta }},t\right)>\varepsilon \mathrm{then}{i}_{\alpha {\beta }_r}>i_{\alpha \beta }\mathrm{hence}\mathrm{choose}{\gamma }_k\mathrm{t}\mathrm{o}\\ \mathrm{increase}\mathrm{the}{i}_{\alpha \beta }\mathrm{current}\end{array}\hfill \\ \begin{array}{l}\mathrm{if}{S}_{\alpha \beta }\left(e_{i_{\alpha \beta }},t\right)<-\varepsilon \mathrm{then}{i}_{\alpha {\beta }_r}>i_{\alpha \beta }\mathrm{hence}\mathrm{choose}{\gamma }_k\mathrm{t}\mathrm{o}\\ \mathrm{decrease}\mathrm{the}{i}_{\alpha \beta }\mathrm{current}\end{array}\hfill \end{array}\right.$

The practical implementation of this switching strategy could be accomplished using three independent two-level hysteresis comparators. However, this might introduce limit cycles as only two line currents are independent. Therefore, the control laws (35.143) and (35.144) can be implemented using the block diagram of Fig. 35.47A, with d, q/α, and β (from Eq. (35.138)) and 1,2,3/α, and β (from Eq. (35.136)) transformations and two three-level hysteretic comparators with equivalent hysteresis ɛ and ρ to limit the maximum switching frequency. A limiter is included to bound the i_d reference current to i_dmax, keeping the input line currents within a safe value. This helps to eliminate the nonminimum-phase behavior (outside sliding mode) when large transients are present while providing short-circuit proof operation.

α, β space vector current modulator

Depending on the values of γ_k, the bridge rectifier leg output voltages can assume only eight possible distinct states represented as voltage vectors in the α and β reference frame (Fig. 35.47B), for sources with isolated neutral.

With only two independent currents, two three-level hysteresis comparators, for the current errors, must be used in order to accurately select all eight available voltage vectors. Each three-level comparator [16] can be obtained by summing the outputs of two comparators with two levels each. One of these two comparators (δ_Lα and δ_Lβ) has a wide hysteresis width, and the other (δ_Nα and δ_Nβ) has a narrower hysteresis width. The hysteresis bands are represented by ɛ and ρ. Table 35.1 represents all possible output combinations of the resulting four two-level comparators, their sums giving the two three-level comparators (δ_α and δ_β), plus the voltage vector needed to accomplish the current tracking strategy $\left(i_{\alpha ,{\beta }_r}-i_{\alpha ,\beta }\right)=0$ (ensuring $\left(i_{\alpha ,{\beta }_r}-i_{\alpha ,\beta }\right)\times d\left(i_{\alpha ,{\beta }_r}-i_{\alpha ,\beta }\right)/dt<0$, plus the γ_k variables and the α and β voltage components).

From the analysis of the PWM boost rectifier, it is concluded that, if, for example, the voltage vector 2 is applied (γ₁=1, γ₂=1, and γ₃=0), in boost operation, the currents i_α and i_β will both decrease. Oppositely, if the voltage vector 5 (γ₁=0, γ₂=0, and γ₃=1) is applied, the currents i_α and i_β will both increase. Therefore, vector 2 should be selected when both i_α and i_β currents are above their respective references, that is, for δ_α=−1, δ_β=−1, whereas vector 5 must be chosen when both i_α and i_β currents are under their respective references or, for δ_α=1, δ_β=1. Nearly all the outputs of Table 35.2 can be filled using this kind of reasoning.

Table 35.2

Two-level and three-level comparator results, showing corresponding vector choice, corresponding γk and vector α and β component voltages; vectors are mapped in Fig. 35.47B

δLα	δNα	δLβ	δNβ	δα	δβ	Vector	γ1	γ2	γ3	vα	vβ
−0.5	−0.5	−0.5	−0.5	−1	−1	2	1	1	0	$v_o/\sqrt{6}$	$v_o/\sqrt{2}$
0.5	−0.5	−0.5	−0.5	0	−1	2	1	1	0	$v_o/\sqrt{6}$	$v_o/\sqrt{2}$
0.5	0.5	−0.5	−0.5	1	−1	3	0	1	0	$-v_o/\sqrt{6}$	$v_o/\sqrt{2}$
−0.5	0.5	−0.5	−0.5	0	−1	3	0	1	0	$-v_o/\sqrt{6}$	$v_o/\sqrt{2}$
−0.5	0.5	0.5	−0.5	0	0	0 or 7	0 or 1	0 or 1	0 or 1	0	0
0.5	0.5	0.5	−0.5	1	0	4	0	1	1	$-\sqrt{2/3}{v}_o$	0
0.5	−0.5	0.5	−0.5	0	0	0 or 7	0 or 1	0 or 1	0 or 1	0	0
−0.5	−0.5	0.5	−0.5	−1	0	1	1	0	0	$\sqrt{2/3}{v}_o$	0
−0.5	−0.5	0.5	0.5	−1	1	6	1	0	1	$v_o/\sqrt{6}$	$-v_o/\sqrt{2}$
0.5	−0.5	0.5	0.5	0	1	6	1	0	1	$v_o/\sqrt{6}$	$-v_o/\sqrt{2}$
0.5	0.5	0.5	0.5	1	1	5	0	0	1	$-v_o/\sqrt{6}$	$-v_o/\sqrt{2}$
−0.5	0.5	0.5	0.5	0	1	5	0	0	1	$-v_o/\sqrt{6}$	$-v_o/\sqrt{2}$
−0.5	0.5	−0.5	0.5	0	0	0 or 7	0 or 1	0 or 1	0 or 1	0	0
0.5	0.5	−0.5	0.5	1	0	4	0	1	1	$-\sqrt{2/3}{v}_o$	0
0.5	−0.5	−0.5	0.5	0	0	0 or 7	0 or 1	0 or 1	0 or 1	0	0
−0.5	−0.5	−0.5	0.5	−1	0	1	1	0	0	$\sqrt{2/3}{v}_o$	0

In the cases where δ_α=0 and δ_β=−1, the vector is selected upon the value of the i_α current error (if δ_Lα>0 and δ_Nα<0, then vector 2 and if δ_Lα<0 and δ_Nα>0, then vector 3). When δ_α=0 and δ_β=1, if δ_Lα>0 and δ_Nα<0, then vector 6, else if δ_Lα<0 and δ_Nα>0, then vector 5. The vectors 0 and 7 are selected in order to minimize the switching frequency (if two of the three upper switches are on, then vector 7, otherwise vector 0). The space-vector decoder can be stored in a lookup table (or in an EPROM) whose inputs are the four two-level comparator outputs and the logic result of the operations needed to select between vectors 0 and 7.

PI output voltage control of the current-mode PWM rectifier

Using the α and β current-mode hysteresis modulators to enforce the i_d and i_q currents to follow their reference values, $i_{d_r},i_{q_r}$ (the values of L and C are such that the i_d and i_q currents usually exhibit a very fast dynamics compared with the slow dynamics of v_o), a first-order model (35.146) of the rectifier output voltage can be obtained from Eq. (35.73):

$\begin{array}{l}\frac{\mathrm{d}{v}_o}{\mathrm{d}t}=\left(\frac{1}{C}-\frac{R{R}_c}{L}\right)\left({\gamma }_d{i}_{d_r}+{\gamma }_q{i}_{q_r}\right)-\frac{R_c\left({\gamma }_d^2+{\gamma }_q^2\right)}{L}{v}_o\\ +\frac{R_c}{L}\left({\gamma }_d{v}_d+{\gamma }_q{v}_q\right)-\frac{i_o}{C}-R_c\frac{\mathrm{d}{i}_o}{\mathrm{d}t}\end{array}$

Assuming now a pure resistor load R₁=v_o/i_o and a mean delay T_d between the i_d current and the reference $i_{d_r}$, continuous transfer functions result for the i_d current (i_d=i_dr (1+sT d)⁻¹) and for the v_o voltage (v_o=k_Ai_d/(1+sk_B) with k_A and k_B obtained from Eq. (35.146)). Therefore, using the same approach as Examples 35.6, 35.8, and 35.11, a linear PI regulator, with gains K_p and K_i (35.147), sampling the error between the output voltage reference $v_{o_r}$ and the output v_o, can be designed to provide a voltage proportional (k_I) to the reference current $i_{d_r}\left(i_{d_r}=\left(K_p+K_i/s\right)K_I\left(v_{o_r}-v_o\right)\right)$:

$\begin{array}{l}{K}_p=\frac{R_1+R_c}{4{\zeta }^2{T}_d{R}_1{K}_1{\gamma }_d\left(1/C-R{R}_c/L\right)}\\ K_i=\frac{R_c\left({\gamma }_d^2+{\gamma }_q^2\right)/L+1/\left(R_{1}C\right)}{4{\zeta }^2{T}_d{K}_1{\gamma }_d\left(1/C-R{R}_c/L\right)}\end{array}$

These PI regulator parameters depend on the load resistance R₁, on the rectifier parameters (C, R_c, L, and R), on the rectifier operating point γ_d, on the mean delay time T_d, and on the required damping factor ζ. Therefore, the expected response can only be obtained with the nominal load and input voltages, the line current dynamics depending on the K_p and K_i gains.

Results (Fig. 35.48) obtained with the values V_RMS≈70 V, L≈1.1 mH, R≈0.1 Ω, C≈2000 μF with equivalent series resistance ESR≈0.1 Ω (R_c≈0.1 Ω), R₁≈25 Ω, R₂≈12 Ω, β=0.0012, K_p=1.2, K_i=100, and k_I=1 show that the α and β space-vector current modulator ensures the current tracking needed (Fig. 35.48) [17–19]. The v_o step response reveals a faster sliding-mode controller and the correct design of the current-mode/PI controller parameters. The robustness property of the sliding-mode-controlled output v_o, compared with the current mode/PI, is shown in Fig. 35.49.

Sliding-mode surface and switching law

For a variable-structure system where the control input u_i(t) can present n levels, consider the n values of the integer variable γ, being−(n−1)/2≤γ≤(n−1)/2 and u_i(t)=γU_cc/(n−1), dependent on the topology and on the conducting semiconductors. To ensure the sliding-mode manifold invariance condition (35.92) and the reaching mode behavior, the switching strategy γ(t_k+1) for the time instant t_k+1, considering the value of γ(t_k), must be

$\gamma \left(t_{k+1}\right)=\left\{\begin{array}{l}\begin{array}{l}\gamma \left(t_k\right)+1\mathrm{if}S\left(e_{x_i},t\right)>\varepsilon \wedge \stackrel{.}{S}\left(e_{x_i},t\right)\\ >\varepsilon \wedge \gamma \left(t_k\right)<\left(n-1\right)/2\end{array}\hfill \\ \begin{array}{l}\gamma \left(t_k\right)-1\mathrm{if}S\left(e_{x_i},t\right)<-\varepsilon \wedge \stackrel{.}{S}\left(e_{x_i},t\right)\\ <-\varepsilon \wedge \gamma \left(t_k\right)>-\left(n-1\right)/2\end{array}\hfill \end{array}\right.$

This switching law can be implemented as depicted in Fig. 35.53A and for five levels in B. An alternative is shown in Fig. 35.53C and named stability condition-based modulator [20], where the switching law (35.149) is directly used, calculating the sliding-mode surface and its time derivative, implemented as a discrete time variation. They are two-level quantized, and upon their values (obtained by half of their sum), the voltage level is increased (or decreased), until it reaches the maximum (or the minimum). Therefore, the output level is increased (or decreased) if the error and its derivative are both positive (or negative), with the upper limit λ_máx=(n−1)/2 and lower limit λ_min=−(n−1)/2.

Other implementations are possible (Fig. 35.53D), since in every modulation method the generated pulse levels must have the same volt-second average of the fundamental sinusoidal (i.e., the integral over time of the n-level voltage waveform minus the value of the fundamental should be zero).

Control of the output voltage in single-phase multilevel converters

To control the inverter output voltage, in closed-loop and in diode-clamped multilevel inverters with n levels and supply voltage U_cc, a control law similar to Eq. (35.132), $S\left(e_{uo},t\right)=\kappa {\displaystyle \int \left(u_{o_r}-k_v\gamma \left(t_k\right)U_{\mathit{cc}}/\left(n-1\right)\right)dt=0}$, is suitable.

Fig. 35.54A shows the waveforms of a five-level sliding-mode-controlled inverter, namely, the input sinus voltage, the generated output staircase wave, and the sliding-surface instantaneous error. This error is always within a band centered around the zero value and presents zero mean value, which is not the case of sigma-delta modulators followed by n-level quantizers, where the error presents an offset mean value in each half period.

Experimental multilevel converters always show capacitor voltage unbalances (Fig. 35.54B) due to small differences between semiconductor voltage drops and circuitry offsets. To obtain capacitor voltage equalization, the voltage error $\left(v_{c_2}-U_{\mathit{cc}}/2\right)$ is fed back to the controller (Fig. 35.55A) to counteract the circuitry offsets. Experimental results (Fig. 35.54C) clearly show the effectiveness of the correction made. The small steady-state error, between the voltages of the two capacitors, still present, could be eliminated using an integral regulator (Fig. 35.55B).

Fig. 35.56 confirms the robustness of the sliding-mode controller to power supply disturbances.

Output current control in single-phase multilevel converters

Considering an inductive load with current i_L, the control law (35.107) and the switching law of (35.149) should be used for single-phase multilevel inverters. Results obtained using the capacitor voltage equalization principle just described are shown in Fig. 35.57.

Output voltage control in multilevel converters

To guarantee the topological constraints of this converter and the correct sharing of the U_dc voltage by the semiconductors, the switching strategy for the k leg (k∈{1, 2, 3}) must ensure complementary states to switches S_k1 and S_k3. The same restriction applies for S_k2 and S_k4. Neglecting switching delays, dead times, on-state semiconductor voltage drops, snubber networks, and power supply variations; supposing small dead times and equal capacitor voltages U_C1=U_C2=U_dc/2; and using the time-dependent switching variable γ_k(t), the leg output voltage U_k (Fig. 35.58) will be U_k=γ_k(t)U_dc/2, with

${\gamma }_k\left(t\right)=\left\{\begin{array}{l}\begin{array}{ll}1\hfill & \mathrm{if}{S}_{k1}\wedge S_{k2}\mathrm{are}\mathrm{ON}\wedge S_{k3}\wedge S_{k4}\mathrm{are}\mathrm{OFF}\hfill \end{array}\hfill \\ \begin{array}{ll}0\hfill & \mathrm{if}{S}_{k2}\wedge S_{k3}\mathrm{are}\mathrm{ON}\wedge S_{k1}\wedge S_{k4}\mathrm{are}\mathrm{OFF}\hfill \end{array}\hfill \\ \begin{array}{ll}-1\hfill & \mathrm{if}{S}_{k3}\wedge S_{k4}\mathrm{are}\mathrm{ON}\wedge S_{k1}\wedge S_{k2}\mathrm{are}\mathrm{OFF}\hfill \end{array}\hfill \end{array}\right.$

The converter output voltages U_Sk of vector U_S can be expressed as

${\mathrm{U}}_S=\left[\begin{array}{lll}2/3\hfill & -1/3\hfill & -1/3\hfill \\ -1/3\hfill & 2/3\hfill & -1/3\hfill \\ -1/3\hfill & -1/3\hfill & 2/3\hfill \end{array}\right]\left[\begin{array}{l}{\gamma }_1\hfill \\ {\gamma }_2\hfill \\ {\gamma }_3\hfill \end{array}\right]\frac{U_{\mathit{dc}}}{2}$

The application of the Concordia transformation U_S1,2,3=[C] U_{Sα, β, o} (Eq. (35.152) to (35.151))

$\left[\begin{array}{l}{U}_{S1}\\ U_{S2}\\ U_{S3}\end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}1& 0& 1/\sqrt{2}\\ -1/2& \sqrt{3}/2& 1/\sqrt{2}\\ -1/2& -\sqrt{3}/2& 1/\sqrt{2}\end{array}\right]\left[\begin{array}{l}{U}_{S\alpha }\\ U_{S\beta }\\ U_{\mathit{So}}\end{array}\right]$

gives the output voltage vector in the α and β coordinates ${\mathbf{U}}_{S_{\alpha ,\beta }}$:

${\mathbf{U}}_{S_{\alpha ,\beta }}=\left[\begin{array}{c}\hfill U_{s\alpha }\hfill \\ \hfill U_{s\beta }\hfill \end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}\hfill 1\hfill & \hfill -\frac{1}{2}\hfill & \hfill -\frac{1}{2}\hfill \\ \hfill 0\hfill & \hfill \frac{\sqrt{3}}{2}\hfill & \hfill -\frac{\sqrt{3}}{2}\hfill \end{array}\right]\left[\begin{array}{c}\hfill {\Gamma }_1\hfill \\ \hfill {\Gamma }_2\hfill \\ \hfill {\Gamma }_3\hfill \end{array}\right]\frac{U_{\mathit{dc}}}{2}=\left[\begin{array}{c}\hfill {\Gamma }_{\alpha }\hfill \\ \hfill {\Gamma }_{\beta }\hfill \end{array}\right]\frac{U_{\mathit{dc}}}{2}$

where

$\begin{array}{l}\begin{array}{cc}\hfill {\Gamma }_1=\frac{2}{3}{\gamma }_1-\frac{1}{3}{\gamma }_2-\frac{1}{3}{\gamma }_3;\hfill & \hfill {\Gamma }_2=\frac{2}{3}{\gamma }_2-\frac{1}{3}{\gamma }_3-\frac{1}{3}{\gamma }_1;\hfill \end{array}\\ {\Gamma }_3=\frac{2}{3}{\gamma }_3-\frac{1}{3}{\gamma }_1-\frac{1}{3}{\gamma }_2\end{array}$

The output voltage vector in the α and β coordinates ${\mathbf{U}}_{S_{\alpha ,\beta }}$ is discontinuous. A suitable state variable for this output can be its average value ${\overline{\mathbf{U}}}_{S_{\alpha ,\beta }}$ during one switching period:

${\overline{\mathbf{U}}}_{S_{\alpha ,\beta }}=\frac{1}{T}{\int }_0^T{\mathbf{U}}_{S_{\alpha ,\beta }}\mathrm{d}t=\frac{1}{T}{\int }_0^T{\Gamma }_{\alpha ,\beta }\frac{U_{\mathit{dc}}}{2}\mathrm{d}t$

The controllable canonical form is

$\frac{\mathrm{d}}{\mathrm{d}t}{\overline{\mathbf{U}}}_{S_{\alpha ,\beta }}=\frac{{\mathbf{U}}_{S_{\alpha ,\beta }}}{T}=\frac{{\Gamma }_{\alpha ,\beta }}{T}\frac{U_{\mathit{dc}}}{2}$

Considering the control goal ${\overline{\mathbf{U}}}_{S_{\alpha ,\beta }}={\overline{\mathbf{U}}}_{S_{\alpha ,{\beta }_{ref}}}$ and Eq. (35.91), the sliding surface is

$\begin{array}{l}\mathbf{S}\left({\mathbf{e}}_{\alpha ,\beta },t\right)={\displaystyle \sum _{o=1}^{\phi }{\mathbf{k}}_{\alpha {\beta }_o}{\mathbf{e}}_{\alpha ,{\beta }_o}}={\mathbf{k}}_{\alpha ,{\beta }_1}{\mathbf{e}}_{\alpha ,{\beta }_1}={\mathbf{k}}_{\alpha ,{\beta }_1}\left({\overline{\mathbf{U}}}_{S_{\alpha ,{\beta }_{ref}}}-{\overline{\mathbf{U}}}_{S_{\alpha ,\beta }}\right)\\ =\frac{{\mathbf{k}}_{\alpha ,\beta }}{T}{\displaystyle {\int }_0^T\left({\mathbf{U}}_{S_{\alpha ,\mathit{\beta ref}}}-{\mathbf{U}}_{S_{\alpha ,\beta }}\right)}dt=0\end{array}$

To ensure reaching mode behavior and sliding-mode stability (35.92), as the first derivative of Eq. (35.157), $\stackrel{.}{\mathbf{S}}\left({\mathbf{e}}_{\alpha ,\beta },t\right)$ is

$\stackrel{.}{\mathbf{S}}\left({\mathbf{e}}_{\alpha ,\beta },t\right)=\frac{{\mathbf{k}}_{\alpha ,\beta }}{T}\left({\mathbf{U}}_{S_{\alpha ,\mathit{\beta ref}}}-{\mathbf{U}}_{S_{\alpha ,\beta }}\right)$

The switching law is

$\begin{array}{l}\mathbf{S}\left({\mathbf{e}}_{\alpha ,\beta },t\right)>0\Rightarrow \stackrel{.}{\mathbf{S}}\left({\mathbf{e}}_{\alpha ,\beta },t\right)<0\Rightarrow {\mathbf{U}}_{S_{\alpha ,\beta }}>{\mathbf{U}}_{S_{\alpha ,\mathit{\beta ref}}}\hfill \\ \mathbf{S}\left({\mathbf{e}}_{\alpha ,\beta },t\right)<0\Rightarrow \stackrel{.}{\mathbf{S}}\left({\mathbf{e}}_{\alpha ,\beta },t\right)>0\Rightarrow {\mathbf{U}}_{S_{\alpha ,\beta }}<{\mathbf{U}}_{S_{\alpha ,\mathit{\beta ref}}}\hfill \end{array}$

This switching strategy must select the proper values of ${\mathbf{U}}_{S_{\alpha ,\beta }}$ from the available outputs. As each inverter leg (Fig. 35.58) can deliver one of the three possible output voltages (U_dc/2, 0, and−U_dc/2), all the 27 possible output voltage vectors listed in Table 35.3 can be represented in the α and β frame of Fig. 35.59 (in per units, 1 p.u. = U_dc). There are nine different levels for the α space vector component and only five for the β component. However, considering any particular value of α (or β) component, there are at most five levels available in the remaining orthogonal component. From the load viewpoint, the 27 space vectors of Table 35.3 define only 19 distinct space positions (Fig. 35.59).