20.2.1 Regulating Control

The series regulators shown in Figs. 20.5 and 20.6 do not have feedback loop. Although they provide satisfactory performance for many applications, their output resistances and ripples cannot be reduced. Fig. 20.7 shows an improved form of the series regulator, in which negative feedback is employed to improve the performance. In this circuit, transistors Q₃ and Q₄ form a single-ended differential amplifier, and the gain of this amplifier is established by R₆. Here, D_z is a stable zener diode reference, biased by R₄. For higher accuracy, D_z can be replaced by an IC reference such as REF series from Burr-Brown. Resistors R₁ and R₂ form a voltage divider for output voltage sensing. Finally, transistors Q₁ and Q₂ form a Darlington pair output stage. The operation of the regulator can be explained as follows. When Q₁ and Q₂ are on, the output voltage increases, and hence, the voltage V_A at the base of Q₃ also increases. During this time, Q₃ is off and Q₄ is on. When V_A reaches a level that is equal to the reference voltage V_REF at the base of Q₄, the base-emitter junction of Q₃ becomes forward-biased. Some Q₁ base current will divert into the collector of Q₃. If the output voltage V_o starts to rise above V_REF, Q₃ conduction increases to further decrease the conduction of Q₁ and Q₂, which will in turn maintain output voltage regulation. Fig. 20.8 shows another improved series regulator that uses an operational amplifier to control the conduction of the pass transistor.

One of the problems in the design of linear series voltage regulators is the high-power dissipation in the pass transistors. If an excess load current is drawn, the pass transistor can be quickly damaged or destroyed. In fact, under short-circuit conditions, the voltage across Q₂ in Fig. 20.7 will be the input voltage V_i, and the current through Q₂ will be greater than the rated full-load output current. This current will cause Q₁ to exceed its rated SOA unless the current is reduced. In the next section, some current-limiting techniques will be presented to overcome this problem.

20.2.2 Current Limiting and Overload Protection

In some series voltage regulators, overloading causes permanent damage to the pass transistors. The pass transistors must be kept from excessive power dissipation under current overloads or short-circuit conditions. A current-limiting mechanism must be used to keep the current through the transistors at a safe value as determined by the power rating of the transistors. The mechanism must be able to respond quickly to protect the transistor and yet permit the regulator to return to normal operation as soon as the overload condition is removed. One of the current-limiting techniques to prevent current overload, called the constant current-limiting method, is shown in Fig. 20.9A. Current limiting is achieved by the combined action of the components shown inside the dashed line. The voltage developed across the current-limit resistor R₃ and the base-to-emitter voltage of current-limit transistor Q₃ is proportional to the circuit output current I_L. During current overload, I_L reaches a predetermined maximum value that is set by the value of R₃ to cause Q₃ to conduct. As Q₃ starts to conduct, Q₃ shunts a portion of the Q₁ base current. This action, in turn, decreases and limits I_L to a maximum value I_L(max). Since the base-to-emitter voltage V_BE of Q₃ cannot exceed above 0.7 V, the voltage across R₃ is held at this value and I_L(max) is limited to

$I_{\mathrm{L}\left(\max \right)}=\frac{0.7\mathrm{V}}{R_3}$

Consequently, the value of the short-circuit current is selected by adjusting the value of R₃. The voltage-current characteristic of this circuit is shown in Fig. 20.9B.

In many high-current regulators, foldback current limiting is always used to protect against excessive current. This technique is similar to the constant current-limiting method, except that as the output voltage is reduced as a result of load impedance moving toward zero, the load current is also reduced. Therefore, a series voltage regulator that includes a foldback current-limiting circuit has the voltage-current characteristic shown in Fig. 20.10. The basic idea of foldback current limiting, with reference to Fig. 20.11, can be explained as follows. The foldback current-limiting circuit (in dashed outline) is similar to the constant current-limiting circuit, with the exception of resistors R₅ and R₆. At low output current, the current-limit transistor Q₃ is cutoff.

A voltage proportional to the output current I_L is developed across the current-limit resistor R₃. This voltage is applied to the base of Q₃ through the divider network R₅ and R₆. At the point of transition into current limit, any further increase in I_L will increase the voltage across R₃ and hence across R₅, and Q₃ will progressively be turned on. As Q₁ conducts, it shunts a portion of the Q₁ base current. This action, in turn, causes the output voltage to fall. As the output voltage falls, the voltage across R₆ decreases and the current in R₆ also decreases, and more current is shunted into the base of Q₃. Hence, the current required in R₃ to maintain the conduction state of Q₃ is also decreased. Consequently, as the load resistance is reduced, the output voltage and current fall, and the current-limit point decreases toward a minimum when the output voltage is short-circuited. In summary, any regulator using foldback current limiting can have peak load current up to I_L(max). But when the output becomes shorted, the current drops to a lower value to prevent overheating of the series transistors.

20.4.1 Fixed Positive and Negative Linear Voltage Regulators

The 78XX series of regulators provide fixed regulated voltages from 5 to 24 V. The last two digits of the IC part number denote the output voltage of the device. For example, a 7824 IC regulator produces a +24 V regulated voltage at the output. The standard configuration of a 78XX fixed positive voltage regulator is shown in Fig. 20.15. The input capacitor C₁ acts as a line filter to prevent unwanted variations in the input line, and the output capacitor C₂ is used to filter the high-frequency noise that may appear at the output. In order to ensure proper operation, the input voltage of the regulator must be at least 2 V above the output voltage. Table 20.1 shows the minimum and maximum input voltages of the 78XX series fixed positive voltage regulator.

The 79XX series voltage regulator is identical to the 78XX series except that it provides negative regulated voltages instead of positive ones. Fig. 20.16 shows the standard configuration of a 79XX series voltage regulator. A list of 79XX series regulators is provided in Table 20.2. The regulation of the circuit can be maintained as long as the output voltage is at least 2–3 V greater than the input voltage.

20.4.2 Adjustable Positive and Negative Linear Voltage Regulators

The IC voltage regulators are also available in circuit configurations that allow the user to set the output voltage to a desired regulated value. The LM317 adjustable positive voltage regulator, for example, is capable of supplying an output current of more than 1.5 A over an output voltage range of 1.2–37 V. Fig. 20.17 shows how the output voltage of an LM317 can be adjusted by using two external resistors R₁ and R₂. The capacitors C₁ and C₂ have the same function as those in the fixed linear voltage regulator.

As indicated in Fig. 20.17, the LM317 has a constant 1.25 V reference voltage, V_REF, across the output and the adjustment terminals. This constant reference voltage produces a constant current through R₁ regardless of the value of R₂. The output voltage V_o is given by

$V_{\mathrm{o}}=V_{\mathrm{R}\mathrm{E}\mathrm{F}}\left(1+\frac{R_2}{R_1}\right)+I_{\mathrm{a}\mathrm{d}\mathrm{j}}{R}_2$

where I_adj is a constant current into the adjustment terminal and has a value of approximately 50 μA for the LM317. As can be seen from Eq. (20.13), with fixed R₁, V_o can be adjusted by varying R₂.

The LM337 adjustable voltage regulator is similar to the LM317 except that it provides negative regulated voltages instead of positive ones. Fig. 20.18 shows the standard configuration of an LM337 voltage regulator. The output voltage can be adjusted from −1.2 to −37 V, depending on the external resistors R₁ and R₂.

20.4.3 Applications of Linear IC Voltage Regulators

Most IC regulators are limited to an output current of 2.5 A. If the output current of an IC regulator exceeds its maximum allowable limit, its internal pass transistor will dissipate an amount of energy more than it can tolerate. As a result, the regulator will be shutdown.

For applications that require more than the maximum allowable current limit of a regulator, an external pass transistor can be used to increase the output current. Fig. 20.19 illustrates such a configuration. This circuit has the capability of producing higher current to the load but still preserving the thermal shutdown and short-circuit protection of the IC regulator.

A constant current-limiting scheme, as discussed in Section 20.2.2, is implemented by using the transistor Q₂ and the resistor R₂ to protect the external pass transistor Q₁ from excessive current under current-overload or short-circuit conditions. The value of the external current-sensing resistor R₁ determines the value of current at which Q₁ begins to conduct. As long as the current is less than the value set by R₁, the transistor Q₁ is off, and the regulator operates normally as shown in Fig. 20.15. But when the load current I_L starts to increase, the voltage across R₁ also increases. This turns on the external transistor Q₁ and conducts the excess current. The value of R₁ is determined by

$R_1=\frac{0.7\mathrm{V}}{I_{\text{max}}}$

where I_max is the maximum current that the voltage regulator can handle internally.

20.5.1 Single-Ended Isolated Flyback Regulators

An isolated flyback regulator consists of four main circuit elements: a power switch, a rectifier diode, a transformer, and a filter capacitor. The power switch, which can be either a power transistor or a MOSFET, is used to control the flow of energy in the circuit. A transformer is placed between the input source and the power switch to provide dc isolation between the input and the output circuits. In addition to being an energy storage element, the transformer also performs a stepping up or down function for the regulator. The rectifier diode and filter capacitor form an energy transfer mechanism to supply energy to maintain the output voltage of the supply. Note that there are two distinct operating modes for flyback regulators: continuous and discontinuous. However, both modes have an identical circuit. It is only the transformer magnetizing current that determines the operating mode of the regulator. Fig. 20.20A shows a simplified isolated flyback regulator. The associated steady-state waveforms, resulting from a discontinuous-mode operation, are shown in Fig. 20.20B. As shown in the figure, the voltage regulation of the regulator is achieved by a control circuit, which controls the conduction period or duty cycle of the switch, to keep the output voltage at a constant level. For clarity, the schematics and operation of the control circuit will be discussed in a separate section.

20.5.1.2 Continuous-Mode Flyback Regulators

In the continuous-mode operation, the power switch is turned on before all the magnetic energy stored in the secondary winding empties itself. The primary and secondary current waveforms have a characteristic appearance as shown in Fig. 20.21. This mode produces a higher-power capability without increasing the peak currents. During the on-time, the primary current I_p rises linearly from its initial value I_p(0) and is given by

$I_{\mathrm{p}}=I_{\mathrm{p}}\left(0\right)+\frac{V_{\mathrm{i}}{t}_{\mathrm{on}}}{L_{\mathrm{p}}}$

  (20.28)

At the end of the on-time, the primary current reaches a value equal to I_p(pk) and is given by

$I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}=I_{\mathrm{p}}\left(0\right)+\frac{V_{\mathrm{i}}DT}{L_{\mathrm{p}}}$

  (20.29)

In general, $I_{\mathrm{p}}\left(0\right)\gg V_{\mathrm{i}}DT/L_{\mathrm{p}}$; thus, Eq. (20.29) can be written as

$I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}\approx I_{\mathrm{p}}\left(0\right)$

  (20.30)

The secondary current I_s at the instant of turn off is given by

$\begin{array}{c}{I}_{\mathrm{s}\left(\mathrm{p}\mathrm{k}\right)}=\left(\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right)I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}\\ =\left(\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right)\left(I_{\mathrm{p}}\left(0\right)+\frac{V_{\mathrm{i}}DT}{L_{\mathrm{p}}}\right)\\ \approx \left(\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right)I_{\mathrm{p}}\left(0\right)\end{array}$

  (20.31)

This current decreases linearly at the rate of

$\frac{d{I}_{\mathrm{s}}}{dt}=\frac{V_{\mathrm{o}}}{L_{\mathrm{s}}}$

  (20.32)

The output power P_o is equal to V_o times the time average of the secondary current pulses and is given by

$\begin{array}{c}{P}_{\mathrm{o}}=V_{\mathrm{o}}{I}_{\mathrm{s}}\frac{T-t_{\mathrm{on}}}{T}\\ \approx V_{\mathrm{o}}{I}_{\mathrm{s}\left(\mathrm{p}\mathrm{k}\right)}\frac{T-t_{\mathrm{on}}}{T}\end{array}$

  (20.33)

or

$I_{\mathrm{s}\left(\mathrm{p}\mathrm{k}\right)}=\frac{P_{\mathrm{o}}}{V_{\mathrm{o}}\left(1-t_{\mathrm{on}}/T\right)}$

  (20.34)

For an efficiency of η, the input power P_in is

$\begin{array}{c}{P}_{\mathrm{in}}=\frac{P_{\mathrm{o}}}{\eta }\\ =V_{\mathrm{i}}{I}_{\mathrm{p}}\frac{t_{\mathrm{on}}}{T}\\ \approx V_{\mathrm{i}}{I}_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}\frac{t_{\mathrm{on}}}{T}\end{array}$

  (20.35)

or

$I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}=\frac{P_{\mathrm{o}}}{\eta V_{\mathrm{i}}\left(t_{\mathrm{on}}/T\right)}$

  (20.36)

Combining Eqs. (20.31), (20.34), and (20.36) and solving for V_o, we have

$V_{\mathrm{o}}=\left(\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}\right)\frac{\eta V_{\mathrm{i}}D}{1-D}$

  (20.37)

The output voltage at D_max is then

$V_{\mathrm{o}}=\left(\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}\right)\frac{\eta V_{\mathrm{i}\left(\min \right)}{D}_{\text{max}}}{1-D_{\text{max}}}$

  (20.38)

The maximum collector current I_C(max) for the continuous mode is then given by

$\begin{array}{c}{I}_{\mathrm{C}\left(\max \right)}=I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}\\ =\frac{P_{\mathrm{o}}}{\eta V_{\mathrm{i}}{D}_{\text{max}}}\end{array}$

  (20.39)

The maximum collector voltage of Q₁ is the same as that in the discontinuous mode and is given by

$V_{\mathrm{Q}1\left(\max \right)}=V_{\mathrm{i}\left(\max \right)}+\left(\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right)V_{\mathrm{o}}$

  (20.40)

The maximum allowable duty cycle for the continuous mode can be found from Eq. (20.38) and is given by

$D_{\text{max}}=\frac{1}{1+\left(\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}\right)\frac{\eta V_{\mathrm{i}\left(\min \right)}}{V_{\mathrm{o}}}}$

  (20.41)

At the transition from the discontinuous mode to continuous mode (or from continuous mode to discontinuous mode), the relationships in Eqs. (20.27) and (20.38) must hold. Thus, equating these two equations, we have

$V_{\mathrm{i}\left(\min \right)}{D}_{\text{max}}\sqrt{\frac{\eta R_{\mathrm{L}}T}{2L_{\mathrm{p}}}}=\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}\frac{D_{\text{max}}}{1-D_{\text{max}}}\eta V_{\mathrm{i}\left(\min \right)}$

  (20.42)

Solving this equation for L_p to give the critical inductance $L_{{}^{\mathrm{p}\left(\mathrm{limit}\right)}}$, at which the transition occurs, we have

$\begin{array}{c}{L}_{\mathrm{p}\left(\mathrm{limit}\right)}=\frac{1}{2\eta }T{R}_{\mathrm{L}}{\left[\left(1-D_{\text{max}}\right)\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right]}^2\\ =\frac{1}{2\eta }T\frac{V_{\mathrm{o}}^2}{P_{\mathrm{o}}}{\left[\left(1-D_{\text{max}}\right)\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right]}^2\end{array}$

  (20.43)

Replacing V_o with Eq. (20.38) and solving for L_p(limit), we have

$L_{\mathrm{p}\left(\mathrm{limit}\right)}=\frac{1}{2}\eta T\frac{D_{\text{max}}^2{V}_{\mathrm{i}\left(\min \right)}^2}{P_{\mathrm{o}}}$

  (20.44)

Then, for a given D_max, input, and output quantities, the inductance value L_p(limit) in Eq. (20.44) determines the mode of operation for the regulator. If $L_{\mathrm{p}}<L_{\mathrm{p}\left(\mathrm{limit}\right)}$, then the circuit is operated in the discontinuous mode. Otherwise, if $L_{\mathrm{P}}>L_{\mathrm{p}\left(\mathrm{limit}\right)}$, the circuit is operated in the continuous mode.

In designing flyback regulators, regardless of their operating modes, the power switch must be able to handle the peak collector voltage at turnoff and the peak collector currents at turn-on as shown in Eqs. (20.23), (20.25), (20.39), and (20.40). The flyback transformer, because of its unidirectional use of the B-H curve, has to be designed so that it will not be driven into saturation. To avoid saturation, the transformer needs a relatively large core with an air gap in it.

Although the continuous and discontinuous modes have an identical circuit, their operating properties differ significantly. As opposed to the discontinuous mode, the continuous mode can provide higher-power capability without increasing the peak current I_p(pk). It means that, for the same output power, the peak currents in the discontinuous mode are much higher than those operated in the continuous mode. As a result, a higher current rating and, therefore, a more expensive power transistor are needed. Moreover, the higher secondary peak currents in the discontinuous mode will have a larger transient spike at the instant of turnoff. However, despite all these problems, the discontinuous mode is still much more widely used than its continuous-mode counterpart. There are two main reasons. First, the inherently smaller magnetizing inductance gives the discontinuous mode a quicker response and a lower transient output voltage spike to sudden changes in load current or input voltage. Second, the continuous mode has a right-half-plane zero in its transfer function, which makes the feedback control circuit more difficult to design.

The flyback configuration is mostly used in applications with output power below 100 W. It is widely used for high output voltages at relatively low power. The essential attractions of this configuration are its simplicity and low cost. Since no output filter inductor is required for the secondary, there is a significant saving in cost and space, especially for multiple output power supplies. Since there is no output filter inductor, the flyback exhibits high ripple currents in the transformer and at the output. Thus, for higher-power applications, the flyback becomes an unsuitable choice. In practice, a small LC filter is added after the filter capacitor C_F in order to suppress high-frequency switching noise spikes.

As mentioned previously, the collector voltage of the power transistor must be able to sustain a voltage as defined in Eq. (20.23). In cases where the voltage is too high for the transistor to handle, the double-ended flyback regulator shown in Fig. 20.22 may be used. The regulator uses two transistors that are switched on or off simultaneously. The diodes D_R1 and D_R2 are used to restrict the maximum collector voltage to V_i. Therefore, the transistors with a lower voltage rating can be used in the circuit.

20.5.2 Single-Ended Isolated Forward Regulators

Although the general appearance of an isolated forward regulator resembles that of its flyback counterpart, their operations are different. The key difference is that the dot on the secondary winding of the transformer is so arranged that the output diode is forward-biased when the voltage across the primary is positive, that is, when the transistor is on. Energy is thus not stored in the primary inductance as it was for the flyback. The transformer acts strictly as a transformer. An inductive energy storage element is required at the output for proper and efficient energy transfer.

Unlike the flyback, the forward regulator is very suitable for working in the continuous mode. In the discontinuous mode, the forward regulator is more difficult to control because of a double pole at the output filter. Thus, it is not as much used as the continuous mode. In view of it, only the continuous mode will be discussed here.

Fig. 20.23 shows a simplified isolated forward regulator and the associated steady-state waveforms for the continuous-mode operation. Again, for clarity, the details of the control circuit are omitted from the figure. Under steady-state condition, the operation of the regulator can be explained as follows. When the power switch Q₁ turns on, the primary current I_p starts to build up and stores energy in the primary winding. Because of the same polarity arrangement of the primary and secondary windings, this energy is forward transferred to the secondary and onto the L₁C_F filter and the load R_L through the rectifier diode D_R2, which is forward-biased. When Q₁ turns off, the polarity of the transformer winding voltage reverses. This causes D_R2 to turn off and D_R1 and D_R3 to turn on. Now, D_R3 is conducting and delivering energy to R_L through the inductor L₁. During this period, the diode D_R2 and the tertiary winding provide a path for the magnetizing current returning to the input.

When the transistor Q₁ is turned on, the voltage across the primary winding is V_i. The secondary winding current is reflected into the primary, and the reaction current I_p, as shown in Fig. 20.24, is given by

$I_{\mathrm{p}}=\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}{I}_{\mathrm{s}}$

The magnetizing current in the primary has a magnitude of I_mag and is given by

$I_{\mathrm{m}\mathrm{a}\mathrm{g}}=\frac{V_{\mathrm{i}}{t}_{\mathrm{on}}}{L_{\mathrm{p}}}$

The total primary current I_p′ is then

$\begin{array}{c}{I}_{\mathrm{p}}^{\prime }=I_{\mathrm{p}}+I_{\mathrm{m}\mathrm{a}\mathrm{g}}\\ =\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}{I}_s+\frac{V_{\mathrm{i}}{t}_{\mathrm{on}}}{L_{\mathrm{p}}}\end{array}$

The voltage developed across the secondary winding V_s is

$V_{\mathrm{s}}=\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}$

Neglecting diode voltage drops and losses, the voltage across the output inductor is $V_{\mathrm{s}}-V_{\mathrm{o}}$. The current in L₁ increases linearly at the rate of

$I_{\mathrm{L}1}=\frac{\left(V_{\mathrm{s}}-V_{\mathrm{o}}\right)t_{\mathrm{on}}}{L_1}$

At the end of the on-time, the total primary current reaches a peak value equal to I′_p(pk) and is given by

$I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}^{\prime }=I_{\mathrm{p}}^{\prime }\left(0\right)+\frac{V_{\mathrm{i}}DT}{L_{\mathrm{p}}}$

The output inductor current I_L1 is

$I_{\mathrm{L}1\left(\mathrm{p}\mathrm{k}\right)}=I_{\mathrm{L}1}\left(0\right)+\frac{\left(V_{\mathrm{s}}-V_{\mathrm{o}}\right)DT}{L_1}$

At the instant of turn-on, the amplitude of the secondary current has a value of I_s(pk) and is given by

$\begin{array}{c}{I}_{\mathrm{s}\left(\mathrm{p}\mathrm{k}\right)}=\left(\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right)I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}^{\prime }\\ =\left(\frac{N_{\mathrm{p}}}{N_{\mathrm{s}}}\right)\left[I_{\mathrm{p}}^{\prime }\left(0\right)+\frac{V_{\mathrm{i}}DT}{L_{\mathrm{p}}}\right]\end{array}$

During the off-time, the current I_L1 in the output inductor is equal to the current I_DR3 in the rectifier diode D_R3, and both decrease linearly at the rate of

$\begin{array}{c}\frac{d{I}_{\mathrm{L}1}}{dt}=\frac{d{I}_{\mathrm{D}\mathrm{R}3}}{dt}\\ =\frac{V_{\mathrm{o}}}{L_1}\end{array}$

The output voltage V_o can be found from the time integral of the secondary winding voltage over a time equal to DT of the switch Q₁. Thus, we have

$\begin{array}{c}{V}_{\mathrm{o}}=\frac{1}{T}{\displaystyle {\int }_0^{DT}}\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}dt\\ =\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}D\end{array}$

The maximum collector current I_C(max) at turn-on is equal to I′_p(pk) and is given by

$\begin{array}{c}{I}_{\mathrm{C}\left(\max \right)}=I_{\mathrm{p}\left(\mathrm{p}\mathrm{k}\right)}^{\prime }\\ =\left(\frac{N_{\mathrm{s}}}{N_{\mathrm{p}}}\right)\left[I_{\mathrm{p}}^{\prime }\left(0\right)+\frac{V_{\mathrm{i}}DT}{L_{\mathrm{p}}}\right]\end{array}$

The maximum collector voltage $V_{{\mathrm{Q}}_1\left(\max \right)}$ at turnoff is equal to the maximum input voltage V_i(max) plus the maximum voltage V_r(max) across the tertiary winding and is given by

$\begin{array}{c}{V}_{{\mathrm{Q}}_1\left(\max \right)}=V_{\mathrm{i}\left(\max \right)}+V_{\mathrm{r}\left(\max \right)}\\ =V_{\mathrm{i}\left(\max \right)}\left(1+\frac{N_{\mathrm{p}}}{N_{\mathrm{r}}}\right)\end{array}$

The maximum duty cycle for the forward regulator operated in the continuous mode can be determined by equating the time integral of the input voltage when Q₁ is on and the clamping voltage V_r when Q₁ is off.

${\displaystyle \underset{0}{\overset{DT}{\int }}}{V}_{\mathrm{i}}dt={\displaystyle \underset{DT}{\overset{T}{\int }}}{V}_{\mathrm{r}}dt$

that leads to

$V_{\mathrm{i}}DT=V_{\mathrm{r}}\left(1-D\right)T$

Grouping the D terms in Eq. (20.58) and replacing V_r/V_i with N_r/N_p, we have

$D_{\text{max}}=\frac{1}{1+N_{\mathrm{r}}/N_{\mathrm{p}}}$

Thus, the maximum duty cycle depends on the turn ratio between the demagnetizing winding and the primary one.

In designing forward regulators, the duty cycle must be kept below the maximum duty cycle D_max to avoid saturating the transformer. It should also be noted that the transformer magnetizing current must be reset to zero at the end of each cycle. Failure to do so will drive the transformer into saturation, which can cause damage to the transistor. There are many ways of implementing the resetting function. In the circuit shown in Fig. 20.23A, a tertiary winding is added to the transformer so that the magnetizing current will return to the input source V_i when the transistor turns off. The primary current always starts at the same value under the steady-state condition.

Unlike flyback regulators, forward regulators require a minimum load at the output. Otherwise, excess output voltage will be produced. One commonly used method to avoid this situation is to attach a small load resistance at the output terminals. Of course, with such an arrangement, a certain amount of power will be lost in the resistor.

Because forward regulators do not store energy in their transformers, for the same output power level, the transformer can be made smaller than for the flyback type. The output current is reasonably constant owing to the action of the output inductor and the flywheel diode; as a result, the output filter capacitor can be made smaller, and its ripple current rating can be much lower than that required for the flybacks.

The forward regulator is widely used with output power below 200 W, though it can be easily constructed with a much higher output power. The limitation comes from the capability of the power transistor to handle the voltage and current stresses if the output power were to increase. In this case, a configuration with more than one transistor can be used to share the burden. Fig. 20.25 shows a double-ended forward regulator. Like the double-ended flyback counterpart, the circuit uses two transistors that are switched on and off simultaneously. The diodes are used to restrict the maximum collector voltage to V_i. Therefore, the transistors with low voltage rating can be used in the circuit.

20.5.3 Half-Bridge Regulators

The half-bridge regulator is another form of an isolated forward regulator. When the voltage on the power transistor in the single-ended forward regulator becomes too high, the half-bridge regulator is used to reduce the stress on the transistor. In a half-bridge regulator, the voltage stress imposed on the power transistors is subject to only the input voltage and is only half of that in a forward regulator. Thus, the output power of a half bridge is double to that of a forward regulator for the same semiconductor devices and magnetic core.

Fig. 20.26 shows the basic configuration of a half-bridge regulator and the associated steady-state waveforms. As seen in Fig. 20.26A, the half-bridge regulator can be viewed as two back-to-back forward regulators, fed by the same input voltage, each delivering power to the load at each alternate half cycle. The capacitors C₁ and C₂ are placed between the input and ground terminals. As such, the voltage across the primary winding is always half the input voltage. The power switches Q₁ and Q₂ are switched on and off alternatively to produce a square-wave ac at the input of the transformer. This square wave is either stepped down or up by the isolation transformer and then rectified by the diodes D_R1 and D_R2. Subsequently, the rectified voltage is filtered to produce the output voltage V_o.

Under steady-state condition, the operation of the regulator can be explained as follows. When Q₁ is on and Q₂ off, D_R1 conducts and D_R2 is reverse-biased. The primary voltage V_p is V_i/2. The primary current I_p starts to build up and stores energy in the primary winding. This energy is forward transferred to the secondary and onto the L₁C filter and the load R_L, through the rectifier diode D_R1. During the time interval Δ, when both Q₁ and Q₂ are off, D_R1 and D_R2 are forced to conduct to carry the magnetizing current that resulted in the interval during which Q₁ is turned on. The inductor current I_L1 in this interval is equal to the sum of the currents in D_R1 and D_R2. This interval terminates at half of the switching period T, when Q₂ is turned on. When Q₂ is on and Q₁ off, D_R1 is reverse-biased and D_R2 conducts. The primary voltage V_p is now $-V_{\mathrm{i}}/2$. The circuit operates in a likewise manner as during the first half cycle.

With Q₁ on, the voltage across the secondary winding is

$V_{\mathrm{s}1}=\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}\left(\frac{V_{\mathrm{i}}}{2}\right)$

Neglecting diode voltage drops and losses, the voltage across the output inductor is then given by

$V_{\mathrm{L}1}=\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}\left(\frac{V_{\mathrm{i}}}{2}\right)-V_{\mathrm{o}}$

In this interval, the inductor current I_L1 increases linearly at the rate of

$\begin{array}{c}\frac{d{I}_{\mathrm{L}1}}{dt}=\frac{V_{\mathrm{L}1}}{L_1}\\ =\frac{1}{L_1}\left[\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}\left(\frac{V_{\mathrm{i}}}{2}\right)-V_{\mathrm{o}}\right]\end{array}$

At the end of Q₁ on-time, I_L1 reaches a value that is given by

$I_{\mathrm{L}1\left(\mathrm{p}\mathrm{k}\right)}=I_{\mathrm{L}1}\left(0\right)+\frac{1}{L_1}\left[\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}\left(\frac{V_{\mathrm{i}}}{2}\right)-V_{\mathrm{o}}\right]DT$

During the interval Δ, I_L1 is equal to the sum of the rectifier diode currents. Assuming the two secondary windings are identical, I_L1 is given by

$I_{\mathrm{L}1}=2I_{\mathrm{D}\mathrm{R}1}=2I_{\mathrm{D}\mathrm{R}2}$

This current decreases linearly at the rate of

$\frac{d{I}_{\mathrm{L}1}}{dt}=\frac{V_{\mathrm{o}}}{L_1}$

The next half cycle repeats with Q₂ on and for the interval Δ.

The output voltage can be found from the time integral of the inductor voltage over a time equal to T. Thus, we have

$V_{\mathrm{o}}=2\times \frac{1}{T}\left[{\displaystyle \underset{0}{\overset{DT}{\int }}}\left(\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}\left(\frac{V_{\mathrm{i}}}{2}\right)-V_{\mathrm{o}}\right)dt+{\displaystyle \underset{T/2}{\overset{T/2+DT}{\int }}}-V_{\mathrm{o}}dt\right]$

Note that the multiplier of 2 appears in Eq. (20.66) because of the two alternate half cycles. Solving Eq. (20.66) for V_o, we have

$V_{\mathrm{o}}=\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}D$

The output power P_o is given by

$\begin{array}{c}{P}_{\mathrm{o}}=V_{\mathrm{o}}{I}_{\mathrm{L}}\\ =\eta P_{\mathrm{in}}\\ =\eta \frac{V_{\mathrm{i}}{I}_{\mathrm{p}\left(\mathrm{a}\mathrm{v}\mathrm{g}\right)}D}{2}\end{array}$

or

$I_{\mathrm{p}\left(\mathrm{a}\mathrm{v}\mathrm{g}\right)}=\frac{2P_{\mathrm{o}}}{\eta V_{\mathrm{i}}D}$

where I_p(avg) has the value of the primary current at the center of the rising or falling ramp. Assuming the reaction current I_p′ reflected from the secondary is much greater than the magnetizing current, then the maximum collector currents for Q₁ and Q₂ are given by

$\begin{array}{c}{I}_{\mathrm{C}\left(\max \right)}=I_{\mathrm{p}\left(\mathrm{a}\mathrm{v}\mathrm{g}\right)}\\ =\frac{2P_{\mathrm{o}}}{\eta V_{\mathrm{i}}{D}_{\text{max}}}\end{array}$

As mentioned, the maximum collector voltages for Q₁ and Q₂ at turnoff are given by

$V_{\mathrm{C}\left(\max \right)}=V_{\mathrm{i}\left(\max \right)}$

In designing half-bridge regulators, the maximum duty cycle can never be greater than 50%. When both the transistors are switched on simultaneously, the input voltage is short-circuited to ground. The series capacitors C₁ and C₂ provide a dc bias to balance the volt-second integrals of the two switching intervals. Hence, any mismatch in devices would not easily saturate the core. However, if such a situation arises, a small coupling capacitor can be inserted in series with the primary winding. A dc bias voltage proportional to the volt-second imbalance is developed across the coupling capacitor. This balances the volt-second integrals of the two switching intervals.

One problem in using half-bridge regulators is related to the design of the drivers for the power switches. Specifically, the emitter of Q₁ is not at ground level, but is at a high ac level. The driver must therefore be referenced to this ac level. Typically, transformer-coupled drivers are used to drive both switches, thus solving the grounding problem and allowing the controller to be isolated from the drivers.

The half-bridge regulator is widely used for medium-power applications. Because of its core-balancing feature, the half bridge becomes the predominant choice for output power ranging from 200 to 400 W. Since the half bridge is more complex, for application below 200 W, the flyback or forward regulator is considered to be a better choice and more cost-effective. Above 400 W, the primary and switch currents of the half bridge become very high. Thus, it becomes unsuitable.

20.5.4 Full-Bridge Regulators

The full-bridge regulator is yet another form of isolated forward regulator. Its performance is improved over that of the half-bridge regulator because of the reduced peak collector current. The two series capacitors that appeared in half-bridge circuits are now replaced by another pair of transistors of the same type. In each switching interval, two of the switches are turned on and off simultaneously such that the full input voltage appears at the primary winding. The primary and the switch currents are only half that of the half bridge for the same power level. Thus, the maximum output power of this topology is twice that of the half bridge.

Fig. 20.27 shows the basic configuration of a full-bridge regulator and the associated steady-state waveforms. Four power switches are required in the circuit. The power switches Q₁ and Q₄ turn on and off simultaneously in one of the half cycles. Q₂ and Q₃ also turn on and off simultaneously in the other half cycle but with opposite phase as Q₁ and Q₄. This produces a square-wave ac with a value of $\pm V_{\mathrm{i}}$ at the primary winding of the transformer. Like the half bridge, this voltage is stepped down, rectified, and then filtered to produce a dc output voltage. The capacitor C₁ is used to balance the volt-second integrals of the two switching intervals and prevent the transformer from being driven into saturation.

Under steady-state conditions, the operation of the full bridge is similar to that of the half bridge. When Q₁ and Q₄ turn on, the voltage across the secondary winding is

$V_{\mathrm{s}1}=\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}$

Neglecting diode voltage drops and losses, the voltage across the output inductor is then given by

$V_{\mathrm{L}1}=\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}-V_{\mathrm{o}}$

In this interval, the inductor current I_L1 increases linearly at the rate of

$\begin{array}{c}\frac{d{I}_{\mathrm{L}1}}{dt}=\frac{V_{\mathrm{L}1}}{L_1}\\ =\frac{1}{L_1}\left[\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}-V_{\mathrm{o}}\right]\end{array}$

At the end of Q₁ and Q₄ on-time, I_L1 reaches a value that is given by

$I_{\mathrm{L}1\left(\mathrm{p}\mathrm{k}\right)}=I_{\mathrm{L}1}\left(0\right)+\frac{1}{L_1}\left[\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}-V_{\mathrm{o}}\right]DT$

During the interval Δ, I_L1 decreases linearly at the rate of

$\frac{d{I}_{\mathrm{L}1}}{dt}=\frac{V_{\mathrm{o}}}{L_1}$

The next half cycle repeats with Q₂ and Q₃ on, and the circuit operates in a similar manner as in the first half cycle.

Again, as in the half bridge, the output voltage can be found from the time integral of the inductor voltage over a time equal to T. Thus, we have

$V_{\mathrm{o}}=2\times \frac{1}{T}\left[{\displaystyle \underset{0}{\overset{DT}{\int }}}\left(\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}{V}_{\mathrm{i}}-V_{\mathrm{o}}\right)dt+{\displaystyle \underset{T/2}{\overset{T/2+DT}{\int }}}-V_{\mathrm{o}}\mathrm{d}t\right]$

Solving Eq. (20.77) for V_o, we have

$V_{\mathrm{o}}=\frac{N_{\mathrm{s}1}}{N_{\mathrm{p}}}2V_{\mathrm{i}}D$

The output power P_o is given by

$\begin{array}{c}{P}_{\mathrm{o}}=\eta P_{\mathrm{in}}\\ =\eta V_{\mathrm{i}}{I}_{\mathrm{p}\left(\mathrm{a}\mathrm{v}\mathrm{g}\right)}D\end{array}$

or

$I_{\mathrm{p}\left(\mathrm{a}\mathrm{v}\mathrm{g}\right)}=\frac{P_{\mathrm{o}}}{\eta V_{\mathrm{i}}D}$

where I_p(avg) has the same definition as in the half-bridge case.

Comparing Eq. (20.80) with Eq. (20.69), we see that the output power of a full bridge is twice that of a half bridge with same input voltage and current. The maximum collector currents for Q₁, Q₂, Q₃, and Q₄ are given by

$\begin{array}{c}{I}_{\mathrm{C}\left(\max \right)}=I_{\mathrm{p}\left(\mathrm{a}\mathrm{v}\mathrm{g}\right)}\\ =\frac{P_{\mathrm{o}}}{\eta V_{\mathrm{i}}{D}_{\text{max}}}\end{array}$

Comparing Eq. (20.81) with Eq. (20.70), for the same output power, the maximum collector current is only half that of the half bridge.

As mentioned, the maximum collector voltage for Q₁ and Q₂ at turnoff is given by

$V_{\mathrm{C}\left(\max \right)}=V_{\mathrm{i}\left(\max \right)}$

The design of the full bridge is similar to that of the half bridge. The only difference is the use of four power switches instead of two in the full bridge. Therefore, additional drivers are required by adding two more secondary windings in the pulse transformer of the driving circuit.

For high-power applications ranging from several hundred to thousand kilowatts, the full-bridge regulator is an inevitable choice. It has the most efficient use of magnetic core and semiconductor switches. The full bridge is complex and therefore expensive to build and is only justified for high-power applications, typically over 500 W.

20.5.5 Control Circuits and Pulse-Width Modulation

In previous subsections, we presented several popular voltage regulators that may be used in a switching mode power supply. This section discusses the control circuits that regulate the output voltage of a switching regulator by constantly adjusting the conduction period t_on or duty cycle d of the power switch. Such adjustment is called pulse-width modulation (PWM).

The duty cycle is defined as the fraction of the period during which the switch is on, that is,

$\begin{array}{c}d=\frac{t_{\mathrm{on}}}{T}\\ =\frac{t_{\mathrm{on}}}{t_{\mathrm{on}}+t_{\mathrm{off}}}\end{array}$

where T is the switching period, that is, $t_{\mathrm{off}}=T-t_{\mathrm{on}}$. By adjusting either t_on or t_off or both, d can be modulated. Thus, PWM controlled regulators can operate at variable frequency and fixed frequency.

Among all types of PWM controllers, the fixed-frequency controller is by far the most popular choice. There are two main reasons for their popularity. First, low-cost fixed-frequency PWM IC controllers have been developed by various solid-state device manufacturers, and most of these IC controllers have all the features that are needed to build a PWM switching power supply using a minimum number of components. Second, because of their fixed-frequency nature, fixed-frequency controllers do not have the problem of unpredictable noise spectrum associated with variable frequency controllers. This makes EMI control much easier.

There are two types of fixed-frequency PWM controllers, namely, the voltage-mode controller and the current-mode controller. In its simplified form, a voltage-mode controller consists of four main functional components: an adjustable clock for setting the switching frequency, an output voltage error amplifier for detecting deviation of the output from the nominal value, a ramp generator for providing a sawtooth signal that is synchronized to the clock, and a comparator that compares the output error signal with the sawtooth signal. The output of the comparator is the signal that drives the controlled switch. Fig. 20.28 shows a simplified PWM voltage-mode controlled forward regulator operating at fixed frequency and its associated driving signal waveform. As shown, the duration of the on-time t_on is determined by the time between the reset of the ramp generator and the intersection of the error voltage with the positive-going ramp signal.

The error voltage v_e is given by

$v_{\mathrm{e}}=\left(1+\frac{Z_2}{Z_1}\right)V_{\mathrm{R}\mathrm{E}\mathrm{F}}-\frac{Z_2}{Z_1}{v}_2$

From Eq. (20.84), the small-signal term can be separated from the dc operating point by

$\mathrm{\Delta }{v}_{\mathrm{e}}=-\frac{Z_2}{Z_1}\mathrm{\Delta }{v}_2$

The dc operating point is given by

$V_{\mathrm{e}}=\left(1+\frac{Z_2}{Z_1}\right)V_{\mathrm{R}\mathrm{E}\mathrm{F}}-\frac{Z_2}{Z_1}{V}_2$

Inspecting the waveform of the sawtooth and the error voltage shows that the duty cycle is related to the error voltage by

$d=\frac{v_{\mathrm{e}}}{V_{\mathrm{p}}}$

where V_p is the peak voltage of the sawtooth.

Hence, the small-signal duty cycle is related to the small-signal error voltage by

$\mathrm{\Delta }d=\frac{\mathrm{\Delta }{v}_{\mathrm{e}}}{V_{\mathrm{p}}}$

The operation of the fixed-frequency voltage-mode controller can be explained as follows. When the output is lower than the nominal dc value, a high error voltage is produced. This means that Δv_e is positive. Hence, Δd is positive. The duty cycle is increased to cause a subsequent increase in output voltage. The feedback dynamics (stability and transient response) is determined by the operational amplifier circuit that consists of Z₁ and Z₂. Some of the popular voltage-mode control ICs are SG1524/25/26/27, TL494/5, and MC34060/63.

The current-mode control makes use of the current information in a regulator to achieve output voltage regulation. In its simplest form, current-mode control consists of an inner loop that samples the inductance current value and turns the switches off as soon as the current reaches a certain value set by the outer voltage loop. In this way, the current-mode control achieves faster response than the voltage mode. There are two types of fixed-frequency PWM current-mode control, namely, the peak current-mode control and the average current-mode control.

In the peak current-mode control, no sawtooth generator is needed. In fact, the inductance current waveform is itself a sawtooth. The voltage analog of the current may be provided by a small resistance or by a current transformer. Also, in practice, the switch current is used since only the positive-going portion of the inductance current waveform is required. Fig. 20.29 shows a peak current-mode controlled flyback regulator.

In Fig. 20.29, the regulator operates at fixed frequency. Turn-on is synchronized with the clock pulse, and turnoff is determined by the instant at which the input current equals the error voltage V_e.

Because of its inherent peak current-limiting capability, the peak current-mode control can enhance reliability of power switches. The dynamic performance is improved because of the use of the additional current information. One main disadvantage of the peak current-mode control is that it is extremely susceptible to noise, since the current ramp is usually small compared with the reference signal. A second disadvantage is its inherent instability property at duty cycle exceeding 50%, which results in subharmonic oscillation. Typically, a compensating ramp is required at the comparator input to eliminate this instability. The third disadvantage is that it has a nonideal loop response because of the use of the peak, instead of the average current sensing.

Fig. 20.30 shows an average current-mode controlled flyback regulator. In the circuit, a PWM modulator (instead of a clocked SR latch in the peak current-mode control) is employed to compare the current error with an externally generated sawtooth signal to formulate the desired control signal. The main advantages of this method over the peak current control are that it has excellent noise immunity property, it is stable at duty cycle exceeding 50%, and it provides good tracking of average current. However, since there are three compensation networks (Z₁, Z₂, and Z₃), the analysis and optimal design of these networks are nontrivial. This is a major obstacle for adopting the average current-mode control.

It should be noted that current-mode control is particularly effective for the flyback and boost-type regulators that have an inherent right-half-plane zero. Current-mode control effectively reduces the system to first order by forcing the inductor current to be related to the output voltage, thus achieving faster response. In the case of the buck-type regulator, current-mode control presents no significant advantage because the current information can be derived from the output voltage, and hence, faster response can still be achieved with a proper feedback network. Some of the popular current-mode control ICs are UC3840/2, UC3825, MC34129, and MC34065.