13.2.1.1 Advantages

• The number of possible output voltage levels is more than twice the number of dc sources $\left(m=2s+1\right)$.

• The series of H-bridges makes for modularized layout and packaging. This will enable the manufacturing process to be done more quickly and cheaply.

13.2.1.2 Disadvantages

• Separate dc sources are required for each of the H-bridges. This will limit its application to products that already have multiple SDCSs readily available.

Another kind of cascaded multilevel converter with transformers using standard three-phase bilevel converters has been proposed [14]. The circuit is shown in Fig. 13.4. The converter uses output transformers to add different voltages. In order to add up the converter output voltages, the outputs of the three converters need to be synchronized with a separation of ${120}^{\circ }$ between each phase. For example, for obtaining a three-level voltage between outputs a and b, the output voltage can be synthesized by $V_{\mathrm{ab}}=V_{\mathrm{a}1-\mathrm{b}1}+V_{\mathrm{b}1-\mathrm{a}2}+V_{\mathrm{a}2-\mathrm{b}2}$. An isolated transformer is used to provide voltage boost. With three converters synchronized, the voltages, $V_{\mathrm{a}1-\mathrm{b}1},V_{\mathrm{b}1-\mathrm{a}2},V_{\mathrm{a}2-\mathrm{b}2}$, are all in phase, and thus, the output level can be tripled [1].

The advantage of the cascaded multilevel converters with transformers using standard three-phase bilevel converters is that the three converters are identical, and thus, control is more simple. However, the three converters need separate dc sources, and a transformer is needed to add up the output voltages.

13.2.2.1 Advantages

• All the phases share a common dc bus, which minimizes the capacitance requirements of the converter. For this reason, a back-to-back topology is not only possible but also practical for uses such as a high-voltage back-to-back interconnection or an adjustable speed drive.

• The capacitors can be precharged as a group.

• Efficiency is high for fundamental frequency switching.

13.2.2.2 Disadvantages

• Real power flow is difficult for a single inverter because the intermediate dc levels will tend to overcharge or discharge without precise monitoring and control.

• The number of clamping diodes required is quadratically related to the number of levels, which can be cumbersome for units with a high number of levels.

13.2.3.1 Advantages

• Phase redundancies are available for balancing the voltage levels of the capacitors.

• Real and reactive power flow can be controlled.

• The large number of capacitors enables the inverter to ride through short duration outages and deep voltage sags.

13.2.3.2 Disadvantages

• Control is complicated to track the voltage levels for all of the capacitors. Also, precharging all of the capacitors to the same voltage level and start-up is complex.

• Switching utilization and efficiency is poor for real power transmission.

• The large number of capacitors is both more expensive and bulky than clamping diodes in multilevel diode-clamped converters. Packaging is also more difficult in inverters with a high number of levels.

13.2.4.1 Advantages

• The number of SMs in each arm depends on the HVDC voltage level and individual IGBT device voltage. For example, with N series-connected SMs per arm, voltage rating of devices is reduced to V_dc/N (V_dc is dc link voltage), which eliminates the direct series connection of devices in two- and three-level converters. Given that the IGBT ratings are in kV level and HVDC rating is typically in hundreds of kV, often several hundred SMs are used for one MMC [54].

• Higher quality output voltage. With higher number of SMs in each arm (N), the output phase voltage of MMC becomes much more sinusoidal, which enables smaller ac filters, lower cost and compact converter footprint, as illustrated in Fig. 13.14.

• Lower switching frequency and higher efficiency. The series connection of N SMs per arm can achieve an equivalent switching frequency of Nf_c (f_c represents carrier frequency of each device) in the output voltage. In practical applications, the device average switching frequency is generally below 200 Hz. Consequently, state-of-the-art MMC-HVDC has loss level about 1%, close to that of LCC.

• Lower high-frequency noise due to reduced dv/dt and di/dt.

• Modular design and inherent redundancy. The modular design of MMC contributes to lower cost, shorter manufacturing as well as maintenance period, and high extensibility for higher voltage and power applications. Furthermore, the system becomes more reliable since failed SMs can be easily replaced by redundant ones [55].

The comparison of site footprint, building area, and building volumes for LCC-HVDC (Grita project, 500 MW and 400 kV), two-level VSC-HVDC, and half-bridge MMC-HVDC (EWIC project, 500 MW and ±200 kV) is presented in Table 13.3, using the Grita project as the 100% reference [56]. Different from LCC-HVDC, the converter reactors and dc yard equipment in VSC-HVDC are mounted in converter buildings, which provide more convenient maintenance, improved personal safety, lower high-frequency emissions and acoustic noise, and protection for equipment from adverse weather.

Without the requirement for reactive power compensation, the overall site area for two-level VSC-HVDC is 77% of that for LCC-HVDC, in spite of its higher converter building footprint, height, and volume. By adopting MMC, the site area is further reduced to only 58% of the reference value, and lower building height is achieved because of a decreased internal suspension height of converter valves. The overall site area reduction of MMC-HVDC supplies a significant benefit, especially for locations with restricted available area and/or high land price.

13.2.4.2 Disadvantages

• To meet the requirement for capacitor voltage ripple, C_sub/N should be constant, which makes the power stage dimensioning quite difficult, especially for a MMC with numerous SMs per arm. Each SM requires a gate drive, protection, capacitor voltage monitoring, and associated communication resources, which greatly increase the cost of the system.

• The control scheme becomes much more complicated than that in a two-level converter. In addition to the generic upper level control to meet the overall system behavior requirements (V_dc-Q, P-Q, etc.), the capacitor voltage-balancing control and circulating current suppression control are indispensable in a MMC for desirable operation performance, and to lower the voltage and current stress applied on semiconductor devices and passive components. Because of the demand for accurate capacitor voltage and arm current detection and/or high-speed communication, these control schemes will introduce considerable expense and computing burden to the control unit.

13.2.4.1 Generalized Multilevel Topology

Existing multilevel converters such as diode-clamped and capacitor-clamped multilevel converters can be derived from the generalized converter topology called P2 topology proposed by Peng [57] as shown in Fig. 13.15. The generalized multilevel converter topology can balance each voltage level by itself regardless of load characteristics, active or reactive power conversion, and without any assistance from other circuits at any number of levels automatically. Thus, the topology provides a complete multilevel topology that embraces the existing multilevel converters in principle.

Fig. 13.15 shows the P2 multilevel converter structure per phase leg. Each switching device, diode, or capacitor's voltage is 1V_dc, for instance, $1/\left(m-1\right)$ of the dc link voltage. Any converter with any number of levels, including the conventional bilevel converter, can be obtained using this generalized topology [1,57].

13.2.4.2 Mixed-Level Hybrid Multilevel Converter

To reduce the number of separate dc sources for high-voltage, high-power applications with multilevel converters, diode-clamped or capacitor-clamped converters can be used to replace the full-bridge cell in a cascaded converter [58]. An example is shown in Fig. 13.16. The nine-level cascade converter incorporates a three-level diode-clamped converter as the cell. The original cascaded H-bridge multilevel converter requires four separate dc sources for one phase leg and 12 for a three-phase converter. If a five-level converter replaces the full-bridge cell, the voltage level is effectively doubled for each cell. Thus, to achieve the same nine voltage levels for each phase, only two separate dc sources are needed for one phase leg and six for a three-phase converter. The configuration has mixed-level hybrid multilevel units because it embeds multilevel cells as the building block of the cascade converter. The advantage of the topology is it needs less separate dc sources. The disadvantage for the topology is its control will be complicated due to its hybrid structure.

13.2.4.3 Soft-Switched Multilevel Converter

Some soft-switching methods can be implemented for different multilevel converters to reduce the switching loss and to increase efficiency. For the cascaded converter, because each converter cell is a bilevel circuit, the implementation of soft switching is not at all different from that of conventional bilevel converters. For capacitor-clamped or diode-clamped converters, soft-switching circuits have been proposed with different circuit combinations. One of the soft-switching circuits is a zero-voltage-switching type that includes auxiliary resonant commutated pole (ARCP), coupled inductor with zero-voltage transition (ZVT), and their combinations [1,59] as shown in Fig. 13.17.

13.2.4.4 Back-to-Back Diode-Clamped Converter

Two multilevel converters can be connected in a back-to-back arrangement, and then, the combination can be connected to the electric system in a series-parallel arrangement as shown in Fig. 13.18. Both the current demanded from the utility and the voltage delivered to the load can be controlled at the same time. This series-parallel active power filter has been referred to as a universal power conditioner [60–66] when used on electric distribution systems and as a universal power flow controller [67–71] when applied at the transmission level. Earlier, Lai and Peng [29] proposed the back-to-back diode-clamped topology shown in Fig. 13.19 for use as a high-voltage dc interconnection between two asynchronous ac systems or as a rectifier or inverter for an adjustable speed drive for high-voltage motors. The diode-clamped inverter has been chosen over the other two basic multilevel circuit topologies for use in a universal power conditioner for the following reasons:

• All six phases (three on each inverter) can share a common dc link. Conversely, the cascade inverter requires that each dc level to be separate, and this is not conducive to a back-to-back arrangement.

• The multilevel flying-capacitor converter also shares a common dc link; however, each phase leg requires several additional auxiliary capacitors. These extra capacitors would add substantially to the cost and the size of the conditioner.

Because a diode-clamped converter acting as a universal power conditioner will be expected to compensate for harmonics and/or operate in low-amplitude modulation index regions, a more sophisticated higher frequency switch control than the fundamental frequency switching method will be needed. For this reason, multilevel space vector and carrier-based PWM approaches are compared in the next section and novel carrier-based PWM methodologies are given.

13.3.1.1 Subharmonic PWM

Carrara et al. [72] extended SH-PWM to multiple levels as follows: for an m-level inverter, $m-1$ carriers with the same frequency f_c and the same amplitude A_c are disposed such that the bands they occupy are contiguous. The reference waveform has peak-to-peak amplitude A_m, a frequency f_m, and its zero centered in the middle of the carrier set. The reference signal is continuously compared with each of the carrier signals. If the reference signal is greater than a carrier signal, then the active device corresponding to that carrier is switched on, and if the reference signal is lesser than a carrier signal, then the active device corresponding to that carrier is switched off.

In multilevel inverters, the amplitude modulation index, m_a, and the frequency ratio, m_f, are defined as

$m_{\mathrm{a}}=\frac{A_{\mathrm{m}}}{\left(m-1\right)\cdot A_{\mathrm{c}}}$

$m_{\mathrm{f}}=\frac{f_{\mathrm{c}}}{f_{\mathrm{m}}}$

Fig. 13.22 shows a set of carriers $\left(m_{\mathrm{f}}=21\right)$ for a six-level diode-clamped inverter and a sinusoidal reference or modulation waveform, with an amplitude modulation index of 0.8. Fig. 13.22 also shows the resulting output voltage of the inverter.

13.3.1.2 Switching Frequency Optimal PWM

Another carrier-based method that was extended to multilevel applications by Menzies et al. is termed SFO-PWM, and it is similar to SH-PWM except that a zero-sequence (triplen harmonic) voltage is added to each of the carrier waveforms [73]. This method takes the instantaneous average of the maximum and minimum of the three reference voltages $\left(V_{\mathrm{a}}^{\ast },V_{\mathrm{b}}^{\ast },V_{\mathrm{c}}^{\ast }\right)$ and subtracts this value from each of the individual reference voltages, that is,

$V_{\mathrm{offset}}=\frac{max\left(V_{\mathrm{a}}^{\ast },V_{\mathrm{b}}^{\ast },V_{\mathrm{c}}^{\ast }\right)+min\left(V_{\mathrm{a}}^{\ast },V_{\mathrm{b}}^{\ast },V_{\mathrm{c}}^{\ast }\right)}{2}$

$V_{\mathrm{aSFO}}^{\ast }=V_{\mathrm{a}}^{\ast }-V_{\mathrm{offset}}$

$V_{\mathrm{bSFO}}^{\ast }=V_{\mathrm{b}}^{\ast }-V_{\mathrm{offset}}$

$V_{\mathrm{cSFO}}^{\ast }=V_{\mathrm{c}}^{\ast }-V_{\mathrm{offset}}$

The addition of this triplen-offset voltage centers all of the three reference waveforms in the carrier band, which is equivalent to using space vector PWM [74,75]. The analog equivalent of Eqs. (13.12)–(13.15) is shown in Fig. 13.23 [76]. The SFO-PWM is shown in Fig. 13.24 for the same reference voltage waveform that was used in Fig. 13.22. The resulting output voltage of the inverter is also shown in Fig. 13.24. The SFO-PWM technique enables the modulation index to be increased by 15% before the overmodulation region is reached.

For the SH-PWM and SFO-PWM techniques shown in Figs. 13.22 and 13.24, the top and bottom switches are switched much more often than the intermediate devices. Methods to balance or reduce the device switchings without an adverse effect on a multilevel inverter's output voltage total harmonic distortion would be beneficial. The development of such methods is discussed in [77]. A novel method to balance device switchings for all of the levels in a diode-clamped inverter has been demonstrated for SH-PWM and SFO-PWM by varying the frequency for the different triangle wave carrier bands as shown in Fig. 13.25 [77].

13.3.1.3 Modulation Index Effect on Level Utilization

For low-amplitude modulation indexes, a multilevel inverter will not make use of all of its levels, and at very low modulation indexes, it operates as if it is a traditional two-level inverter. Fig. 13.26 shows two simulation results of what the output voltage waveform looks like at amplitude modulation indexes of 0.5 and 0.15. Fig. 13.26A shows how the bottom and top switches (${\mathrm{S}}_{\mathrm{a}1}-{\mathrm{S}}_{{\mathrm{a}}^{\prime }1},{\mathrm{S}}_{\mathrm{a}5}-{\mathrm{S}}_{{\mathrm{a}}^{\prime }5}$ in Fig. 13.5) are unused for amplitude modulation indexes less than 0.6 in a six-level inverter. Fig. 13.26B shows how only the middle switches (${\mathrm{S}}_{\mathrm{a}3}-{\mathrm{S}}_{{\mathrm{a}}^{\prime }3}$ in Fig. 13.5) change states when a six-level inverter is operated at an amplitude modulation index less than 0.2. The output waveform in Fig. 13.26B appears to be that of a traditional two-level inverter rather than a multilevel inverter.

The minimum modulation index m_a min, for which a multilevel inverter controlled with SH-PWM makes use of all of its levels, m, is

$m_{\mathrm{a}\min }=\frac{m-3}{m-1}$

Table 13.4 lists the minimum modulation index in which a multilevel inverter uses all its constituent levels for both SH-PWM and SFO-PWM techniques. Table 13.4 also shows that the maximum modulation index before pulse dropping (overmodulation) occurs is 1.000 for SH-PWM and 1.155 for SFO-PWM. As shown in Table 13.4, when a multilevel inverter operates at modulation indexes much less than 1.000, not all of its levels are involved in the generation of the output voltage and simply remain in an unused state until the modulation index increases sufficiently. The table also shows that level usage is more likely to suffer to a greater extent as the number of levels in the inverter increases.

One way to make use of the multiple levels, even during low modulation periods, is to take advantage of the redundant output voltage states by rotating level usage in the inverter after each modulation cycle. This will reduce the switching stresses on some of the inner levels by making use of those outer voltage levels that otherwise would go unused.

As mentioned earlier, diode-clamped inverters have redundant line-line voltage states for low modulation indexes but have no phase redundancies [78]. For an output voltage state (i,j,k) in an m-level diode-clamped inverter, the number of redundant states available is given by

$N_{{}_{\mathrm{available}}^{\mathrm{redundancies}}}=m-1-\left[max\left(i,j,k\right)-min\left(i,j,k\right)\right]$

As the modulation index decreases, more redundant states are available. Table 13.5 shows the number of distinct and redundant line-line voltage states available in a six-level inverter for different output voltages.

Table 13.5

Six-level inverter line-line voltage redundancies

$max\left(i,j,k\right)-min\left(i,j,k\right)$	Number of distinct states	Number of redundancies per distinct state	Total number of states
0	1	5	6
1	6	4	30
2	12	3	48
3	18	2	54
4	24	1	48
5	30	0	30
Total	91	—	216

In the next section, a carrier-based method is given that uses line-line redundancies in a diode-clamped inverter operating at a low modulation index so that active device usage is more balanced among the levels.

13.3.1.4 Increasing Switching Frequency at Low Modulation Indexes

For amplitude modulation indexes less than 0.5, the level usage in odd-level inverters can be sufficiently rotated so that the switching frequency can be doubled and still keep the thermal losses within the limits of the device. For inverters with an even number of levels, the modulation index at which frequency doubling can be accomplished varies with the levels as shown in Table 13.6. This increase in switching frequency enables the inverter to compensate for higher frequency harmonics and yields a waveform that more closely tracks a reference.

Table 13.6

Increased switching frequency possible at lower modulation indexes

Inverter levels	Modulation index, ma		Frequency multiplier
	Min	Max
3	0.000	0.500	2$\times$
4	0.000	0.333	3$\times$
5	0.250	0.500	2$\times$
	0.000	0.250	4$\times$
6	0.200	0.400	2$\times$
	0.000	0.200	5$\times$
7	0.333	0.500	2$\times$
	0.167	0.333	3$\times$
	0.000	0.167	6$\times$
8	0.285	0.428	2$\times$
	0.142	0.285	3$\times$
	0.000	0.142	7$\times$
9	0.25	0.500	2$\times$
	0.125	0.250	4$\times$
	0.000	0.125	8$\times$
10	0.333	0.444	2$\times$
	0.222	0.333	3$\times$
	0.111	0.222	4$\times$
	0.000	0.111	9$\times$
11	0.333	0.500	2$\times$
	0.200	0.333	3$\times$
	0.000	0.200	5$\times$
12	0.272	0.454	2$\times$
	0.181	0.272	3$\times$
	0.090	0.181	5$\times$
	0.000	0.090	11$\times$
13	0.333	0.500	2$\times$
	0.250	0.333	3$\times$
	0.167	0.250	4$\times$
	0.0833	0.167	6$\times$
	0.000	0.0833	12$\times$

As an example of how to accomplish this doubling of inverter frequency, an analysis of a seven-level diode-clamped inverter with an amplitude modulation index of 0.4 is conducted. During the first cycle, the reference waveform is centered in the upper three carrier bands, and during the next cycle, the reference waveform is centered in the lower three carrier bands as shown in Fig. 13.27. This technique enables half of the switches to “rest” every other cycle and does not incur any switching losses. With this method, the switching frequency (or carrier frequency f_c in the case of multilevel inverters) can effectively be doubled to 2f_c, but the switches will have the same thermal losses as if they were switching at f_c but every cycle.

This method is possible only for three-wire systems because the diode-clamped inverter has line-line redundancies and no phase redundancies. This means that at the discontinuity where the reference moves from one carrier band set to another, the transition has to be synchronized such that all three phases are moved from one carrier set to the next set at the same time. In the case of frequency doubling, all three phases add or subtract the following number of states (or levels) every other reference cycle:

$h_{\mathrm{a}}\left(j+1\right)=h_{\mathrm{a}}\left(j\right)+{\left(-1\right)}^j\cdot \frac{⌊m-1⌋}{2}$

At modulation indexes closer to zero, the switching frequency can be increased even more. This is possible because the reference waveform can be rotated among the carrier bands for a few cycles before returning to a previous set of switches for use. The switches are allowed to “rest” for a few cycles and thus are able to absorb higher losses during the cycle they are switched. Table 13.6 shows the possible increased switching frequencies available at lower amplitude modulation indexes for several different inverter levels.

Some additional switching loss is associated with the redundant switchings of the three phases at the end of each modulation cycle when rotating among carrier bands. For instance, for Fig. 13.28, each of the three phases in the seven-level inverter will have three switch pairs that change states at the end of every reference cycle. However, compared with the switching loss associated with just the normal PWM switchings, this redundant switching loss is quite small, typically less than 5% of the total switching loss.

Figs. 13.28 and 13.29 show two different methods of rotating the reference waveform among three different regions (top, middle, and bottom) for modulation indexes less than 0.333 in a seven-level inverter to enable the carrier frequency to be increased by a factor of three. The method shown in Fig. 13.28 is preferred over that shown in Fig. 13.29 because of less redundant state switching. The method shown in Fig. 13.28 requires only four redundant state switchings for every three reference cycles, whereas the method shown in Fig. 13.29 requires eight redundant switchings for every three reference cycles. In general, for any multilevel inverter regardless of the number of levels or number of rotation regions, using the preferred reference rotation method will have half of the redundant switching losses that the alternate method would have.

Unlike the diode-clamped inverter, the cascaded H-bridge inverter has phase redundancies in addition to the aforementioned line-line redundancies. Phase redundancies are much easier to exploit than line-line redundancies because the output voltage in each phase of a three-phase inverter can be generated independently of the other two phases when only phase redundancies are used. A method was given in [18] that makes use of these phase redundancies in a cascaded inverter so that duty cycle of each active device is balanced over $\left(m-1\right)/2$ modulation waveform cycles regardless of the modulation index. The same pulse rotation technique used for fundamental frequency switching of cascade inverters was used but with a PWM output voltage waveform [79], which is a much more effective means of controlling a driven motor at low speeds than continuing to do fundamental frequency switching. The effect of this control is that the output waveform can have a high switching frequency, but the individual levels can still switch at a constant switching frequency of 60 Hz if desired.

13.3.1.5 Multicarrier Modulation Techniques for MMC

The multicarrier techniques have also been successfully extended for MMC by using multiple carriers to control power switches of the converter topologies. It is mainly divided into two types: (1) carrier phase-shifted PWM (CPS-PWM) and (2) carrier level-shifted PWM (CLS-PWM) [80,81].

(1) CPS-PWM
For an MMC with 2N cells, the carrier waves (either sawtooth or triangular waveforms) with a phase shift of 360 degrees/N or 180 degrees/N can be employed to generate the staircase multilevel output waveform with low distortion. The modulation and output voltage waveforms for N+1 and 2N+1 levels (N=4) are given in Figs. 13.30 and 13.31, respectively.
With N+1 level modulation scheme (phase shift of 360 degrees/N among carriers), N SMs per phase are inserted at all times, leading to a balanced capacitor voltage. In contrast, if 2N+1 level modulation scheme (phase shift of 180 degrees/N among carriers) is used, N+1 or N−1 SMs will be inserted at certain time, causing issues with the capacitor voltage self-balancing algorithm and requiring additional balancing control. Using PS-PWM modulation algorithm, the effective switching frequency of the load voltage will be much higher that of each cell (Nf_c for N+1 level and 2Nf_c for 2N+1 level, f_c is the carrier frequency). This property allows low switching frequency of each SM, thus reducing switching losses. In addition, it enables a high degree of linearity, outstanding control performance, and other advantages.

(2) CLS-PWM
The carriers can also be arranged with shifts in amplitude, relating each carrier with the corresponding output voltage level generated by the multilevel inverter, which is the so-called level-shifted PWM (LS-PWM). Depending on the disposition of the carriers, three types of CLS-PWM have been developed: phase disposition (PD), phase opposition disposition (POD), and alternate phase opposition disposition (APOD), as shown in Fig. 13.32.

The PD-PWM method is realized through a comparison between a sinusoidal reference wave with vertically shifted carrier waves. N carrier signals will be created to generate an output voltage with N+1 levels. The carrier signals have the same amplitude and frequency, and all signals are in phase. In the POD-PWM method, all carrier signals above the zero axis (positive region) are in phase, and those below zero axis (negative region) are also in phase but 180 degrees phase shifted from the carrier waves in positive region. The APOD-PWM scheme requires N−1 carrier signals with phase shift of 180 degrees from each other.

The LS-PWM methods can be adopted for any multilevel converter topology. However, they are not very suitable for CHB (cascaded H-bridge converter) and MMC inverters. According to the modulation principle, the uppermost SMs will be inserted for a short time, while the middle ones insert for most of the time during a fundamental cycle, producing an uneven power dissipation and large capacitor voltage differences among the SMs.

13.3.3 Selective Harmonic Elimination

13.3.3.1 Fundamental Switching Frequency

The selective harmonic elimination method is also called fundamental switching frequency method based on the harmonic elimination theory proposed by Patel and Hoft [88,89]. A typical 11-level multilevel converter output with fundamental frequency switching scheme is shown in Fig. 13.2. The Fourier series expansion of the output voltage waveform as shown in Fig. 13.2 is expressed in Eqs. (13.1) and (13.2).

The conducting angles, θ₁,θ₂,…,θ_s, can be chosen such that the voltage total harmonic distortion is a minimum. Normally, these angles are chosen so as to cancel the predominant lower frequency harmonics [19].

For the 11-level case in Fig. 13.2, the fifth, seventh, eleventh, and thirteenth harmonics can be eliminated with the appropriate choice of the conducting angles. One degree of freedom is used so that the magnitude of the fundamental waveform corresponds to the reference waveform's amplitude or modulation index, m_a, which is defined as $V_{\mathrm{L}}^{\ast }/V_{\mathrm{Lmax}}.V_{\mathrm{L}}^{\ast }$ is the amplitude command of the inverter for a sine wave output phase voltage, and V_Lmax is the maximum attainable amplitude of the converter, that is, $V_{\mathrm{Lmax}}=s\cdot V_{\mathrm{dc}}$. The equations from Eq. (13.2) will now be as follows:

$\begin{array}{l}cos\left(5{\mathrm{\theta }}_1\right)+cos\left(5{\mathrm{\theta }}_2\right)+cos\left(5{\mathrm{\theta }}_3\right)+cos\left(5{\mathrm{\theta }}_4\right)+cos\left(5{\mathrm{\theta }}_5\right)=0\hfill \\ cos\left(7{\mathrm{\theta }}_1\right)+cos\left(7{\mathrm{\theta }}_2\right)+cos\left(7{\mathrm{\theta }}_3\right)+cos\left(7{\mathrm{\theta }}_4\right)+cos\left(7{\mathrm{\theta }}_5\right)=0\\ cos\left(11{\mathrm{\theta }}_1\right)+cos\left(11{\mathrm{\theta }}_2\right)+cos\left(11{\mathrm{\theta }}_3\right)+cos\left(11{\mathrm{\theta }}_4\right)+cos\left(11{\mathrm{\theta }}_5\right)=0\\ cos\left(13{\mathrm{\theta }}_1\right)+cos\left(13{\mathrm{\theta }}_2\right)+cos\left(13{\mathrm{\theta }}_3\right)+cos\left(13{\mathrm{\theta }}_4\right)+cos\left(13{\mathrm{\theta }}_5\right)=0\\ cos\left({\mathrm{\theta }}_1\right)+cos\left({\mathrm{\theta }}_2\right)+cos\left({\mathrm{\theta }}_3\right)+cos\left({\mathrm{\theta }}_4\right)+cos\left({\mathrm{\theta }}_5\right)=5{\mathrm{m}}_{\mathrm{a}}\end{array}$

The above equations are nonlinear transcendental equations that can be solved by an iterative method such as the Newton-Raphson method. For example, using a modulation index of 0.8 obtains the following: ${\theta }_1=6.57\mathrm{degrees},{\theta }_2=18.94\mathrm{degrees},{\theta }_3=27.18\mathrm{degrees},{\theta }_4=45.14\mathrm{degrees},{\theta }_5=62.24\mathrm{degrees}$. Thus, if the inverter output is symmetrically switched during the positive half cycle of the fundamental voltage to $+V_{\mathrm{dc}}$ at $6.57\mathrm{degrees},+2V_{\mathrm{dc}}$ at $18.94\mathrm{degrees},+3V_{\mathrm{dc}}$ at $27.18\mathrm{degrees},+4V_{\mathrm{dc}}$ at 45.14degrees and $+5V_{\mathrm{dc}}$ at 62.24degrees and similarly in the negative half cycle to $-V_{\mathrm{dc}}$ at $186.57\mathrm{degrees},-2V_{\mathrm{dc}}$ at $198.94\mathrm{degrees},-3V_{\mathrm{dc}}$ at $207.18\mathrm{degrees},-4V_{\mathrm{dc}}$ at $225.14\mathrm{degrees},-5V_{\mathrm{dc}}$ at 242.24degrees, the output voltage of the 11-level inverter will not contain the 5th, 7th, 11th, and 13th harmonic components [18]. Other methods to solve these equations include using genetic algorithms [90] and resultant theory [91,92].

Practically, the precalculated switching angles are stored as the data in memory (lookup table). Therefore, a microcontroller could be used to generate the PWM gate-drive signals. More recent methods have been developed that can generate the switching angles in real time using genetic algorithms.

13.3.3.2 Selective Harmonic Elimination PWM

In order to achieve a wide range of modulation indexes with minimized THD for the synthesized waveforms, a generalized selective harmonic modulation method [93,94] was proposed, which is called virtual stage PWM [90]. An output waveform is shown in Fig. 13.36. The virtual stage PWM is a combination of the unipolar programmed PWM and the fundamental frequency switching scheme. The output waveform of unipolar programmed PWM is shown in Fig. 13.37. When unipolar programmed PWM is employed on a multilevel converter, typically one dc voltage is involved, where the switches connected to the dc voltage are switched “on” and “off” several times per fundamental cycle. The switching pattern decides what the output voltage waveform looks like.

For fundamental switching frequency method, the number of switching angles is equal to the number of dc sources. However, for the virtual stage PWM method, the number of switching angles is not equal to the number of dc voltages. For example, in Fig. 13.36, only two dc voltages are used, whereas there are four switching angles.

Bipolar programmed PWM and unipolar programmed PWM could be used for modulation indexes too low for the applicability of the multilevel fundamental frequency switching method. Virtual stage PWM can also be used for low modulation indexes. Virtual stage PWM will produce output waveforms with a lower THD most of the time [90]. Therefore, virtual stage PWM provides another alternative to bipolar programmed PWM and unipolar programmed PWM for low modulation index control.

The major difficulty for selective harmonic elimination methods, including the fundamental switching frequency method and the virtual stage PWM method, is to solve the transcendental Eq. (13.28) for switching angles. Newton's method can be used to solve Eq. (13.28), but it needs good initial guesses, and solutions are not guaranteed. Therefore, Newton's method is not feasible to solving equations for large number of switching angles if good initial guesses are not available [95].

The resultant method has been proposed in [91,92,96] to solve the transcendental equations for switching angles. The transcendental equations characterizing the harmonic content can be converted into polynomial equations. Elimination resultant theory has been employed to determine the switching angles to eliminate specific harmonics, such as the 5th, 7th, 11th, and 13th. However, as the number of dc voltages or the number of switching angles increases, the degrees of the polynomials in these equations become bulky.

To overcome this problem, the fundamental frequency switching angle computation is solved by Newton's method. The initial guess can be provided by the results of lower order transcendental equations by the resultant method [95].