18.4.4 Solid-State Marx Generators

The use of voltage multiplication techniques for generating HV repetitive pulses is not limited to the use of transformers. More complex methods can be used without the limitation of transformers. The most common is the Marx generator concept [55].

The Marx generator concept is presented in the circuit of Fig. 18.44, which comprises a number of modular stages constituted by an energy storage capacitor C_i, two impedances Z_i (resistive and/or inductive) for charging and limiting the self-short-circuit capacitor paths and a switch S_i, for i∈{1, 2, …,n}. During the charging period, a relatively low-voltage dc power supply V_dc charges the C_i capacitors in parallel through impedances Z_i.

When switches S_i are turned on, the C_i capacitors are connected in series and apply a voltage into the load, equal to

$v_0=-n{V}_{\mathit{dc}}$

depending that the capacitors are charged to the power supply full voltage, V_dc. During this time, the bottom impedances Z_i limit the self-short-circuit path of the C_i capacitors.

The circuit in Fig. 18.44 is assembled in such a way that there is voltage modularity, meaning that each stage holds the power supply voltage V_dc. However, due to this parallel process, the first stages carry the total charging current, which sets different power requirements for the devices in each stage.

This concept has been used intensively through the years, with spark gaps used as switch S_i for very high-voltages and powers, but the spark gap only turns off when the current goes to zero. Recent technological upgrades with the addition of solid-state switches and the replacement of most of the passive elements increased the lifetime of the modulator and allowed higher pulse repetition rates, meaning an improved performance [22,56–58].

18.4.4.1 Generation of Negative Pulses

During the last years, various semiconductor-based Marx and SM topologies have been described, with analogous characteristics in order to reduce the losses and increase the performance of the circuit for different types of applications and loads [22,56–58].

Fig. 18.45 shows a typical SM topology, with n stages able to deliver negative high-voltage repetitive pulses into a load R_L; the theoretical key waveforms are shown in Fig. 18.46. Each stage of the SM consists of an energy storing capacitor C_i, a diode D_ci, and two switches S_ci and S_pi, with antiparallel diodes, where the subscript i∈{1, 2, …, n−1, n, n+1}. The S_i switches can be implemented with BJTs, GTOs, IGCTs, IGBTs, MOSFETS, or other on-off devices. The inclusion of S_c1 guarantees that during the pulse period, the dc charging power supply V_dc is not short-circuited, preventing high-current-load pulses through the power supply.

Considering resistive load, R_L, the operation of the Fig. 18.45 modulator can be understood considering two operating modes, for a switch duty ratio D=t_on/T. In the first one, switches S_ci and S_pi are, respectively, turned on and turned off. During the charging period, (T–t_on), capacitors C_i are charged from the dc charging power supply, V_dc, with current limited by the internal resistance of the semiconductors, the wires, and the dc charging power supply internal resistance (or externally added) R_dc, resulting in a small time constant that enables kHz operation. The on-state of D_ci ensures that during this period, the voltage, V₀, applied to the load is, approximately, zero.

In the second operating mode, switches S_ci and S_pi are, respectively, turned off and turned on. During the pulse mode, t_on, capacitors C_i are connected in series and their voltage applied to the load. The load voltage v₀ is proportional to the charging power supply:

$v_0=-kn{V}_{\mathit{dc}}$

  (18.97)

where n is the number of stages and k<1 characterizes the nonideal behavior of the passive and active elements in the circuit and operating conditions.

The D_ci diodes guarantee, also, that the S_pi switches only block a maximum voltage of V_dc, even in fault condition, such as the lack of synchronization. Considering Fig. 18.45, for example, if switch T_pn is off during pulse mode, D_cn conducts and short-circuits the last stage, imposing an output voltage of

$v_0=-k\left(n-1\right)V_{\mathit{dc}}$

  (18.98)

The operation of Fig. 18.45 circuit can be represented by its equivalent model during both operating modes, considering ideal switches and C_i=C. During the charging mode, the C_i capacitors are in parallel, and the circuit can be model as shown in Fig. 18.47A, where nC is the equivalent capacitance, seen by the power supply, charged with V_dc. In addition, during pulse mode, the C_i capacitors are in series, where C/n is the equivalent capacitance, seen by the load, charged with nV_dc, as shown in Fig. 18.47B.

The energy stored in the C_i capacitors, during T–t_on, is

$E_{C_i}=\frac{n}{2}C{V}_{\mathit{dc}}^2$

  (18.99)

and the energy delivered to the load, during t_on, is

$E_0=n^2\frac{V_{\mathit{dc}}^2}{R_L}{t}_{\mathit{on}}$

  (18.100)

For pulse power applications, only a small fraction of the stored energy should be transferred to the output during the pulse mode, otherwise the pulse voltage has a typical RC discharge waveform, not an almost rectangular shape. Considering a resistive load R_L, the capacitance of the C_i capacitors in Fig. 18.45 circuit can be determined according to energy delivered to the load. For the required pulse voltage droop,

$\mathrm{\Delta }{v}_0=\frac{V_{C_f}}{V_{C_i}}$

  (18.101)

where $V_{C_f}$ is the capacitor voltage at the end-of-pulse mode, t_on, and $V_{C_i}$ is the capacitors voltage immediately before pulse mode. Considering Eq. (18.101), the difference between Eqs. (18.99) and (18.100) is the energy stored in the C_i capacitors at end-of-pulse mode, $E_{C_f}$:

$E_{C_i}-E_0=E_{C_f}$

  (18.102)

where Eq. (18.102) for this case results in

$\frac{n}{2}C{V}_{\mathit{dc}}^2-n^2\frac{V_{\mathit{dc}}^2}{R_L}{t}_{\mathit{on}}=\frac{n}{2}C{\left(\mathrm{\Delta }{v}_0{V}_{\mathit{dc}}\right)}^2$

  (18.103)

Assuming that $V_{C_i}=V_{\mathit{dc}}$, equating (18.103), the capacitor value should satisfy the condition

$C\ge \frac{2n{t}_{\mathit{on}}}{R_L\left(1-\mathrm{\Delta }{v_0}^2\right)}$

  (18.104)

Considering Eqs. (18.99) through (18.104), it is mandatory to have storage energy greater than five times the pulse energy in order to have an output voltage droop better than 10%, but if a 1% voltage droop is expected, a 50 times storage energy is required, which impose limits to the design of the modulator.

The power dissipation in the switches and the capacitors charging time impose a high-voltage pulse frequency limitation. Therefore, this circuit operates better with low duty ratio, D, pulses as required in most PP applications.

In addition, the V_dc power supply must be able to charge the C_i capacitors with an energy equal to the delivered pulse energy, E₀, plus losses during the charging time, T–t_on:

$P_{V_{\mathit{dc}}}=\frac{E_0}{T-t_{\mathit{on}}}-P_{\mathit{loss}}$

  (18.105)

where the P_loss term represents the power dissipated in the circuit wiring and switches.

This determines the maximum power rating for the V_dc power supply that imposes the maximum operating frequency, pulse duty ratio, and load power to the modulator.

To build and operate the circuit of Fig. 18.45, some design consideration must be considered. First, during start-up, when the energy storing capacitors are completely discharged, the charging voltage V_dc must be slowly increased in order to limit the charging current on the switches S_ci and D_ci, which is critical in the first stages due to the parallel charging topology of the capacitors.

Actually, in the parallel charging method, the semiconductor modules current loading is not equal. For instance, in the Fig. 18.45 circuit, switch S_c1 conducts current required to capacitors C₁, C₂…, C_n–1, C_n, switch S_c2 conducts charging current for C₂, C₃…, C_n–1, C_n, and so forth. Thus, in practical implementation, modules with successive decreasing current ratings can be used, the benefits of standardization being somewhat compromised.

Also, the S_ci and S_pi switches conduct different current values, respectively, the discharge and pulse current. Hence, instead of switches needing to block unequal voltages, they are required to conduct unequal currents.

Consequently, when choosing semiconductors to implement the S switches, it is fundamental that the semiconductor current rating must be selected to guarantee that the devices work always in the saturation region inside the forward safe operating area. If not, during the first instants of the on-state (when the current is high) the semiconductors can operate in the active region where the voltage drop and losses are higher, which might destroy the devices.

The switches triggering is another important concern in these circuits. There are two drive signals, v_gs(Spi) and v_gs(Sci), respectively, to S_pi and S_ci, which should be triggered synchronously. Since all the semiconductor switches are at different high-voltage potentials, gate drive circuits with galvanic isolation are required (the use of optical fibers is mandatory to transmit the gate signals and to reduce stray capacitances to ground and neighbor cells), together with isolated power supplies to further process the transmitted gate signal and supply power to the gate drivers.

Several authors have come up with solutions to supply power to semiconductor triggering drivers for high-voltage applications. The most common include isolation transformers [59], but diode strings are also described [57].

The circuit in Fig. 18.45 enables the use of typical half-bridge semiconductor structures currently integrated in modular packages, which is advantageous to assemble the circuit and trigger the semiconductors, since it allows bootstrap operation [10].

However, the circuit topology shown in Fig. 18.45 is not suitable for dealing with capacitive loads. In fact, if a capacitive-type load is connected to the circuit output, the load stays charged after the HV pulse with a negative voltage until the charging mode of the energy storing capacitors. However, during the charging period, the load is not shorted by the D_ci, except if the energy stored in the load is very low and the charging current of capacitors C_i is sufficient to turn-on diodes D_ci.

In order to guarantee the discharge of the load capacitances after the negative HV pulse, it is necessary to change the Fig. 18.45 circuit topology for the one shown in Fig. 18.48, which also produces negative HV pulses into the load.

Considering the circuit in Fig. 18.48, as the V_dc power supply is negative, it is necessary to change the topology in comparison with Fig. 18.45 in order to maintain a similar operating behavior. The two main differences are the addition of an extra switch, S_c0, which guarantees that during the pulse period, the dc charging power supply V_dc does not participate in the pulse mode, t_on. The most important regards the fact that during the charging period, T–t_on, the S_ci switches short-circuit the load discharging any capacitance, as the one shown in Fig. 18.48.

Considering now the application of negative HV pulses into inductive loads, the circuit in Fig. 18.45 requires an additional half-bridge switching structure that connects to the load, as shown in Fig. 18.49.

As shown in Fig. 18.50, the operation of the circuit in Fig. 18.49 in comparison with circuit of Fig. 18.45, has some changes, which includes one additional time period for enabling the reset of the inductive load by the freewheeling diodes, T_ab, besides the charging, T_c, and pulse modes, t_on, in order to impose a zero average voltage to the load.

During the charging period, the on-state of D_ci and the S_p(n+1) antiparallel diode ensures that the output voltage, V₀, applied to the load is approximately zero.

After the HV negative pulse, t_on, the S_ci and S_pi switches are turned off, but in order to conserve energy, the inductive load current, i₀, must have an alternative path. This path is set by freewheeling diodes (S_ci antiparallel diodes and D_ci diodes) and the capacitor with the lowest voltage, which is charged. Normally, C_n has the lowest voltage; thus, the current path is through the S_c(n+1) antiparallel diode D_B, capacitor C_n, and diodes D_c1–D_cn. During this time, T_a, the voltage applied to the load is, about, V_dc (voltage in capacitor C_n), resetting the inductive load. Capacitor C_n is charged until its voltage is equal to the capacitor C_n–1 voltage, after which, if there is still energy in the load, the current path changes to capacitor C_n–1. As the maximum clamping voltage is V_dc, the higher the number of stages the longer the resetting time.

In this way, most of the load magnetic energy is sent back to energy storing capacitors C_i, after which the load current i₀ goes to zero, and it can be imposed again the charging mode of operation. It is important to have a safety time t_b in order to guarantee the completely reset of the load. Due to this load energy recovery method, the power supply energy needed to charge the capacitors after each pulse is lower, and the yield of this modulator can be higher.

Example 18.9

A negative solid-state Marx generator needs to be assembled for delivering −9 kV and 25 μs pulses into a 900 Ω resistive load, with less than 20% voltage droop. Considering the existing equipment, there are two alternatives: (1) V_dc=1.5 kV, n=6, and C_i=1 μF and (2) V_dc=1 kV, n=9, and C_i=1 μF. Determine which is the best alternative.

Solution

Considering the capacitance of 1 μF in each stage, then, the pulse voltage droop can be determined by Eq. (18.104). Hence, for the first alternative,

$C=\frac{2n{t}_{\mathit{on}}}{R_L\left(1-\mathrm{\Delta }{v_0}^2\right)}\iff {10}^{-6}=\frac{2\times 6\times 25\times {10}^{-6}}{900\left(1-\mathrm{\Delta }{v_0}^2\right)}\iff \mathrm{\Delta }{v}_0=0.816$

and for the second alternative,

$C=\frac{2n{t}_{\mathit{on}}}{R_L\left(1-\mathrm{\Delta }{v_0}^2\right)}\iff {10}^{-6}=\frac{2\times 9\times 25\times {10}^{-6}}{900\left(1-\mathrm{\Delta }{v_0}^2\right)}\iff \mathrm{\Delta }{v}_0=0.707$

which gives, respectively, 18.35% and 29.23% voltage droop, meaning that after the pulse the capacitors stay charged with about Eq. (18.101), respectively, 1224.7 and 707.1 V. Hence, only the first alternative keeps the pulse voltage droop below 20%. In this case, the energy stored in the capacitors is Eq. (18.99) 6.75 J, three times bigger than the energy delivered to the load during each pulse Eq. (18.100) 2.25 J.

18.4.4.2 Generation of Positive Pulses

The solid-state Marx modulators for generating positive HV pulses, with different load conditions, have equivalent properties as the ones for negative pulses, shown in the last section, besides the necessary modifications to enable the change in the output polarity. Thus, Fig. 18.51 shows the basic topology of the SM, with n stages, able to deliver positive high-voltage repetitive pulses into resistive and capacitive loads, R_LC_L.

During the pulse mode, t_on, the switches S_ci and S_pi are, respectively, turned off and turned on. Capacitors C_i are connected in series and their voltage applied to the load. The load voltage v₀ is proportional to the charging power supply:

$v_0=kn{V}_{\mathit{dc}}$

  (18.106)

where n is the number of stages and k<1 characterizes the nonideal behavior of the passive and active elements in the circuit and operating conditions. Also, in this topology, for example, if S_pn is off during pulse mode, the antiparallel S_cn diode conducts and short-circuits the last stage, imposing an output voltage of

$v_0=k\left(n-1\right)U_{\mathit{dc}}$

  (18.107)

Actually, the Fig. 18.51 circuit is equivalent to Fig. 18.45 circuit, whereas in this case with a positive V_dc power supply, it can produce positive HV pulses for both resistive and capacitive loads. The capacitive load can be driven, given that during the charging mode of capacitors C_i, the load is short-circuited by the S_ci switches, stray inductances limiting the discharge rate.

Considering now the application of positive HV pulses into inductive loads, the circuit in Fig. 18.51 requires an additional switch S_p0 and diode D₀ at the input, as shown in Fig. 18.52.

The circuit operation requires, also, an additional time period for resetting the inductive load by the added freewheeling diodes, t_ab, in addition to the charging, t_c, and pulse modes, t_on, in order to impose a zero average voltage to the load.

Considering an inductive load, after the HV positive pulse, the S_ci and S_pi switches are off, and the path for the inductive current i₀ is set by the capacitor C_n, which usually has the lowest voltage, the S_ci antiparallel diode and diode D_B. During this time, the voltage applied to the load is approximately −V_dc (the voltage in capacitor C_n), resetting the inductive load. After the load current i₀ goes to zero, the charging mode of operation can be imposed.

18.4.5 Solid-State Marx-Based High-Voltage Switches

The solid-state Marx generator concept described in the last section can be used for distributing the voltage in series-stacked semiconductors. Further, the Marx generator circuit can be used as a series switch, maintaining some intrinsic properties, which are desirable for the use with relatively low-voltage semiconductors, such as equal voltage distribution between stages and the fact the semiconductors in each stage hold off only the stage voltage capacitor.

The Marx series switch, based on the solid-state Marx of Fig. 18.51, for positive voltages, is shown in Fig. 18.53 not to apply voltage but to hold it between its terminals. Therefore, the input power supply V_dc is removed, and the S_pi switches are replaced by diodes D_pi. Also, resistors R_ci are connected in parallel with the D_ci diodes in order to balance the voltage in the capacitors C_i.

Consider the common HV pulse power topology of Fig. 18.54, where switches S₁ and S₂ commutate alternately. A HV power supply, V_dc, charges an energy storage capacitor C_dc, with current limited by resistor R_dc. The switch S₁ applies the capacitor C_dc voltage v_c to the capacitive load C_L||R_L, during the pulse period, t_on. Subsequently, switch S₂ discharges the load and other circuit parasitic capacitances to zero.

Taking into account the proposed operating scheme, each switch S_i, where i∈{1, 2}, holds a maximum voltage equal to the power supply voltage amplitude, V_dc, considering that the capacitor C_dc is charged with the voltage V_dc. When S₁ is conducting, S₂ holds off the voltage V_dc, and when S₂ is conducting, S₁ holds off the voltage V_dc. Hence, if the voltage V_dc is greater than a couple of kV, a solid-state switch comprising series-stacked semiconductors is mandatory for implementing switches S₁ and S₂.

The switching frequency of S₁ and S₂ and the pulse on time depend on the energy stored in the C_dc capacitor, on the load consumption, and on the power dissipated in the switches during commutation.

The proposed PP topology in Fig. 18.54 implemented with the series switch of Fig. 18.53 as series switch S₁ (Marx 1) and S₂ (Marx 2) is shown in Fig. 18.55.

The operation of Fig. 18.55 circuit can be understood considering the concept presented in Fig. 18.53 and the voltage waveforms presented in Fig. 18.57. For the first operating mode, during time t_on, the S_ci switches in Marx 1 are on, the C_i capacitors in Marx 1 are in parallel, and the S_ci switches in Marx 2 are off, as shown in Fig. 18.56A. The capacitor C_dc voltage, v_c, is applied into the load, v₀, and the C_i capacitors in Marx 2 are stacked in series, through the D_pi diodes, distributing the voltage across the S_ci switches, in parallel with the load.

Subsequently, in the second operating mode, during time T–t_on, the S_ci switches in Marx 1 are off and the S_ci switches in Marx 2 are on, and the load is discharged to zero, as shown in Fig. 18.56B. The v_c voltage appears between the Marx 1 terminals as shown in Fig. 18.57D, where this voltage is sustained by the C_i capacitors in series through the D_pi diodes, distributing the voltage across the S_ci switches.

Unlike in a typical Marx generator, the C_i capacitors in both Marx 1 and Marx 2 of Fig. 18.55 can suffer from voltage imbalance problems due to the fact that the C_i capacitors are charged in series: (i) in Marx 1 during period T–t_on when the load is short-circuited and the voltage v_C appears between the Marx 1 terminals, v_S1, and (ii) in Marx 2 during period t_on when the voltage is applied to the load and the voltage V_C appears between the Marx 2 terminals.

Two main causes contribute to this voltage imbalance: (i) The C_i capacitance values are not equal, and (ii) the C_i capacitors placed near the V_dc power supply are charged with a higher voltage due to the voltage droop in the semiconductors in each stage. Considering the last, the D_ci diodes do not conduct, and R_ci are used in parallel to uniformly distribute the voltage between the C_i capacitors during (i) t_on in the Marx 1 switch and (ii) T–t_on in Marx 2 switch. Alternatively, extra switches can be placed in antiparallel with diodes D_ci.

18.4.6 Solid-State Marx-Based Bipolar Generators

The Marx generator concept was extended in Ref. [60] to allow the generation of positive and/or negative pulses. This bipolar Marx generator is shown in Fig. 18.58, based in n modules with four controlled semiconductors T_fi, T_ei, T_ai, T_bi, (i∈{1,2,…,n}), two diodes D_hi, D_gi, and energy storage capacitor C_i.

During the charging period, the dc power supply V_dc charges the C_i capacitors in parallel from the power supply and C₀ capacitor by turning ON switches T_dc, D_dc, T_fi, and T_ei, through diodes D_hi and D_gi (Fig. 18.59). The on-state of T_ei and D_gi switches, during this period, may guarantee a near-zero value to the load voltage, V₀, provided the charging current is bigger than the load current.

To obtain positive pulses, only switches T_fi and T_ai are driven on (Fig. 18.60). For negative pulses, only switches T_bi and T_ei are driven on (Fig. 18.61).

18.4.7 Solid-State Marx-Based Multilevel Bipolar Generators

Some of the previous presented Marx modulators may be used to generate staircase like voltage waveforms with multiple voltage levels, which can be useful to reduce electromagnetic interference since the rate of change of the pulse voltage is reduced regarding the two level voltage pulse.

The solid-state Marx-based high-voltage switch of Fig. 18.55 can be enhanced by adding an antiparallel transistor to diodes D_pi, to obtain one of the 2(n−1) modules of the multilevel bipolar generator in Fig. 18.62A, able to output n voltage levels [61]. The extra transistor and the D_k-1,k module interconnecting diode enable a better control of the charge/discharge of the storage capacitors C_k, since they can be connected in series with the capacitors in other modules to charge/discharge, or in parallel with some other capacitors to balance their voltages Fig. 18.62B, provided diode D_k-1,k is forward-biased [61].

The C_k capacitors are charged in series (being U_Ck≈U_dc/(n−1)).

Considering a boolean switching function γ_k, the voltage U_k of each module is written as

$U_k={\gamma }_k{U}_{Ck},\mathrm{being}{\gamma }_k=\left\{\begin{array}{c}\hfill 0\mathrm{if}{S}_k,S_{k-1,k}\mathrm{are}\mathrm{ON}\wedge S_{\mathit{ka}}\mathrm{is}\mathrm{OFF}\hfill \\ \hfill 1\mathrm{if}{S}_k,S_{k-1,k}\mathrm{are}\mathrm{OFF}\wedge S_{\mathit{ka}}\mathrm{is}\mathrm{ON}\hfill \end{array}\right.$

Neglecting parasitic voltage drops, the load pulse voltage U_Load is

$U_{\mathit{Load}}=U_{CA}-{\displaystyle \sum _{k=1}^{n-1}{\gamma }_k}{U}_{Ck}=-U_{CB}+{\displaystyle \sum _{k=n}^{2\left(n-1\right)}{\gamma }_k}{U}_{Ck}$

Supposing U_CA=U_CB=U_dc/2, summing and subtracting the two previous equations, it can be obtained:

$\begin{array}{l}{U}_{\mathit{Load}}=\frac{1}{2}\left({\displaystyle \sum _{k=n}^{2\left(n-1\right)}{\gamma }_k}{U}_{Ck}-{\displaystyle \sum _{k=1}^{n-1}{\gamma }_k}{U}_{Ck}\right)\\ U_{\mathit{dc}}={\displaystyle \sum _{k=n}^{2\left(n-1\right)}{\gamma }_k}{U}_{Ck}+{\displaystyle \sum _{k=1}^{n-1}{\gamma }_k}{U}_{Ck}={\displaystyle \sum _{k=1}^{2\left(n-1\right)}{\gamma }_k}{U}_{Ck}\end{array}$

To obtain the maximum output voltage U_Loadmax=U_dc/2, it must be ${\displaystyle \sum _{k=1}^{n-1}{\gamma }_k}{U}_{Ck}=0$, which from the second equation of (18.110) means ${\displaystyle \sum _{k=n}^{2\left(n-1\right)}{\gamma }_k}{U}_{Ck}=U_{\mathit{dc}}$. Supposing balanced capacitor voltages, then, each capacitor voltage is $U_{Ck}=U_{\mathit{dc}}/\left(n-1\right)$. To generate the minimum voltage, U_Loadmin=−U_dc/2, and then, ${\displaystyle \sum _{k=n}^{2\left(n-1\right)}{\gamma }_k}{U}_{Ck}=0$, being $U_{\mathit{dc}}={\displaystyle \sum _{k=1}^{n-1}{\gamma }_k}{U}_{Ck}$. These relationships show that each generator half arm must hold off the high-voltage U_dc. From $U_{\mathit{dc}}={\displaystyle \sum _{k=1}^{n-1}{\gamma }_k}\frac{U_{\mathit{dc}}}{n-1}\Rightarrow {\displaystyle \sum _{k=1}^{n-1}{\gamma }_k=n-1}$, which must be used to define the γ_k values needed for each level n. This means that half of the total 2(n−1) modules must have γ_k=1, while the remaining half must have γ_k=0. The γ_k values can create redundant states that must be used to balance the C_k capacitor voltages [61].

Fig. 18.63 shows the simulated output voltage of a seven levels (500 V each) 12 modules bipolar generator, including the zero voltage level.

18.5 Power Electronics in Capacitor Charging Applications

18.5.1 Introduction

Conventional dc power supplies operate at a given dc output voltage into a constant or near-constant load. However, pulse loads such as lasers, flashlamps, rail guns, and radar require short but intense bursts of energy. Typically, this energy is stored in a capacitor and then released into the load. The rate at which the capacitor is charged and discharged is called the repetition rate, T, and may vary from 0.01 Hz for large capacitor banks to a few kHz for certain lasers. Recharging the capacitor voltage to a specified voltage is tasked to a capacitor charging power supply (CCPS). The role of power electronics devices, topologies, and charging strategies for capacitor charging applications is presented in this chapter.

Fig. 18.64 shows the voltage across the energy storage capacitor connected to the output of a CCPS. This figure shows that the CCPS has three modes of operation. The first mode is the charging mode in which the capacitor is charged from an initial voltage of zero to a specified final voltage. The duration of the charging mode is determined by the capacitance of the energy storage capacitor and the rate at which the CCPS delivers energy. The next mode of operation is the refresh mode, which can be considered a “standby mode,” where the stored energy is simply maintained. When the output voltage drops below a predetermined value, the CCPS should turn-on and deliver the energy necessary to compensate for capacitor leakage. Since energy is lost during the refresh mode, the duration of the refresh mode should be as brief as possible. Issues that lead to nonzero refresh times include safety margins for worst-case charging and discharging mode times and SOA requirements of switching devices. The final mode of operation is the discharge mode in which the load is actively discharging the capacitor. The CCPS does not supply any energy to the load in this mode. The amount of time the CCPS remains in this mode is determined by how quickly the load can discharge the capacitor.

The instantaneous output power for a CCPS varies over a wide range in comparison to a conventional dc power supply that supplies a near-constant power to its load. This is shown in Fig. 18.65; the output power for the PP load is drawn as linear for illustration purposes only. The charging mode is characterized by high peak power. At the beginning of this mode, the output power is zero (i.e., there is no voltage present but current is flowing). Thus, the load capacitor is equivalent to a short-circuit. In addition, at the end of the charging mode, the output power is again zero (i.e., there is an output voltage present but no current is flowing). Now, the load capacitor is equivalent to an open-circuit. The refresh mode is typically a low-power mode because the current required to compensate for capacitor leakage is small. The CCPS does not supply any power during the discharge mode when the energy storage capacitor is being discharged by the pulsed load.

The average output power for a CCPS depends on the discharge mode energy and the repetition rate of the load. It is maximum when the energy storage capacitor is discharged at the end of the charging mode (large voltage and current), which corresponds to operation without a refresh mode. Because the CCPS power is not constant, the rating of a CCPS is often given in kJ/s instead of kW. The kJ/s rating can be written as

$\mathrm{kJ}/\mathrm{s}=\frac{W_{\mathit{LOAD}}}{T}$

where W_LOAD is the energy delivered to the load per charging cycle and T is the repetition rate. In the optimum case with no refresh and instantaneous discharge, the kJ/s rating is limited to how fast a particular capacitor can be charged by its specified voltage.

18.5.2 High-Voltage dc Power Supply With Charging Resistor

In this technique, the energy storage capacitor is charged by a high-voltage dc power supply through a charging resistor as shown in Fig. 18.66. The charging mode ends when the capacitor voltage equals the output voltage of the power supply. The capacitor is continually refreshed by the power supply. During the discharge mode, the charging resistor isolates the power supply from the pulse load. The advantages of this technique are its simplicity, reliability, and low cost.

The major disadvantage of this technique is its poor efficiency. In the charging mode, the energy dissipated in the charging resistor is equal to the energy stored in the capacitor in the ideal case; therefore, the maximum efficiency is 50%. As a result, this technique is utilized only in applications where the charge rate is low, that is, 200 J/s. Another disadvantage of this technique is related to the charging time, which is determined by the RC time constant. Some laser applications require that the output voltage be within 0.1% of a target voltage. For this technique, more than five time constants are required for the capacitor voltage to meet this voltage specification.

18.5.3 Resonance-Charging

The basic resonance-charging technique is shown in Fig. 18.67. An ac input voltage is stepped up with a transformer, rectified, and filtered with capacitor C₂ to produce a high dc voltage V₀. In this circuit, C₂ is much greater than C₁. Thyristor T₁ is gated and current flows through the inductor and diode D₁ is transferring energy from C₂ to C₁. The voltage v(t) and current i(t) are described by the following equations assuming that $C_2\gg C_1$. The charge time, t_c, for this circuit can be calculated by finding the time at which the current, described by Eq. (18.112), reaches zero and is given below. The voltage v(t) has a value of 2V₀ at the end of the charging mode:

$v\left(t\right)=V_0\left(1-cos{\omega }_{0}t\right)$

$i\left(t\right)=V_0\sqrt{\frac{C_1}{L}}sin{\omega }_{0}t$

${\omega }_0=\frac{1}{\sqrt{L{C}_1}}$

$t_{\mathrm{c}}=\pi \sqrt{L{C}_1}=\frac{\pi }{{\omega }_0}$

Even though this technique is simple and efficient, it is not without its limitations. A high-voltage capacitor with a large capacitance value is needed for C₂, which increases the cost. A single thyristor is shown in Fig. 18.67. Multiple thyristors connected in series or a thyratron may be required depending on the voltage level. The repetition rate of the pulse load should be such that C₁ is fully charged and i(t) has reached zero before the load discharges to prevent latch up of T₁. It is not possible for this circuit to operate in the refresh mode because of the switch characteristics; therefore, v(t) will drift due to capacitor leakage. The charge time is a function of the circuit parameters and will drift as they change with temperature or due to aging.

Because all of the energy stored in C₁ is transmitted from C₂ in a single pulse, it can be difficult to achieve precise voltage regulation with the resonance-charging technique. However, regulation can be improved with the addition of a dequeing circuit as shown in Fig. 18.68. The voltage v(t) is monitored with a sensing network. Before v(t) reaches the desired level, thyristor T₂ is fired, which terminates the charging mode. The remaining energy stored in the inductor is dissipated in R. The addition of the dequeing circuit reduces the circuit efficiency and increases the circuit complexity and cost but still does not enable a refresh mode to compensate for capacitor leakage.

Boost charging, a variation on the resonance-charging technique, is shown in Fig. 18.69 [62]. An extra switch is added to the circuit of Fig. 18.67, allowing energy to be stored in both C₂ and L. This can be modeled as an increase in the voltage gain of the CCPS. With switches S₁ and S₂ closed, the current i(t) is given by

$i\left(t\right)=\frac{V_0}{L}t$

When $t=t_{\mathrm{on}}$, S₂ is opened, and the current is now described by

$i\left(t\right)=I_{0}cos{\omega }_{0}t+V_0\sqrt{\frac{C_1}{L}}sin{\omega }_{0}t$

where

$I_0=\frac{V_0}{L}{t}_{\mathit{on}}$

is the inductor current initial value at t_on. The voltage v(t) is then

$v\left(t\right)=I_0\sqrt{\frac{L}{C_1}}sin{\omega }_{0}t+V_0\left(1-cos{\omega }_{0}t\right)$

The time required for the current to reach zero and for the voltage v(t) to reach its peak value can be calculated from

$tan\left({\omega }_0{t}_c\right)=-\frac{I_0\sqrt{\frac{L}{C_1}}}{V_0}=-{\omega }_0{t}_{\mathit{on}}$

This is also the charge time, t_c, or the length of the charging mode. Note from Eq. (18.119) that the charge time depends on t_on, which is the on-time of switch S₂. In addition, the peak capacitor voltage is a function of t_on. The peak capacitor voltage is limited to 2V₀ without S₂; voltage gains as high as 20 are possible with the addition of S₂ [62].

The switching elements in Figs. 18.67 and 18.68 are realized with thyristors. Simple switches are shown for the boost charging technique in Fig. 18.69. Switch S₁ could be implemented with a thyristor. The boost capability provided by switch S₂ is best realized with a gate-controlled semiconductor device such as a GTO or an IGBT.

18.5.4 Switching Converters

The poor efficiency when charging a capacitor through a resistor from a high-voltage power supply limits its application to low charging rates. In the resonance-charging concepts, the energy is transferred to the load capacitor in a single pulse, and it is not possible to compensate for capacitor leakage. Energy storage capacitors may be charged utilizing the same power electronic technology that has been applied in switching converters for constant power loads. Instead of charging the energy storage capacitor with a single pulse, switching converters can charge the capacitor with a series of pulses or pulse train. The peak current is reduced when charging with a series of pulses, thus improving the efficiency of the charging process. In addition, soft-switching techniques may be used in the switching converter to increase the efficiency. The regulation of the output voltage is also improved with the pulse train because the energy is passed to the energy storage capacitor as small packets. Common control techniques such as pulse width modulation can be used to control the size of the energy packet. This capability to control the size of the energy packet permits the CCPS to operate in the refresh mode and compensate for capacitor leakage. As a result, the CCPS may operate over a broad range of load repetition rates and still maintain tight output voltage regulation during refresh mode. During the refresh mode, energy lost due to capacitor leakage may be replaced in a burst fashion [63] or in a continuous fashion similar to trickle charging a battery [64].

In the switching converter, semiconductor switches may be operated on the lower side of the transformer permitting the use of MOSFETs or IGBTs in the CCPS. Because the CCPS begins the charging mode with a short-circuit across its output, the switching converter must be capable of operating under this severe load condition. This may require the implementation of a current limiting scheme in the converter control circuit.

One switching converter as shown in Fig. 18.70 consists of a resonant converter. Note that the MOSFETs and resonant components L_r and C_r are connected on the low-voltage side of the transformer. Only the rectifier diodes and energy storage capacitor must have high-voltage ratings. When the output rectifier is conducting, the energy storage capacitor C₁ is connected in series with the resonant capacitor C_r. For a transformer turn ratio of 1/N, reflecting C₁ through the transformer yields a capacitance of N²C₁. Since N is typically large, this reflected capacitance is much larger than C_r, thus the resonant frequency, which is defined in Eq. (18.120), is not affected by C₁. For high-voltage, high-frequency operation, the leakage inductance of the transformer may be utilized as L_r. Thus, the resonant frequency can be expressed as

${\omega }_r=\frac{1}{\sqrt{L_r\left(\left(N{C}_r{C}_1\right)/\left(C_r+N{C}_1\right)\right)}}$

One characteristic of this converter, which makes it attractive for capacitor charging, is the ability to operate under the short-circuit conditions present at the beginning of the charging mode. The voltage across C₁ is zero at the beginning of this mode. The current in the switches is limited by the input voltage and impedance Z₀ as is defined in Eq. (18.121).

$Z_0=\sqrt{\frac{L_r}{C_r}}$

Another method for current limiting is to vary the ratio of f_s, the switching frequency of the MOSFETs, and the resonant frequency, f_r, which is ω_r/2π. This effectively controls the flow of energy from the source to C₁. The ratio f_s/f_r may be set to a low value at the beginning of the charging mode and increased toward unity as the voltage across C₁ increases. This limits the current when the voltage across C₁ is low and allows increased energy transfer as the voltage approaches the target voltage. The disadvantage of this approach is that variable frequency operation complicates device and component selection and degrades EMI/EMC performance of the CCPS.

The flyback converter, shown in Fig. 18.71, also may be utilized for capacitor charging applications [65,66]. When the MOSFET is turned on, current increases in the primary winding, storing energy in the magnetic field. When it reaches a specified level, the MOSFET is turned off and the energy is transferred from the magnetic field to C₁. This energy transfer is terminated when the MOSFET is turned on again.

In cases where precise output regulation is not required and the packet energy is low, the diode in Fig. 18.71 can be replaced with a Zener diode with a Zener voltage of

$V_Z=n{V}_{\mathit{in}}+V_{O,nom}$

where V_O,nom is the nominal value of V_O [67]. Once V_O,nom is reached, the next energy packet will force the diode into a brief period of breakdown with the excess energy partially recycled to the input circuit. If the packet energy is small enough, the breakdown is not destructive and V_O is limited to

$V_O=V_{O,nom}+V_{O,\Omega }$

where V_O,Ω is the small excess voltage caused by the last energy packet.

Sokal and Redl [68] have investigated different control schemes for charging capacitors using the flyback converter. Their recommendation is to charge C₁ with current pulses that are nearly flat-topped. This strategy results in higher average current for a given peak current. The capacitor is charged faster because the charge delivered to it during a pulse is directly proportional to the average current. This desired pulse shape is achieved by turning on the MOSFET to terminate the transfer of energy to C₁ soon after the MOSFET is turned off, which increases the switching frequency. When the primary current rises to a preset minimum level, the MOSFET is again turned off. This switching strategy is essentially hysteretic current mode control, in which the switch current is limited between two preset bounds.

Another converter for capacitor charging applications is the Ward converter [69–71] shown in Fig. 18.72. When the MOSFET is turned on, energy is stored in the inductor, and capacitor C_a transfers energy into the energy storage capacitor C₁ and capacitor C_b. The energy stored in the inductor is transferred to C_a when the MOSFET is turned off. The leakage inductance of the transformer and C_a resonate producing a sinusoidal current that flows in the primary winding of the transformer and the MOSFET. When the primary current reaches zero and starts negative, the diode turns on, which allows the MOSFET to be turned off efficiently at zero-current.

In some converter operating conditions, the voltage across C_a is very small because most of the energy has been transferred from C_a to C₁. The energy stored in C_a may be too small to ensure zero-current turnoff of the MOSFET. In this case, the energy stored in C_b helps to ensure that the amplitude of the current is large enough for zero-current turnoff of this device.