11.2.1 Voltage Source Inverter

The traditional topologies for single-phase VSIs are half bridge and full bridge (Fig. 11.2). The converter is composed of capacitors, switches, and diodes, where an array of two switches is called “inverter leg.” For instance, the inverter leg of the half bridge is composed of $S_{+}$ and $S_{-}$. The capacitors required to provide a neutral point N are large, such that each capacitor maintains a constant voltage.

In order to operate properly the voltage-source inverter, the following rules are compulsory:

1. Switches of the same leg cannot be on simultaneously, because a short circuit across the dc link voltage source v_i would be produced.

2. Diode in antiparallel to each switch must be placed, in order to provide a current path for inductive loads. If the commercial switch includes this diode, then the circuit is already complete.

3. In practical implementation, a dead time, also known as blanking time, must be considered in the control signals of the leg switches, to avoid breaking rule 1.

For the half-bridge VSI (Fig. 11.2A), there are two defined (states 1 and 2) and one undefined (state 3) switching state as shown in Table 11.1. In order to avoid an undefined ac output voltage condition, state 3 should be used just for the dead time. Then, the modulating technique should always ensure that at any instant either the top or the bottom switch of the inverter leg is on.

Table 11.1

Switch states for a half-bridge single-phase VSI

State	State no.	vo	Components conducting
$S_{+}$ is on, and $S_{-}$ is off	1	vi/2	$S_{+}$	If $i_o>0$
			$D_{+}$	If $i_o<0$
$S_{-}$ is on, and $S_{+}$ is off	2	$-v_i/2$	$D_{-}$	If $i_o>0$
			$S_{-}$	If $i_o<0$
$S_{+}$ and $S_{-}$ are all off	3	$-v_i/2$	$D_{-}$	If $i_o>0$
		vi/2	$D_{+}$	If $i_o<0$

Fig. 11.3 shows the ideal waveforms associated with the half-bridge inverter shown in Fig. 11.2A. The states for the switches $S_{+}$ and $S_{-}$ are defined by the modulating technique, which in this case is a carrier-based PWM.

For the full-bridge VSI (Fig. 11.2B), there are four defined (states 1–4) and one undefined (state 5) switching state as shown in Table 11.2. Again, in order to avoid an undefined ac output voltage condition, state 5 should be used just for the dead time. Then, the modulating technique should always ensure that at any instant either the top or the bottom switch of an inverter leg is on.

Table 11.2

Switch states for a full-bridge single-phase VSI

State	State no.	vaN	vbN	vo	Components conducting
$S_{1+}$ and $S_{2-}$ are on, and $S_{1-}$ and $S_{2+}$ are off	1	vi/2	$-v_i/2$	vi	$S_{1+}$ and $S_{2-}$	If $i_o>0$
					$D_{1+}$ and $D_{2-}$	If $i_o<0$
$S_{1-}$ and $S_{2+}$ are on, and $S_{1+}$ and $S_{2-}$ are off	2	$-v_i/2$	vi/2	$-v_i$	$D_{1-}$ and $D_{2+}$	If $i_o>0$
					$S_{1-}$ and $S_{2+}$	If $i_o<0$
$S_{1+}$ and $S_{2+}$ are on, and $S_{1-}$ and $S_{2-}$ are off	3	vi/2	vi/2	0	$S_{1+}$ and $D_{2+}$	If $i_o>0$
					$D_{1+}$ and $S_{2+}$	If $i_o<0$
$S_{1-}$ and $S_{2-}$ are on, and $S_{1+}$ and $S_{2+}$ are off	4	$-v_i/2$	$-v_i/2$	0	$D_{1-}$ and $S_{2-}$	If $i_o>0$
					$S_{1-}$ and $D_{2-}$	If $i_o<0$
$S_{1-}$ and $S_{1+}$ are off	5	$-v_i/2$		Depends on $S_{2-}$ and $S_{2+}$	$D_{1-}$	If $i_o>0$
		vi/2			$D_{1+}$	If $i_o<0$
$S_{2-}$ and $S_{2+}$ are off			vi/2	Depends on $S_{1-}$ and $S_{1+}$	$D_{2+}$	If $i_o>0$
			$-v_i/2$		$D_{2-}$	If $i_o<0$

Fig. 11.4 shows the ideal waveforms associated with the full-bridge inverter shown in Fig. 11.2B. The states for the switches are defined by the modulating technique, which in this case is a carrier-based PWM, but unipolar output is considered.

For the VSIs, different output filters may be employed, in order to provide the fundamental component of the output. Depending on the application, it would be desirable to provide a voltage or a current output. In Fig. 11.5, some output filters for this converter are shown; in all cases, an inductor is required immediately for the output of the converter. The first and the last one are used to provide a current output, such as in VSIs connected to the grid, where a current-like performance is required. The second-order filter is used for voltage output, such as stand-alone applications or ASDs.

11.2.2 Current Source Inverter

The topology for the single-phase CSIs is the shown in Fig. 11.6. The converter is composed of inductors, switches, and diodes. The inductors required are large, such that the inductors maintain a constant current i_i. Current-source topologies feature a low switching dv/dt and reliable overcurrent/short-circuit protection.

In order to operate properly the current-source inverter, the following rules are compulsory:

1. Top or bottom switches of the different legs cannot be off simultaneously, because no current path is provided to the input inductors.

2. Diode in series to each switch must be placed, because a short circuit across the output voltage v_o would be produced. If the commercial switch does not include antiparallel diodes, then the circuit is already complete.

3. In practical implementation, an overlapping time must be considered in the control signals of the top or bottom switches of the different legs.

According to the previous rules, it should be noticed that both switches of the inverter leg can be turned on at the same time, and this is not possible in VSI.

For the CSI (Fig. 11.6), there are four defined (states 1–4) and one not permitted switching state (state 5) as shown in Table 11.3. The modulating technique should always ensure that at any instant, at least one of the top and bottom switch of the inverter legs is on; otherwise, the inverter will be damaged.

Table 11.3

Switch states for a single-phase CSI

State	State no.	io	Components conducting
$S_{1+}$ and $S_{2-}$ are on, and $S_{1-}$ and $S_{2+}$ are off	1	ii	$S_{1+}$, $S_{2-}$, $D_{1+}$, and $D_{2-}$
$S_{1-}$ and $S_{2+}$ are on, and $S_{1+}$ and $S_{2-}$ are off	2	−ii	$S_{1-}$, $S_{2+}$, $D_{1-}$, and $D_{2+}$
$S_{1+}$ and $S_{1-}$ are on, and $S_{2+}$ and $S_{2-}$ are off	3	0	$S_{1+}$, $S_{1-}$, $D_{1+}$, and $D_{1-}$
$S_{2+}$ and $S_{2-}$ are on, and $S_{1+}$ and $S_{1-}$ are off	4	0	$S_{2+}$, $S_{2-}$, $D_{1-}$, and $D_{2-}$
$S_{1+}$ and $S_{1-}$ are off, and $S_{2+}$ and $S_{2-}$ are off	5		This state must be avoided

Fig. 11.7 shows the ideal waveforms associated with the CSI shown in Fig. 11.6. Notice that only the control signals of one inverter leg are graphed, since the other control signals are the opposite due to the rules ($S_{1+}$ = not $S_{2+}$ and $S_{1-}$ = not $S_{2-}$), but the overlapping time should be considered for implementation. The states for the switches are defined by the modulating technique, which in this case is a carrier-based PWM, but unipolar output is considered.

For the CSIs, different output filters may be employed, in order to provide the fundamental component of the output waveform. Depending on the application, it would be desirable to provide a voltage or current output. In Fig. 11.8, some output filters for this converter are shown; in all cases, a capacitor is required immediately for the output of the converter.

11.2.3 Impedance Source Inverter

There are different topologies for single-phase ISIs, namely, “Z,”- “qZ,”- and “TZ”-source inverters; in Fig. 11.9, the Z-source inverter (ZSI) is shown. The converter is composed of capacitors and inductors, switches, and diodes. The capacitors and the inductors are arranged to form an input impedance for the inverter.

In order to operate properly the impedance-source inverter of Fig. 11.9, the following rules are compulsory:

1. No restrictions to the switches of the inverter leg apply.

2. Diodes in antiparallel to each switch must be placed, in order to provide a current path for inductive loads. If the commercial switch includes these diodes, then the circuit is already complete.

3. In practical implementation, no dead or overlapping time must be considered in the control signals of the leg switches.

According to the previous rules, it should be noticed that the switches of the inverter leg can be turned on and off at any time, and then, this converter has more switching states than the others, and this is used to boost the input voltage.

For the ISI shown in Fig. 11.9, there are five defined (states 1–5) and one undefined switching state as shown in Table 11.4. The modulating technique may permit to use the additional switching state (no. 5, known as shoot-through state), and then, another modulating signal should be employed for this purpose, but usually, it has a constant waveform.

Table 11.4

Switch states for a single-phase ZSI

State	State no.	vo
$S_{1+}$ and $S_{2-}$ are on, and $S_{1-}$ and $S_{2+}$ are off	1	2vcz−vi
$S_{1-}$ and $S_{2+}$ are on, and $S_{1+}$ and $S_{2-}$ are off	2	−(2vcz−vi)
$S_{1+}$ and $S_{2+}$ are on, and $S_{1-}$ and $S_{2-}$ are off	3	0
$S_{1-}$ and $S_{2-}$ are on, and $S_{1+}$ and $S_{2+}$ are off	4	0
$S_{1+}$ and $S_{2+}$ are on, and $S_{1-}$ or $S_{2-}$ is on	5	0
$S_{1-}$ and $S_{2-}$ are on, and $S_{1+}$ or $S_{2+}$ is on
$S_{1-}$ and $S_{1+}$ are off	6	Depends on $S_{2-}$ and $S_{2+}$
$S_{2-}$ and $S_{2+}$ are off		Depends on $S_{1-}$ and $S_{1+}$

Fig. 11.10 shows the ideal waveforms associated with the ZSI shown in Fig. 11.9. The states for the switches are defined by the modulating technique, which in this case is a carrier-based PWM, but unipolar output is considered; the shoot-through state is modulated by v_r.

For the converter ZSI, the output filter may be the same as for the VSI, and then, the filters are like the ones shown in Fig. 11.5.

11.2.4 Other Inverter Schemes

In the literature, other inverter topologies, with different operation from the previous discussed converters, have been proposed. However, the compulsory rules are valid, according to the input source. The entitled boost inverter is based on two bidirectional dc/dc boost converters and is able to produce an output voltage higher than the input voltage. This idea can be easily extrapolated to other dc/dc converter topologies. For more details, the appropriate references can be consulted.

11.2.5 Pulse Width Modulation

In order to produce a sinusoidal output, the pulse width modulation is employed. The modulating techniques mostly used are the carrier-based technique (e.g., sinusoidal pulse width modulation, SPWM), the space-vector (SV) technique, and the selective harmonic elimination (SHE) technique.

11.2.5.1 The Carrier-Based Pulse Width Modulation (PWM) Technique

As mentioned earlier, it is desired that the ac output voltage, v_o, follows a given waveform (e.g., sinusoidal) on a continuous basis by properly switching the semiconductors. The carrier-based PWM technique fulfills such a requirement as it defines the on and off states of the switches of the inverter legs by comparing a modulating signal v_c (desired ac output voltage) and a triangular waveform v_Δ (carrier signal).

A special case is when the modulating signal v_c is a sinusoidal at frequency f_c and amplitude ${\hat{v}}_c$, and the triangular signal v_Δ is at frequency f_Δ and amplitude ${\hat{v}}_{\mathrm{\Delta }}$. This is the sinusoidal PWM (SPWM) scheme. In this case, the modulation index m_a (also known as the amplitude modulation ratio) is defined as

$m_a=\frac{{\hat{v}}_c}{{\hat{v}}_{\mathrm{\Delta }}}$

  (11.1)

and the normalized carrier frequency m_f (also known as the frequency modulation ratio) is

$m_f=\frac{f_{\mathrm{\Delta }}}{f_c}$

  (11.2)

There are two known output waveforms entitled bipolar and unipolar output. Figs. 11.3D (bipolar) and 11.4d (unipolar) clearly show that the ac output voltage v_o is basically a sinusoidal waveform plus harmonics.

Bipolar PWM technique

To generate a bipolar output, a carrier-based technique can be used as shown in Fig. 11.3. In this technique, only one modulating signal v_c is used and also only one triangular signal v_Δ. The important features for the bipolar output are the following:

(a) The amplitude of the fundamental component of the ac output voltage ${\hat{v}}_{o1}$ satisfies the following expression:

${\hat{v}}_{o1}={\hat{v}}_{\mathit{aN}1}=\frac{v_i}{2}{m}_a$

  (11.3)

for half-bridge VSI, Fig. 11.2A,

${\hat{v}}_{o1}={\hat{v}}_{\mathit{ab}1}=v_i{m}_a$

  (11.4)

for the full-bridge VSI, Fig. 11.2B; these equations are valid for $m_a\le 1$, which is called the linear region of the modulating technique (higher values of m_a lead to overmodulation that will be discussed later).

(b) For odd values of the normalized carrier frequency m_f, the harmonics in the ac output voltage appear at normalized frequencies f_h centered around m_f and its multiples, specifically,

$h=l{m}_f\pm kl=1,2,3,\dots$

  (11.5)

where $k=2,4,6,\dots$ for $l=1,3,5,\dots$ and $k=1,3,5,\dots$ for $l=2,4,6,\dots$.

(c) The amplitude of the ac output voltage harmonics is a function of the modulation index m_a and is independent of the normalized carrier frequency m_f for $m_f>9$.

(d) The harmonics in the dc link current (due to the modulation) appear at normalized frequencies f_p centered around the normalized carrier frequency m_f and its multiples, specifically,

$p=l{m}_f\pm k\pm 1l=1,2,\dots$

  (11.6)

where $k=2,4,6,\dots$ for $l=1,3,5,\dots$ and $k=1,3,5,\dots$ for $l=2,4,6,\dots$.

Additional important issues are the following: (a) For small values of m_f ($m_f<21$), the carrier signal v_Δ and the signal v_c should be synchronized to each other (m_f integer), which is required to hold the previous features; if this is not the case, subharmonics will be present in the ac output voltage; (b) for large values of m_f ($m_f>21$), the subharmonics are negligible if an asynchronous PWM technique is used; however, due to potential very low-order subharmonics, its use should be avoided; finally, (c) in the overmodulation region ($m_a>1$), some intersections between the carrier and the modulating signal are missed, which leads to the generation of low-order harmonics, but a higher fundamental ac output voltage is obtained; unfortunately, the linearity between m_a and ${\hat{v}}_{o1}$ achieved in the linear region does not hold in the overmodulation region; moreover, a saturation effect can be observed (Fig. 11.11).

As mentioned before, the PWM technique allows an ac output voltage to be generated that tracks a given modulating signal. In the SPWM technique, the modulating signal is a sinusoidal that provides, in the linear region, an ac output voltage that varies linearly as a function of the modulation index, and the harmonics are at well-defined frequencies and amplitudes. These features simplify the design of filtering components. Unfortunately, the maximum amplitude of the fundamental ac voltage is bounded in this operating mode. Higher voltages are obtained by using the overmodulation region ($m_a>1$); however, low-order harmonics appear in the ac output voltage. Very large values of the modulation index ($m_a>3.24$) lead to a totally square ac output voltage.

Unipolar PWM technique

To generate a unipolar output, also a carrier-based technique can be used as shown in Fig. 11.4, where two sinusoidal modulating signals (v_c and $-v_c)$ are used. The signal v_c is used to generate S₁₊, and $-v_c$ is used to generate S₂₊. Notice that this output cannot be produced by a half-bridge inverter. Important features for the unipolar output are the following:

(a) The amplitude of the fundamental component of the ac output voltage ${\hat{v}}_{o1}$ satisfies the following expression:

${\hat{v}}_{o1}=2\cdot {\hat{v}}_{\mathit{aN}1}=m_a\cdot v_i$

  (11.7)

(b) Since the phase voltages (v_aN and v_bN) are identical but 180° out of phase, the output voltage ($v_o=v_{\mathit{ab}}=v_{\mathit{aN}}-v_{bN}$) will not contain even harmonics. Thus, if m_f is taken even, the harmonics in the ac output voltage appear at normalized odd frequencies f_h centered around twice the normalized carrier frequency m_f and its multiples. Specifically,

$h=l{m}_f\pm kl=2,4,\dots$

  (11.8)

where $k=1,3,5,\dots$; this feature is considered to be an advantage because it allows the use of smaller filtering components to obtain high-quality voltage and current waveforms while using the same switching frequency as in VSIs modulated by the bipolar approach.

(c) The amplitude of the ac output voltage harmonics is also a function of the modulation index m_a.

(d) The harmonics in the dc link current appear at normalized frequencies f_p centered around twice the normalized carrier frequency m_f and its multiples. Specifically,

$p=l{m}_f\pm k\pm 1l=2,4,\dots$

  (11.9)

where $k=1,3,5,\dots$

11.2.5.2 Selective Harmonic Elimination

The main objective is to obtain a sinusoidal ac output voltage waveform where the fundamental component can be adjusted arbitrarily within a range and the intrinsic harmonics selectively eliminated. This is achieved by mathematically generating the exact instant of the turn-on and turnoff of the power semiconductors. The ac output voltage features odd half- and quarter-wave symmetry; therefore, even harmonics are not present ($v_{oh}=0$, $h=2,4,6,\dots$). Moreover, the phase voltage waveform (v_o) should be chopped N times per half cycle in order to adjust the fundamental and eliminate $N-1$ harmonics in the ac output voltage waveform.

For this modulation, also the output may be bipolar or unipolar.

Bipolar SHE technique

The general expressions to eliminate an even $N-1$ ($N-1=2,4,6,\dots$) number of harmonics are

$\begin{array}{ll}-{\displaystyle \sum _{k=1}^N}{\left(-1\right)}^{k}cos\left({\alpha }_k\right)\hfill & =\frac{\left(2+\pi {\hat{v}}_{o1}\right)/v_i}{4}\hfill \\ -{\displaystyle \sum _{k=1}^N}{\left(-1\right)}^{k}cos\left(n{\alpha }_k\right)\hfill & =\frac{1}{2}\mathrm{f}\mathrm{o}\mathrm{r}n=3,5,\dots ,2N-1\hfill \end{array}$

  (11.10)

where α₁, α₂,…, α_N should satisfy ${\alpha }_1<{\alpha }_2<\cdots <{\alpha }_N<\pi /2$.

For instance, to eliminate the third and fifth harmonics and to perform fundamental magnitude control ($N=3$), the equations to be solved are the following:

$\begin{array}{ll}cos\left(1{\alpha }_1\right)-cos\left(1{\alpha }_2\right)+cos\left(1{\alpha }_3\right)\hfill & =\left(2+\pi {\hat{v}}_{o1}/v_i\right)/4\hfill \\ cos\left(3{\alpha }_1\right)-cos\left(3{\alpha }_2\right)+cos\left(3{\alpha }_3\right)\hfill & =1/2\hfill \\ cos\left(5{\alpha }_1\right)-cos\left(5{\alpha }_2\right)+cos\left(5{\alpha }_3\right)\hfill & =1/2\hfill \end{array}$

  (11.11)

where the angles α₁, α₂, and α₃ are defined as shown in Fig. 11.12A and the spectrum in Fig. 11.12B. The angles are found by means of iterative algorithms as no analytic solutions can be derived. The angles α₁, α₂, and α₃ are plotted for different values of ${\hat{v}}_{o1}/v_i$ in Fig. 11.13A.

Similarly, the general expressions to eliminate an odd $N-1$ ($N-1=3,5,7,\dots$) number of harmonics are given by

$\begin{array}{ll}-{\displaystyle \sum _{k=1}^N}{\left(-1\right)}^{k}cos\left(n{\alpha }_k\right)\hfill & =\frac{\left(2-\pi {\hat{v}}_{o1}\right)/v_i}{4}\hfill \\ -{\displaystyle \sum _{k=1}^N}{\left(-1\right)}^{k}cos\left(n{\alpha }_k\right)\hfill & =\frac{1}{2}\mathrm{f}\mathrm{o}\mathrm{r}n=3,5,\dots ,2N-1\hfill \end{array}$

  (11.12)

where α₁,α₂,…,α_N should satisfy ${\alpha }_1<{\alpha }_2<\cdots <{\alpha }_N<\pi /2$.

For instance, to eliminate the third, fifth, and seventh harmonics and to perform the fundamental magnitude control ($N-1=3$), the equations to be solved are

$\begin{array}{ll}cos\left(1{\alpha }_1\right)-cos\left(1{\alpha }_2\right)+cos\left(1{\alpha }_3\right)-cos\left(1{\alpha }_4\right)\hfill & =\left(2-\pi {\hat{v}}_{o1}/v_i\right)/4\hfill \\ cos\left(3{\alpha }_1\right)-cos\left(3{\alpha }_2\right)+cos\left(3{\alpha }_3\right)-cos\left(3{\alpha }_4\right)\hfill & =1/2\hfill \\ cos\left(5{\alpha }_1\right)-cos\left(5{\alpha }_2\right)+cos\left(5{\alpha }_3\right)-cos\left(5{\alpha }_4\right)\hfill & =1/2\hfill \\ cos\left(7{\alpha }_1\right)-cos\left(7{\alpha }_2\right)+cos\left(7{\alpha }_3\right)-cos\left(7{\alpha }_4\right)\hfill & =1/2\hfill \end{array}$

  (11.13)

where the angles α₁, α₂, α₃, and α₄ are defined as shown in Fig. 11.12C, and the spectrum in Fig. 11.12D. The angles α₁, α₂, and α₃ are plotted for different values of ${\hat{v}}_{o1}/v_i$ in Fig. 11.13B.

Unipolar SHE technique

The general expressions to eliminate an arbitrary $N-1$ ($N-1=3,5,7,\dots$) number of harmonics are given by

$\begin{array}{ll}-{\displaystyle \sum _{k=1}^N}{\left(-1\right)}^{k}cos\left(n{\alpha }_k\right)\hfill & =\frac{\pi }{4}\left(\frac{{\hat{v}}_{o1}}{v_i}\right)\hfill \\ -{\displaystyle \sum _{k=1}^N}{\left(-1\right)}^{k}cos\left(n{\alpha }_k\right)\hfill & =0\mathrm{f}\mathrm{o}\mathrm{r}n=3,5,\dots ,2N-1\hfill \end{array}$

  (11.14)

where α₁,α₂,…,α_N should satisfy ${\alpha }_1<{\alpha }_2<\cdots <{\alpha }_N<\pi /2$.

For instance, to eliminate the third, the fifth, and the seventh harmonics and to perform fundamental component magnitude control ($N=4$), the equations to be solved are

$\begin{array}{ll}cos\left(1{\alpha }_1\right)-cos\left(1{\alpha }_2\right)+cos\left(1{\alpha }_3\right)-cos\left(1{\alpha }_4\right)\hfill & =\pi {\hat{v}}_{o1}/\left(v_{i}4\right)\hfill \\ cos\left(3{\alpha }_1\right)-cos\left(3{\alpha }_2\right)+cos\left(3{\alpha }_3\right)-cos\left(3{\alpha }_4\right)\hfill & =0\hfill \\ cos\left(5{\alpha }_1\right)-cos\left(5{\alpha }_2\right)+cos\left(5{\alpha }_3\right)-cos\left(5{\alpha }_4\right)\hfill & =0\hfill \\ cos\left(7{\alpha }_1\right)-cos\left(7{\alpha }_2\right)+cos\left(7{\alpha }_3\right)-cos\left(7{\alpha }_4\right)\hfill & =0\hfill \end{array}$

  (11.15)

where the angles α₁, α₂, α₃, and α₄ are defined as shown in Fig. 11.14A and the spectrum in Fig. 11.14B. The angles α₁, α₂, α₃, and α₄ are plotted for different values of ${\hat{v}}_{o1}/v_i$ in Fig. 11.15A.

Fig. 11.14C shows a special case where only the fundamental ac output voltage is controlled. This is known as output control by voltage cancellation, which derives from the fact that its implementation is easily attainable by using two phase-shifted square-wave switching signals as shown in Fig. 11.16. The phase-shift angle becomes two $\cdot {\alpha }_1$ (Fig. 11.16B). Thus, the amplitude of the fundamental component and harmonics in the ac output voltage are given by

${\hat{v}}_{oh}=\frac{4}{\pi }{v}_i\frac{{\left(-1\right)}^{\left(h-1\right)/2}}{h}cos\left(h{\alpha }_1\right)h=1,3,5,\dots$

  (11.16)

It can also be observed in Fig. 11.16C that for ${\alpha }_1=0$ square-wave operation is achieved. In this case, the fundamental ac output voltage is given by

${\hat{v}}_{o1}=\frac{4}{\pi }{v}_i$

  (11.17)

where the fundamental load voltage can be controlled by the manipulation of the dc link voltage v_i. Additional means to modify this voltage should be provided. Depending on the dc link source of power, this could be a controlled rectifier, for ac sources, or a dc/dc converter, for dc sources.

To implement the SHE modulating technique, the modulator should generate the gating pattern according to the angles as shown in Figs. 11.13 and 11.15. This task is usually performed by digital systems that normally store the angles in look-up tables.

11.3.1 Sinusoidal PWM

This is an extension of the one introduced for single-phase VSIs. In this case and in order to produce 120° out-of-phase load voltages, three modulating signals that are 120° out of phase are used. Fig. 11.18 shows the ideal waveforms of three-phase VSI SPWM. In order to use a single-carrier signal and preserve the features of the PWM technique, the normalized carrier frequency m_f should be an odd multiple of 3. Thus, all phase voltages (v_aN, v_bN, and $v_{cN})$ are identical, but 120° out of phase without even harmonics; moreover, harmonics at frequencies, a multiple of 3, are identical in amplitude and phase in all phases. For instance, if the ninth harmonic in phase aN is

$v_{\mathit{aN}9}\left(t\right)={\hat{v}}_{9}sin\left(9\omega t\right)$

the ninth harmonic in phase bN will be

$\begin{array}{c}{v}_{bN9}\left(t\right)={\hat{v}}_{9}sin\left[9\left(\omega t-120°\right)\right]\\ ={\hat{v}}_{9}sin\left(9\omega t-1080°\right)={\hat{v}}_{9}sin\left(9\omega t\right)\end{array}$

Thus, the ac output line voltage $v_{\mathit{ab}}=v_{\mathit{aN}}-v_{bN}$ will not contain the ninth harmonic. Therefore, for odd multiple of 3 values of the normalized carrier frequency m_f, the harmonics in the ac output voltage appear at normalized frequencies f_h centered around m_f and its multiples, specifically, at

$h=l{m}_f\pm kl=1,2,\dots$

where $l=1,3,5,\dots$ for $k=2,4,6,\dots$ and $l=2,4,\dots$ for $k=1,5,7,\dots$ such that h is not a multiple of 3. Therefore, the harmonics will be at $m_f\pm 2$, $m_f\pm 4,\dots$, $2m_f\pm 1$, $2m_f\pm 5,\dots ,3m_f\pm 2$, $3m_f\pm 4,\dots ,4m_f\pm 1$, $4m_f\pm 5,\dots$. For nearly sinusoidal ac load current, the harmonics in the dc link current are at frequencies given by

$h=l{m}_f\pm k\pm 1l=1,2,\dots$

where $l=0,2,4,\dots$ for $k=1,5,7,\dots$ and $l=1,3,5,\dots$ for $k=2,4,6,\dots$ such that $h=l\cdot m_f\pm k$ is positive and not a multiple of 3.

The identical conclusions can be drawn for the operation at small and large values of m_f as for the single-phase configurations. However, because the maximum amplitude of the fundamental phase voltage in the linear region ($m_a\le 1$) is v_i/2, the maximum amplitude of the fundamental ac output line voltage is $\sqrt{3}{v}_i/2$. Therefore, one can write

${\hat{v}}_{\mathit{ab}1}=m_a\sqrt{3}\frac{v_i}{2}0<m_a\le 1$

To further increase the amplitude of the load voltage, the amplitude of the modulating signal ${\hat{v}}_c$ can be made higher than the amplitude of the carrier signal ${\hat{v}}_{\mathrm{\Delta }}$, which leads to overmodulation. The relationship between the amplitude of the fundamental ac output line voltage and the dc link voltage becomes nonlinear as in single-phase VSIs. Thus, in the overmodulation region, the line voltages range is

$\sqrt{3}\frac{v_i}{2}<{\hat{v}}_{\mathit{ab}1}={\hat{v}}_{bc1}={\hat{v}}_{ca1}<\frac{4}{\pi }\sqrt{3}\frac{v_i}{2}$

11.3.2 Square-Wave Operation of Three-phase VSIs

Large values of m_a in the SPWM technique lead to full overmodulation. This is known as square-wave operation as illustrated in Fig. 11.19, where the power semiconductors are on for 180°. In this operation mode, the VSI cannot control the load voltage except by means of the dc link voltage v_i. This is based on the fundamental ac line-voltage expression

${\hat{v}}_{\mathit{ab}1}=\frac{4}{\pi }\sqrt{3}\frac{v_i}{2}$

The ac line output voltage contains the harmonics f_h, where $h=6\cdot k\pm 1$ ($k=1,2,3,\dots$), and they feature amplitudes that are inversely proportional to their harmonic order (Fig. 11.18D). Their amplitudes are

${\hat{v}}_{\mathit{ab}h}=\frac{1}{h}\frac{4}{\pi }\sqrt{3}\frac{v_i}{2}$

11.3.3 Sinusoidal PWM with Zero Sequence Signal Injection

The restriction for m_a ($m_a\le 1$) can be relaxed if a zero-sequence signal is added to the modulating signals before they are compared with the carrier signal. Fig. 11.20 shows the block diagram of the technique. Clearly, the addition of the zero sequence reduces the peak amplitude of the resulting modulating signals (u_ca, u_cb, $u_{\mathit{cc}})$, while the fundamental components remain unchanged. This approach expands the range of the linear region as it allows the use of modulation indexes m_a up to $2/\sqrt{3}$ without getting into the overmodulating region.

The maximum amplitude of the fundamental phase voltage in the linear region $\left(m_a\le 2/\sqrt{3}\right)$ is v_i/2; thus, the maximum amplitude of the fundamental ac output line voltage is v_i. Therefore, one can write

${\hat{v}}_{\mathit{ab}1}=m_a\sqrt{3}\frac{v_i}{2}\left(0<m_a\le 2/\sqrt{3}\right)$

Fig. 11.21 shows the ideal waveforms of a three-phase VSI SPWM with zero injection for $m_a=0.8$.

11.3.4 Selective Harmonic Elimination in Three-phase VSIs

As in single-phase VSIs, the SHE technique can be applied to three-phase VSIs. In this case, the power semiconductors of each leg of the inverter are switched so as to eliminate a given number of harmonics and to control the fundamental phase voltage amplitude. Considering that in many applications the required line output voltages should be balanced and 120° out of phase, the harmonic multiples of 3 ($h=3,9,15,\dots$), which could be present in the phase voltages (v_aN, v_bN, and v_cN), will not be present in the load voltages (v_ab, v_bc, and v_ca). Therefore, these harmonics are not required to be eliminated; thus, the chopping angles are used to eliminate only the harmonics at frequencies $h=5,7,11,13,\dots$ as required.

The expressions to eliminate a given number of harmonics are the same as those used in single-phase inverters. For instance, to eliminate the fifth and seventh harmonics and perform fundamental magnitude control ($N=3$), the equations to be solved are

$\begin{array}{l}cos\left(1{\alpha }_1\right)-cos\left(1{\alpha }_2\right)+cos\left(1{\alpha }_3\right)=\left(2+\pi {\hat{v}}_{\mathit{aN}1}/v_i\right)/4\\ cos\left(5{\alpha }_1\right)-cos\left(5{\alpha }_2\right)+cos\left(5{\alpha }_3\right)=1/2\\ cos\left(7{\alpha }_1\right)-cos\left(7{\alpha }_2\right)+cos\left(7{\alpha }_3\right)=1/2\end{array}$

where the angles α₁, α₂, and α₃ are defined as shown in Fig. 11.22A and plotted in Fig. 11.23. Fig. 11.22B shows that the third, ninth, fifteenth, … harmonics are all present in the phase voltages; however, they are not in the line voltages (Fig. 11.22D). If necessary, higher-order harmonics not eliminated with this technique can be filtered using small filters.

11.3.5 Space-Vector (SV)-Based Modulating Techniques

At present, the control strategies are implemented in digital systems, and therefore, digital modulating techniques are also available. The SV-based modulating technique is a digital technique in which the objective is to generate PWM load line voltages that are on average equal to given load line voltages. This is done in each sampling period by properly selecting the switch states from the valid ones of the VSI (Table 11.5) and by proper calculation of the period of times they are used. The selection and calculation times are based upon the SV transformation.

11.3.5.1 Space-Vector Transformation

Any three-phase set of variables that add up to zero in the stationary abc frame can be represented in a complex plane by a complex vector that contains a real (α) and an imaginary (β) component. For instance, the vector of three-phase line-modulating signals ${\mathbf{v}}_{\mathbf{c}}^{abc}={\left[v_{ca}{v}_{cb}{v}_{\mathit{cc}}\right]}^T$ can be represented by the complex vector ${\overrightarrow{\mathbf{v}}}_{\mathbf{c}}={\mathbf{v}}_{\mathbf{c}}^{\mathrm{\alpha }\mathrm{\beta }}={\left[v_{c\alpha }{v}_{c\beta }\right]}^T$ by means of the following transformation:

$v_{c\alpha }=\frac{2}{3}\left[v_{ca}-0.5\left(v_{cb}+v_{\mathit{cc}}\right)\right]$

  (11.31)

$v_{c\beta }=\frac{\sqrt{3}}{3}\left(v_{cb}-v_{\mathit{cc}}\right)$

  (11.32)

If the line-modulating signals v_c^abc are three balanced sinusoidal waveforms that feature an amplitude ${\hat{v}}_c$ and an angular frequency ω, the resulting modulating signals in the αβ stationary frame become a vector ${\overrightarrow{\mathbf{v}}}_{\mathbf{c}}={\mathbf{v}}_{\mathbf{c}}^{\mathrm{\alpha }\mathrm{\beta }}$ of fixed module ${\hat{v}}_c$, which rotates at frequency ω (Fig. 11.24). Similarly, the SV transformation is applied to the line voltages of the eight states of the VSI normalized with respect to v_i (Table 11.5), which generates the eight space vectors (${\overrightarrow{\mathbf{v}}}_i$, $i=1,2,\dots ,8$) in Fig. 11.24. As expected, ${\overrightarrow{\mathbf{v}}}_1$ to ${\overrightarrow{\mathbf{v}}}_6$ are nonnull line-voltage vectors, and ${\overrightarrow{\mathbf{v}}}_7$ and ${\overrightarrow{\mathbf{v}}}_8$ are null line-voltage vectors.

The objective of the SV technique is to approximate the line-modulating signal space vector ${\overrightarrow{\mathbf{v}}}_{\mathbf{c}}$ with the eight space vectors (${\overrightarrow{\mathbf{v}}}_i$, $i=1,2,\dots ,8$) available in VSIs. However, if the modulating signal ${\overrightarrow{\mathbf{v}}}_{\mathbf{c}}$ is laying between the arbitrary vectors ${\overrightarrow{\mathbf{v}}}_i$ and ${\overrightarrow{\mathbf{v}}}_{i+1}$, only the nearest two nonzero vectors (${\overrightarrow{\mathbf{v}}}_i$ and ${\overrightarrow{\mathbf{v}}}_{i+1}$) and the zero SV (${\overrightarrow{\mathbf{v}}}_z={\overrightarrow{\mathbf{v}}}_7$ or ${\overrightarrow{\mathbf{v}}}_8$) should be used. Thus, the maximum load line voltage is maximized, and the switching frequency is minimized. To ensure that the generated voltage in one sampling period T_s (made up of the voltages provided by the vectors ${\overrightarrow{\mathbf{v}}}_i$, ${\overrightarrow{\mathbf{v}}}_{i+1}$, and ${\overrightarrow{\mathbf{v}}}_z$ used during times T_i, $T_{i+1}$, and T_z) is on average equal to the vector ${\overrightarrow{\mathbf{v}}}_{\mathbf{c}}$, the following expression should hold:

${\overrightarrow{\mathbf{v}}}_{\mathbf{c}}\cdot T_s={\overrightarrow{\mathbf{v}}}_i\cdot T_s+{\overrightarrow{\mathbf{v}}}_{i+1}\cdot T_{i+1}+{\overrightarrow{\mathbf{v}}}_z\cdot T_z$

  (11.33)

The solution of the real and imaginary parts of Eq. (11.32) for a line-load voltage that features an amplitude restricted to $0\le {\hat{v}}_c\le 1$ gives

$T_i=T_s\cdot {\hat{v}}_c\cdot sin\left(\pi /3-\theta \right)$

  (11.34)

$T_{i+1}=T_s\cdot {\hat{v}}_c\cdot sin\left(\theta \right)$

  (11.35)

$T_z=T_s-T_i-T_{i+1}$

  (11.36)

The preceding expressions indicate that the maximum fundamental line-voltage amplitude is unity as $0\le \theta \le \pi /3$. This is an advantage over the SPWM technique that achieves a $\surd 3/2$ maximum fundamental line-voltage amplitude in the linear operating region. Although the space-vector-modulation (SVM) technique selects the vectors to be used and their respective on-times, the sequence in which they are used, the selection of the zero space vector, and the normalized sampled frequency remain undetermined.

For instance, if the modulating line-voltage vector is in sector 1 (Fig. 11.24), the vectors ${\overrightarrow{\mathbf{v}}}_1$, ${\overrightarrow{\mathbf{v}}}_2$, and ${\overrightarrow{\mathbf{v}}}_z$ should be used within a sampling period by intervals given by T₁, T₂, and T_z, respectively. However, the sequence should be different, for example, (i) ${\overrightarrow{\mathbf{v}}}_1-{\overrightarrow{\mathbf{v}}}_2-{\overrightarrow{\mathbf{v}}}_z$, (ii) ${\overrightarrow{\mathbf{v}}}_z-{\overrightarrow{\mathbf{v}}}_1-{\overrightarrow{\mathbf{v}}}_2-{\overrightarrow{\mathbf{v}}}_z$, and (iii) ${\overrightarrow{\mathbf{v}}}_z-{\overrightarrow{\mathbf{v}}}_1-{\overrightarrow{\mathbf{v}}}_2-{\overrightarrow{\mathbf{v}}}_1-{\overrightarrow{\mathbf{v}}}_z$. Finally, the technique does not indicate whether ${\overrightarrow{\mathbf{v}}}_z$ should be ${\overrightarrow{\mathbf{v}}}_7$, ${\overrightarrow{\mathbf{v}}}_8$, or a combination of both.

11.3.5.3 The Normalized Sampling Frequency

The normalized carrier frequency m_f in three-phase carrier-based PWM techniques is chosen to be an odd integer number multiple of 3 ($m_f=3\cdot n$, $n=1,3,5,\dots$). Thus, it is possible to minimize parasitic or nonintrinsic harmonics in the PWM waveforms. A similar approach can be used in the SVM technique to minimize uncharacteristic harmonics. Hence, it is found that the normalized sampling frequency f_sn should be an integer multiple of 6. This is due to the fact that in order to produce symmetrical line voltages, all the sectors (a total of six) should be used equally in one period. As an example, Fig. 11.25 shows the relevant waveforms of a VSI SVM for $f_{sn}=18$ and ${\hat{v}}_c=0.8$. Fig. 11.25 confirms that the first set of relevant harmonics in the load line voltage are at f_sn, which is also the switching frequency.

11.3.6 DC Link Current in Three-Phase VSIs

Due to the fact that the inverter is assumed to be lossless and constructed without storage energy components, the instantaneous power balance indicates that

$v_i\left(t\right)\cdot i_i\left(t\right)=v_{\mathit{ab}}\left(t\right)\cdot i_a\left(t\right)+v_{bc}\left(t\right)\cdot i_b\left(t\right)+v_{ca}\left(t\right)\cdot i_c\left(t\right)$

where i_a(t), i_b(t), and i_c(t) are the phase-load currents as shown in Fig. 11.26. If the load is balanced and inductive and a relatively high switching frequency is used, the load currents become nearly sinusoidal balanced waveforms. On the other hand, if the ac output voltages are considered sinusoidal and the dc link voltage is assumed constant $v_i\left(t\right)=V_i$, Eq. (11.37) can be simplified to

$i_i\left(t\right)=\frac{1}{V_i}\left\{\begin{array}{l}\sqrt{2}{V}_{o1}sin\left(\omega t\right)\cdot \sqrt{2}{I}_{o}sin\left(\omega t-\varphi \right)\hfill \\ +\sqrt{2}{V}_{o1}sin\left(\omega t-{120}^{\circ }\right)\cdot \sqrt{2}{I}_{o}sin\left(\omega t-120°-\varphi \right)\hfill \\ +\sqrt{2}{V}_{o1}sin\left(\omega t-{240}^{\circ }\right)\cdot \sqrt{2}{I}_{o}sin\left(\omega t-240°-\varphi \right)\hfill \end{array}\right\}$

where V_o1 is the fundamental rms ac output line voltage, I_o is the rms phase-load current, and ϕ is an arbitrary inductive load power factor. Hence, the dc link current expression can be further simplified to

$i_i\left(t\right)=3\frac{V_{o1}}{V_i}{I}_{o}cos\left(\varphi \right)=\sqrt{3}\frac{V_{o1}}{V_i}{I}_{l}cos\left(\varphi \right)$

where $I_l=\sqrt{3}{I}_o$ is the rms load line current. The resulting dc link current expression indicates that under harmonic-free load voltages, only a clean dc current should be expected in the dc bus and, compared with single-phase VSIs, there is no presence of second harmonic. However, as the ac load line voltages contain harmonics around the normalized sampling frequency f_sn, the dc link current will contain harmonics but around f_sn as shown in Fig. 11.25H.

11.3.7 Phase-Load Voltage in Three-Phase VSIs

The load is sometimes wye-connected, and the phase-load voltages v_an, v_bn, and v_cn may be required (Fig. 11.27). To obtain them, it should be considered that the line-voltage vector is

$\left[\begin{array}{c}\hfill v_{\mathit{ab}}\hfill \\ \hfill v_{bc}\hfill \\ \hfill v_{ca}\hfill \end{array}\right]=\left[\begin{array}{c}\hfill v_{\mathit{an}}-v_{bn}\hfill \\ \hfill v_{bn}-v_{cn}\hfill \\ \hfill v_{cn}-v_{\mathit{an}}\hfill \end{array}\right]$

which can be written as a function of the phase voltage vector [v_anv_bnv_cn]^T as

$\left[\begin{array}{c}\hfill v_{\mathit{ab}}\hfill \\ \hfill v_{bc}\hfill \\ \hfill v_{ca}\hfill \end{array}\right]=\left[\begin{array}{ccc}\hfill 1\hfill & \hfill -1\hfill & \hfill 0\hfill \\ \hfill 0\hfill & \hfill 1\hfill & \hfill -1\hfill \\ \hfill -1\hfill & \hfill 0\hfill & \hfill 1\hfill \end{array}\right]\left[\begin{array}{c}\hfill v_{\mathit{an}}\hfill \\ \hfill v_{bn}\hfill \\ \hfill v_{cn}\hfill \end{array}\right]$

Expression (11.41) represents a linear system where the unknown quantity is the vector [v_anv_bnv_cn]^T. Unfortunately, the system is singular as the rows add up to zero (line voltages add up to zero); therefore, the phase-load voltages cannot be obtained by matrix inversion. However, if the phase-load voltages add up to zero, Eq. (11.41) can be rewritten as

$\left[\begin{array}{c}\hfill v_{\mathit{ab}}\hfill \\ \hfill v_{bc}\hfill \\ \hfill 0\hfill \end{array}\right]=\left[\begin{array}{ccc}\hfill 1\hfill & \hfill -1\hfill & \hfill 0\hfill \\ \hfill 0\hfill & \hfill 1\hfill & \hfill -1\hfill \\ \hfill 1\hfill & \hfill 1\hfill & \hfill 1\hfill \end{array}\right]\left[\begin{array}{c}\hfill v_{\mathit{an}}\hfill \\ \hfill v_{bn}\hfill \\ \hfill v_{cn}\hfill \end{array}\right]$

which is not singular, and hence,

$\left[\begin{array}{c}\hfill v_{\mathit{an}}\hfill \\ \hfill v_{bn}\hfill \\ \hfill v_{cn}\hfill \end{array}\right]={\left[\begin{array}{ccc}\hfill 1\hfill & \hfill -1\hfill & \hfill 0\hfill \\ \hfill 0\hfill & \hfill 1\hfill & \hfill -1\hfill \\ \hfill 1\hfill & \hfill 1\hfill & \hfill 1\hfill \end{array}\right]}^{-1}\left[\begin{array}{c}\hfill v_{\mathit{ab}}\hfill \\ \hfill v_{bc}\hfill \\ \hfill 0\hfill \end{array}\right]=\frac{1}{3}\left[\begin{array}{ccc}\hfill 2\hfill & \hfill 1\hfill & \hfill 1\hfill \\ \hfill -1\hfill & \hfill 1\hfill & \hfill 1\hfill \\ \hfill -1\hfill & \hfill -2\hfill & \hfill 1\hfill \end{array}\right]\left[\begin{array}{c}\hfill v_{\mathit{ab}}\hfill \\ \hfill v_{bc}\hfill \\ \hfill 0\hfill \end{array}\right]$

that can be further simplified to

$\left[\begin{array}{c}\hfill v_{\mathit{an}}\hfill \\ \hfill v_{bn}\hfill \\ \hfill v_{cn}\hfill \end{array}\right]=\frac{1}{3}\left[\begin{array}{ll}2\hfill & 1\hfill \\ -1\hfill & 1\hfill \\ -1\hfill & -2\hfill \end{array}\right]\left[\begin{array}{c}\hfill v_{\mathit{ab}}\hfill \\ \hfill v_{bc}\hfill \end{array}\right]$

The final expression for the phase-load voltages is only a function of v_ab and v_bc, which is due to the fact that the last row in Eq. (11.42) is chosen to be only ones. Fig. 11.28 shows the line and phase voltages obtained using Eq. (11.44).

In the particular case of a square-wave three-phase VSI, this is known as a six-step inverter because of the six voltage changes per output voltage cycle.