11.4.4.1 Space-Vector Transformation in CSIs

Similarly to VSIs, the vector of three-phase line-modulating signals ${\mathbf{i}}_{\mathbf{c}}^{\mathrm{a}\mathrm{b}\mathrm{c}}={\left[i_{ca}{i}_{cb}{i}_{\mathit{cc}}\right]}^T$ can be represented by the complex vector ${\overrightarrow{\mathbf{i}}}_{\mathbf{c}}={\mathbf{i}}_{\mathbf{c}}^{\mathrm{\alpha }\mathrm{\beta }}={\left[i_{c\alpha }{i}_{c\beta }\right]}^T$ by means of Eqs. (11.31) and (11.32). For three-phase balanced sinusoidal modulating waveforms, which feature an amplitude î_c and an angular frequency ω, the resulting modulating signal complex vector ${\overrightarrow{\mathbf{i}}}_{\mathbf{c}}={\mathbf{i}}_{\mathbf{c}}^{\mathrm{\alpha }\mathrm{\beta }}$ becomes a vector of fixed module î_c, which rotates at frequency ω (Fig. 11.37). Similarly, the SV transformation is applied to the line currents of the nine states of the CSI normalized with respect to i_i, which generates nine space vectors (${\overrightarrow{\mathbf{i}}}_{\mathbf{i}}$, $i=1,2,\dots ,9$ in Fig. 11.37). As expected, ${\overrightarrow{\mathbf{i}}}_1$ to ${\overrightarrow{\mathbf{i}}}_6$ are nonnull line current vectors, and ${\overrightarrow{\mathbf{i}}}_7$, ${\overrightarrow{\mathbf{i}}}_8$, and ${\overrightarrow{\mathbf{i}}}_9$ are null line current vectors.

The SV technique approximates the line-modulating signal space vector ${\overrightarrow{\mathbf{i}}}_{\mathbf{c}}$ by using the nine space vectors (${\overrightarrow{\mathbf{i}}}_i$, $i=1,2,\dots ,9$) available in CSIs. If the modulating signal vector ${\overrightarrow{\mathbf{i}}}_{\mathbf{c}}$ is between the arbitrary vectors ${\overrightarrow{\mathbf{i}}}_i$ and ${\overrightarrow{\mathbf{i}}}_{i+1}$, then ${\overrightarrow{\mathbf{i}}}_i$ and ${\overrightarrow{\mathbf{i}}}_{i+1}$ combined with one zero SV (${\overrightarrow{\mathbf{i}}}_z={\overrightarrow{\mathbf{i}}}_7$ or ${\overrightarrow{\mathbf{i}}}_8$ or ${\overrightarrow{\mathbf{i}}}_9$) should be used to generate ${\overrightarrow{\mathbf{i}}}_{\mathbf{c}}$. To ensure that the generated current in one sampling period T_s (made up of the currents provided by the vectors ${\overrightarrow{\mathbf{i}}}_i$, ${\overrightarrow{\mathbf{i}}}_{i+1}$, and ${\overrightarrow{\mathbf{i}}}_z$ used during times T_i, $T_{i+1}$, and $T_z)$ is on average equal to the vector ${\overrightarrow{\mathbf{i}}}_{\mathbf{c}}$, the following expressions should hold:

$T_i=T_s\cdot {\hat{i}}_c\cdot sin\left(\pi /3-\theta \right)$

$T_{i+1}=T_s\cdot {\hat{i}}_c\cdot sin\left(\theta \right)$

$T_z=T_s-T_i-T_{i+1}$

where $0\le {\hat{i}}_c\le 1$. Although the SVM technique selects the vectors to be used and their respective on-times, the sequence in which they are used, the selection of the zero space vector, and the normalized sampled frequency remain undetermined.

11.4.4.2 Space-Vector Sequences and Zero Space-Vector Selection

Although there is no systematic approach to generate a SV sequence, a graphic representation shows that the sequence ${\overrightarrow{\mathbf{i}}}_i$, ${\overrightarrow{\mathbf{i}}}_z$, ${\overrightarrow{\mathbf{i}}}_{i+1}$ (where the chosen ${\overrightarrow{\mathbf{i}}}_z$ depends upon the sector) provides high performance in terms of minimizing unwanted harmonics and reducing the switching frequency. To obtain the zero SV that minimizes the switching frequency, it is assumed that I_c is in sector ②. Then, Fig. 11.38 shows all the possible transitions that could be found in sector ②. It can be seen that the zero vector ${\overrightarrow{\mathbf{i}}}_9$ should be chosen to minimize the switching frequency in all cases. Table 11.7 gives a summary of the zero space vector to be used in each sector in order to minimize the switching frequency. However, it should be noted that Table 11.7 is valid only for the sequence ${\overrightarrow{\mathbf{i}}}_i$, ${\overrightarrow{\mathbf{i}}}_{i+1}$, ${\overrightarrow{\mathbf{i}}}_z$. Another sequence will require reformulating the zero space-vector selection algorithm.

Table 11.7

Zero SV for minimum switching frequency in CSI and sequence ${\overrightarrow{\mathbf{i}}}_i$, ${\overrightarrow{\mathbf{i}}}_{i+1}$, ${\overrightarrow{\mathbf{i}}}_z$

Sector	${\overrightarrow{\mathbf{i}}}_i$	${\overrightarrow{\mathbf{i}}}_{i+1}$	${\overrightarrow{\mathbf{i}}}_z$
①	${\overrightarrow{\mathbf{i}}}_6$	${\overrightarrow{\mathbf{i}}}_1$	${\overrightarrow{\mathbf{i}}}_7$
②	${\overrightarrow{\mathbf{i}}}_1$	${\overrightarrow{\mathbf{i}}}_2$	${\overrightarrow{\mathbf{i}}}_9$
③	${\overrightarrow{\mathbf{i}}}_2$	${\overrightarrow{\mathbf{i}}}_3$	${\overrightarrow{\mathbf{i}}}_8$
④	${\overrightarrow{\mathbf{i}}}_3$	${\overrightarrow{\mathbf{i}}}_4$	${\overrightarrow{\mathbf{i}}}_7$
⑤	${\overrightarrow{\mathbf{i}}}_4$	${\overrightarrow{\mathbf{i}}}_5$	${\overrightarrow{\mathbf{i}}}_9$
⑥	${\overrightarrow{\mathbf{i}}}_5$	${\overrightarrow{\mathbf{i}}}_6$	${\overrightarrow{\mathbf{i}}}_8$

11.4.4.3 The Normalized Sampling Frequency

As in VSIs modulated by an SV approach, the normalized sampling frequency f_sn should be an integer multiple of 6 to minimize uncharacteristic harmonics. As an example, Fig. 11.39 shows the relevant waveforms of a CSI SVM for $f_{sn}=18$ and ${\hat{i}}_c=0.8$. Fig. 11.39 also shows that the first set of relevant harmonics load line current are at f_sn.

11.5.1.1 Neutral Point Clamped Inverter

In Fig. 11.42, the neutral-point-clamped inverter is shown (three levels). For this topology, not only an M-level inverter requires (M−1) capacitors and 2(M−1) switching semiconductors per leg, but also 2(M−2) additional diodes must be included per leg; for instance, D_a+ and D_a− are added for the left leg. M−1 devices per leg must be on to select the desired level.

Table 11.8 gives the switch states of the three-level inverter, just left leg. As it can be observed, not only always two switches are on, but also the signal S_1a is the opposite of S_4a, and S_1b is the opposite of S_4b. These conditions must be always satisfied. The switch states for phases b and c are identical to those of phase a.

Table 11.8

Valid switch states for the three-level neutral-point-clamped inverter, the left leg

s1a	s1b	s4a	s4b	van	Components conducting
1	1	0	0	vi/2	S1a, S1b	If $i_{oa}>0$
					D1a, D1b	If $i_{oa}<0$
0	1	1	0	0	S1b, $D_{a+}$	If $i_{oa}>0$
					S4a, $D_{a-}$	If $i_{oa}<0$
0	0	1	1	$-v_i/2$	D4a, D4b	If $i_{oa}>0$
					S4a, S4b	If $i_{oa}<0$

11.5.1.2 Flying Capacitors Inverter

In Fig. 11.43, the flying capacitor inverter is shown (three levels). For this topology, an M-level inverter requires ${\displaystyle {\sum }_{j=1}^{M-1}\left(M-j\right)}$ capacitors per leg (considering that the capacitors have the same voltage rating) and 2(M−1) switching semiconductors per leg, but no additional diodes are required. Also M−1 switches per leg must be on to select the desired level.

Table 11.9 is the switch state of the three-level inverter, just left leg. As it can be observed, not only always two switches are on, but also the signal S_1a is the opposite of S_4a, and S_1b is the opposite of S_4b. These conditions must be always satisfied. Table 11.9 shows that there is more than one switching state to produce the zero output level; this redundancy should be employed to distribute the losses or to regulate the capacitor voltages. Moreover, as the number of levels increase, more redundancy exists at different levels.

Table 11.9

Valid switch states for the three-level flying capacitors inverter, left leg

s1a	s1b	s4a	s4b	vaN	Components conducting
1	1	0	0	vi/2	S1a, S1b	If $i_{oa}>0$
					D1a, D1b	If $i_{oa}<0$
1	0	0	1	0	S1a, D4b	If $i_{oa}>0$
					D1a, S4b	If $i_{oa}<0$
0	1	1	0	0	S1b, D4a	If $i_{oa}>0$
					D1b, S4a	If $i_{oa}<0$
0	0	1	1	$-v_i$ /2	D4a, D4b	If $i_{oa}>0$
					S4a, S4b	If $i_{oa}<0$

11.5.1.3 Casacade Inverter

In Fig. 11.44, the cascade inverter is shown (five levels). This topology is based on several full-bridge single-phase voltage-source inverters with their output connected in series. An M-level inverter requires (M−1)/2 single-phase full-bridge VSI per leg and 2(M−1) switching semiconductors per leg, but no additional diodes are required. Also M−1 switches per leg must be on to select the desired level.

Table 11.10 gives the switch states of the five-level inverter. Notice that only the top switch control signals of each single-phase full-bridge VSI are shown. Their respective bottom switch control signals are complementary, in order to accomplish with the first compulsory rule for VSIs. As it can be observed, always four devices are on; notice that since a single-phase full-bridge inverter is used, the same rules apply for the control signals of the semiconductors. As it can be observed in Table 11.10, there are more than one switching state to produce some output levels; this redundancy should be employed to distribute the losses. Moreover, as the number of levels increases, more redundancy exists at different levels.

Table 11.10

Valid switch states for the five-level cascade inverter, left leg

$s_{21+}$	$s_{22+}$	$s_{11+}$	$s_{12+}$	van
1	0	1	0	vi
1	0	0	0	vi/2
1	0	1	1	vi/2
0	0	1	0	vi/2
1	1	1	0	vi/2
0	0	0	0	0
0	0	1	1	0
1	0	0	1	0
0	1	1	0	0
1	1	0	0	0
1	1	1	1	0
0	1	0	0	$-v_i/2$
0	1	1	1	$-v_i/2$
0	0	0	1	$-v_i/2$
1	1	0	1	$-v_i/2$
0	1	0	1	$-v_i$

11.5.3.1 The SPWM Technique

The main objective is to generate the appropriate gating signals so as to obtain fundamental inverter phase voltages or currents equal to a given set of modulating signals. Specifically, the SPWM in three-level VSIs uses a sinusoidal set of modulating signals (v_ca, v_cb, and v_cc for phases a, b, and c, respectively) and M−1=2 triangular type of carrier signals (v_Δ1 and v_Δ2) as illustrated in Fig. 11.46A. The best results are obtained if the carrier signals are in-phase (synchronized with the modulating signal) and feature an odd normalized frequency (e.g., $m_f=15$). According to Fig. 11.46A and considering a neutral-point-clamped inverter (Fig. 11.42), the switch S_1a is turned either on if $v_{ca}>v_{\mathrm{\Delta }1}$ or off if $v_{ca}<v_{\mathrm{\Delta }1}$, and switch S_1b is turned either on if $v_{ca}>v_{\mathrm{\Delta }2}$ or off if $v_{ca}<v_{\mathrm{\Delta }2}$. Additionally, the switch S_4a status is obtained as the opposite to switch S_1a, and the switch S_4b status is obtained as the opposite to switch S_1b. In order to use the same set of carrier signals to generate the gating signals for phases b and c, the normalized frequency of the carrier signal m_f should be a multiple of 3. Thus, the possible values are $m_f=3,9,15,21,\dots$.

Fig. 11.46 shows the relevant waveforms for a three-level neutral-point-clamped inverter modulated by means of an SPWM technique ($m_f=15$, $m_a=0.8$). Specifically, Fig. 11.46D shows the inverter phase voltage, which is clearly a three-level type of voltage, and Fig. 11.46F shows the load line voltage, which shows that the step voltages are at most v_i/2. More importantly, the inverter phase voltage (Fig. 11.46E) contains harmonics at $l\cdot m_f\pm k$ with $l=1,3,\dots$ and $k=0,2,4,\dots$ and at $l\cdot m_f\pm k$ with $l=2,4,\dots$ and $k=1,3,\dots$. For instance, the first set of harmonics ($l=1$, $m_f=15$) are at 15, $15\pm 2$, $15\pm 4,\dots$. The inverter line voltage (Fig. 11.46G) contains harmonics at $l\cdot m_f\pm k$ with $l=1,3,\dots$ and $k=2,4,\dots$ and at $l\cdot m_f\pm k$ with $l=2,4,\dots$ and $k=1,3,\dots$. For instance, the first set of harmonics in the line voltages ($l=1$, $m_f=15$) are at $15\pm 2$, $15\pm 4,\dots$.

All the other features of carrier-based PWM techniques also apply in multilevel inverters. Firstly, the fundamental component of the inverter phase voltages satisfies

${\hat{v}}_{\mathit{aN}1}={\hat{v}}_{bN1}={\hat{v}}_{cN1}=m_a\frac{v_i}{2}0<m_a\le 1$

and thus, the line voltages satisfy

${\hat{v}}_{\mathit{ab}1}={\hat{v}}_{bc1}={\hat{v}}_{ca1}=m_a\sqrt{3}\frac{v_i}{2}0<m_a\le 1$

where $0<m_a\le 1$ is the linear operating region. To further increase the amplitude of the load voltages, the overmodulation operating region can be used by further increasing the modulating signal amplitudes ($m_a>1$), where the line voltages range in

$\sqrt{3}\frac{v_i}{2}<{\hat{v}}_{\mathit{ab}1}={\hat{v}}_{bc1}={\hat{v}}_{ca1}<\frac{4}{\pi }\sqrt{3}\frac{v_i}{2}$

Second, the modulating signals could be improved by adding a third harmonic (zero sequence), which will increase the linear region up to $m_a=1.15$. This results in a maximum fundamental line-voltage component equal to v_i; as a third point, a nonsinusoidal set of modulating signals could also be used by the modulating technique. This is the case where nonsinusoidal line voltages are required as in active filter applications, and finally, because of the two quadrants operation of VSIs, the multilevel inverter could equally be used in applications where the active power flow goes from the dc to the ac side or from the ac to the dc side.

In general, for an M-level inverter modulated by means of a carrier-based technique, three modulating signals 120° out of phase and M−1 carrier signals are required. Key waveforms are shown in Fig. 11.47.

One of the drawbacks of the multilevel inverter is that the dc link capacitor voltages or inductor currents, depending on the type of inverter, should be regulated. Unfortunately, this is not a natural operating condition mainly due to the fact that the storage elements are operated in a not symmetrical manner, and therefore, they will not equally share energy.

11.5.3.2 The SPWM Technique in Three-level CSIs

As in three-level VSIs, the main objective is to generate the appropriate 12 gating signals so as to obtain fundamental inverter line currents equal to a given set of modulating signals. Specifically, the SPWM in three-level inverters uses a sinusoidal set of modulating signals (i_ca, i_cb, and i_cc for phases a, b, and c, respectively) and $N-1=2$ triangular type of carrier signals (i_Δ1 and i_Δ2) as illustrated in Fig. 11.48A and E. The best results are obtained if the carrier signals are 180° out of phase and feature an odd normalized frequency (e.g., $m_f=15$). In order to use the same set of carrier signals to generate the gating signals for phases b and c, the normalized frequency of the carrier signal m_f should be a multiple of 3. Thus, the possible values are $m_f=3,9,15,21,\dots$.

Fig. 11.48 shows the relevant waveforms for a three-level inverter modulated by means of an SPWM technique ($m_f=15$, $m_a=0.8$). Specifically, Fig. 11.48B and F show the gating signals obtained as described earlier in this chapter. The inverter line currents shown in Fig. 11.48C and G feature spectra shown in Fig. 11.48D and H, respectively. As expected, the inverter line currents contain harmonics at $l\cdot m_f\pm k$ with $l=1,3,\dots$ and $k=2,4,\dots$ and at $l\cdot m_f\pm k$ with $l=2,4,\dots$ and $k=1,3,\dots$. For instance, the first set of harmonics in the line currents ($l=$ 1, $m_f=15$) are at $15\pm 2$, $15\pm 4,\dots$.

The total inverter line current is shown in Fig. 11.49A and features the first set of unwanted harmonics around 2m_f (Fig. 11.49B). This becomes the first advantage of using a multilevel topology as the filtering component requirements become more relaxed. All the other features of carrier-based PWM techniques also apply in current-source multilevel inverters. For instance, (I) the fundamental component of the line currents satisfies

${\hat{i}}_{oa1}={\hat{i}}_{ob1}={\hat{i}}_{oc1}=m_a\frac{\sqrt{3}}{2}\left(i_{i1}+i_{i2}\right)0<m_a\le 1$

where $0<m_a\le 1$ is the linear operating region. Also, (II) to further increase the amplitude of the load currents, a zero-sequence signal could be injected to the modulating signals, in this case,

${\hat{i}}_{oa1}={\hat{i}}_{ob1}={\hat{i}}_{oc1}=m_a\frac{\sqrt{3}}{2}\left(i_{i1}+i_{i2}\right)0<m_a\le 2/\sqrt{3}$

the overmodulation operating region can be used by further increasing the modulating signal amplitudes ($m_a>2/\sqrt{3}$), where the line currents range in

$\left(i_{i1}+i_{i2}\right)<{\hat{i}}_{oa1}={\hat{i}}_{ob1}={\hat{i}}_{oc1}<\frac{4}{\pi }\left(i_{i1}+i_{i2}\right)$

Also, (III) a nonsinusoidal set of modulating signals could also be used by the modulating technique. This is the case where nonsinusoidal line currents are required as in active filter applications, and (IV) because of the two quadrants operation of CSIs, the multilevel inverter could equally be used in applications where the active power flow goes from the dc to the ac side or from the ac to the dc side. In general, for an N-level inverter modulated by means of a carrier-based technique, three modulating signals 120° out of phase and $N-1$ carrier signals are required, and the line currents in the inverters have a peak value of i_i/($N-1$).

One of the drawbacks of the multilevel inverter is that the dc link capacitors cannot be supplied by a single dc voltage source. This is due to the fact that the currents required by the inverter in the dc bus are not symmetrical, and therefore, the capacitors will not equally share the dc supply voltage v_i. To overcome this problem, two alternatives are developed later on.

11.5.3.3 The Space-Vector Modulation

The SV modulating technique can be applied using the same principles used in two-level inverters. However, the higher number of voltage levels increases the complexity of the practical implementation of the technique. For instance, in M=3-level inverters, each leg allows M=3 different switch combinations as indicated in the previous sections. Therefore, in a three-phase system, there are M ³=27 total valid switch combinations, which generate M ³=27 load line voltages that are represented by M ³=27 space vectors (${\overrightarrow{\mathbf{v}}}_1$, ${\overrightarrow{\mathbf{v}}}_2,\dots ,{\overrightarrow{\mathbf{v}}}_{27}$) in Fig. 11.50. For instance, ${\overrightarrow{\mathbf{v}}}_2=0.5+j0.866$ is due to the line voltages $v_{\mathit{ab}}=0.5$, $v_{bc}=0.5$, $v_{ca}=-1.0$ in per unit. Thus, although the principle of operation is the same, the SV digital algorithm will have to deal with a higher number of states M ³. Moreover, because some space vectors (e.g., ${\overrightarrow{\mathbf{v}}}_{13}$ and ${\overrightarrow{\mathbf{v}}}_{14}$ in Fig. 11.50) produce the same load voltage terminals, the algorithm will have to decide between the two based on additional criteria and that of the basic SV approach. Clearly, as the number of level increases, the algorithm becomes more and more elaborate. However, the benefits are not evident as the number of level increases. The maximum number of levels used in practical applications is five. This is based on a compromise between the complexity of the implementation and the benefits of the resulting waveforms.

11.5.3.4 Balancing Issues

The operation for the multilevel converter was made considering an even distribution of the voltage across the dc link capacitors or current of the inductors, depending of the type of inverter. This even distribution is not naturally achieved and could be overcome by supplying the storage elements from independent supplies or properly gating the power semiconductors of the inverter in order to minimize the unbalance.

Fig. 11.51 shows an ASD based on a three-level VSI, where the dc link capacitors are feed from two different sources. This approach is being commercially used as it ensures a robust balanced dc link voltage distribution and operates with a high-performance type of ac main current. Indeed, for an M-level inverter, M−1-independent dc voltage supplies are required that could be provided by M−1 six-pulse rectifiers feed from an M−1 pulse transformer. Therefore, the ac main currents are an M−1-level type of waveform.

This approach cannot be used when the inverter does not feature dc link voltage supplies. This is the case of static power reactive power compensators and static power active filters. In this case, the proper gating of the power semiconductors becomes the only choice to keep and balance the dc link voltages. Fig. 11.52A shows this case where the current added by the inverter i_o^abc provides the reactive power and current harmonics such that the ac main current i_s^abc features a given power factor.

The SPWM modulating technique could be used as in Fig. 11.46; however, the zero level of the carrier δ is left as a manipulable variable in Fig. 11.52B. In fact, it is used to control the difference of the upper and lower capacitor voltages $\mathrm{\Delta }{v}_i=v_{i1}-v_{i2}$. A closed-loop alternative is depicted in Fig. 11.52C to manipulate δ. The modulating signals v_c^abc are left to control the reactive power and current harmonics injected into the ac mains by regulating the currents i_o^abc and keep the total dc link voltage $v_i=v_{i1}+v_{i2}$ equal to a reference. Both loops are not included in Fig. 11.52C.

11.6.2.1 Hysteresis Current Control

The main purpose here is to force the ac line current to follow a given reference. The status of the power semiconductors are changed whenever the actual i_oa current goes beyond a given reference $i_{oa,ref}\pm \mathrm{\Delta }i/2$. Fig. 11.57 shows the hysteresis current controller for one phase. Identical controllers are used in the other phases. The implementation of this controller is simple as it requires a simple comparator operating in the hysteresis mode; thus, the controller and modulator are combined in one unit.

Unfortunately, there are several drawbacks associated with the technique itself. First, the switching frequency cannot be predicted as in carrier-based modulators, and therefore, the harmonic content of the ac line voltages and currents becomes random (Fig. 11.58D). This could be a disadvantage when designing the filtering components. Second, as three-phase loads do not have the neutral connected as in ASDs, the load currents add up to zero. This means that only two ac line currents can be controlled independently at any given instant. Therefore, one of the hysteresis controllers is redundant at a given time. This explains why the load current goes beyond the limits and introduces limit cycles (Fig. 11.58A). Finally, although the ac load currents add up to zero, the controllers cannot ensure that all load line currents feature a zero dc component in one load cycle.

11.6.2.2 Linear Control of VSIs

Proportional and proportional-integrative controllers can also be used in VSIs by employing a transformation. The main purpose is to generate the modulating signals v_ca, v_cb, and v_cc in a closed-loop fashion as depicted in Fig. 11.59. The modulating signals can be used by a carrier-based technique such as the SPWM (as depicted in Fig. 11.59) or by space-vector modulation. Because the load line currents add up to zero, the load line current references must add up to zero. Thus, the abc/ αβγ transformation can be used to reduce to two controllers the overall implementation scheme as the γ component is always zero. This avoids limit cycles in the ac load currents.

The transformation of a set of variables in the stationary abc frame x^abc into a set of variables in the stationary αβ frame x^αβ is given by

  (11.67)

The selection of the controller (P, PI, …) is done according to the control procedures such as steady-state error, settling time, and overshoot. Fig. 11.60 shows the relevant waveforms of a VSI SPWM controlled by means of a PI controller as shown in Fig. 11.59.

Although it is difficult to prove that no limit cycles are generated, the ac line current appears very much sinusoidal. Moreover, the ac line voltage generated by the VSI preserves the characteristics of such waveforms generated by SPWM modulators.

However, an error between the actual i_oa and the ac line current reference i_oa,ref can be observed (Fig. 11.60A). This error is inherent to linear controllers and cannot be totally eliminated, but it can be minimized by increasing the gain of the controller. However, the noise in the circuit is also increased, which could deteriorate the overall performance of the control scheme. The inherent presence of the error in this type of controllers is due to the fact that the controller needs a sinusoidal error to generate sinusoidal modulating signals v_ca, v_cb, and v_cc, as required by the modulator. Therefore, an error must exist between the actual and the ac line current references.

Nevertheless, as current-controlled VSIs are actually the inner loops in many control strategies, their inherent errors are compensated by the outer loop. This is the case of ASDs, where the outer speed loop compensates the inner current loops. In general, if the outer loop is implemented with dc quantities (such as speed), it can compensate the ac inner loops (such as ac line currents). If it is mandatory that a zero steady-state error be achieved with the ac quantities, then a stationary (abc frame) to rotating (dq frame) transformation is a valid alternative to use.

11.6.2.3 Linear Control of VSIs in a Rotating Frame

The rotating dq transformation allows ac three-phase circuits to be operated as if they were dc circuits. This is based upon a mathematical operation, that is, the transformation of a set of variables in the stationary abc frame x^abc into a set of variables in the rotating dq0 frame x^dq0. The transformation is given by

${\mathbf{x}}^{\mathrm{d}\mathrm{q}}=\frac{2}{3}\left[\begin{array}{ccc}\hfill sin\left(\omega t\right)\hfill & \hfill sin\left(\omega t-2\pi /3\right)\hfill & \hfill sin\left(\omega t-4\pi /3\right)\hfill \\ \hfill cos\left(\omega t\right)\hfill & \hfill cos\left(\omega t-2\pi /3\right)\hfill & \hfill cos\left(\omega t-4\pi /3\right)\hfill \\ \hfill 1/\sqrt{2}\hfill & \hfill 1/\sqrt{2}\hfill & \hfill 1/\sqrt{2}\hfill \end{array}\right]{\mathbf{x}}^{\mathrm{a}\mathrm{b}\mathrm{c}}$

where ω is the angular frequency of the ac quantities. For instance, the current vector given by

${\mathbf{i}}^{\mathrm{a}\mathrm{b}\mathrm{c}}=\left[\begin{array}{c}\hfill i_a\hfill \\ \hfill i_b\hfill \\ \hfill i_c\hfill \end{array}\right]=\left[\begin{array}{c}\hfill Isin\left(\omega t-\phi \right)\hfill \\ \hfill Isin\left(\omega t-2\pi /3-\phi \right)\hfill \\ \hfill Isin\left(\omega t-4\pi /3-\phi \right)\hfill \end{array}\right]$

becomes the vector

${\mathbf{i}}^{\mathrm{d}\mathrm{q}0}=\left[\begin{array}{c}\hfill i_{\mathrm{d}}\hfill \\ \hfill i_{\mathrm{q}}\hfill \\ \hfill i_0\hfill \end{array}\right]=\left[\begin{array}{c}\hfill Icos\left(\phi \right)\hfill \\ \hfill -Isin\left(\phi \right)\hfill \\ \hfill 0\hfill \end{array}\right]$

where I and φ are the amplitude and phase of the line currents, respectively. It can be observed that (a) the zero-component i₀ is always zero as the three-phase quantities add up to zero and (b) the d and q components i_d, i_q are dc quantities. Thus, linear controllers should help to achieve zero steady-state error. The control strategy shown in Fig. 11.61 is an alternative where the zero-component controller has been eliminated due to the fact that the line currents at the load side add up to zero.

The controllers in Fig. 11.61 include an integrator that generates the appropriate dc outputs m_d and m_q even if the actual and the line current references are identical. This ensures that the zero steady-state error is achieved. The decoupling block in Fig. 11.61 is used to eliminate the cross coupling effect generated by the dq0 transformation and to allow an easier design of the parameters of the controllers.

The dq0 transformation requires the intensive use of multiplications and trigonometric functions. These operations can readily be done by means of digital microprocessors. Also, analog implementations would indeed be involved.

11.7.2.1 Occasional Regenerative Operating Mode

This mode is required during transient conditions such as in occasional braking of electric machines (ASDs). Specifically, the speed needs to be reduced, and the kinetic energy is taken into the dc bus. Because the motor line voltage is imposed by the VSI, the speed reduction should be done in such a way that the motor line currents do not exceed the maximum values. This boundary condition will limit the ramp-down speed to a minimum, but shorter braking times will require a mechanical braking system.

Fig. 11.65 shows a transition from the motoring to regenerative operating mode for an ASD as shown in Fig. 11.63. Here, a stiff dc bus voltage has been used. Zone I in Fig. 11.65 is the motoring mode, zone II is a transition condition, and zone III is the regeneration mode. The line voltage is adjusted dynamically to obtain nominal motor line currents during regeneration (Fig. 11.65D). Zone III clearly shows that the shaft power gets reversed.

Occasional regeneration means that the drive rarely goes into this operating mode. Therefore, such energy can be (a) left uncontrolled or (b) burned in resistors that are paralleled to the dc bus. The first option is used in low- to medium-power applications that use diode-based front-end rectifiers. Therefore, the dc bus current flows into the dc bus capacitor, and the dc bus voltage rises accordingly to

$\mathrm{\Delta }{v}_i=\frac{1}{C}{I}_i\mathrm{\Delta }t$

where Δv_i is the dc bus voltage variation, C is the dc bus voltage capacitor, I_i is the average dc bus current during regeneration, and Δt is the duration of the regeneration operating mode. Usually, the drives have the capacitor C designed to allow a 10% overvoltage in the dc bus.

The second option uses burning resistors R_R that are paralleled in the dc bus as shown in Fig. 11.66 by means of the switch S_R. A closed-loop strategy based on the actual dc bus voltage modifies the duty cycle of the turn-on/turnoff of the switch S_R in order to keep such voltage under a given reference. This alternative is used when the energy recovered by the VSI would result in an acceptable dc bus voltage variation if an uncontrolled alternative is used.

There are some special cases where the regeneration operating mode is frequently used. For instance, electric shovels in mining companies have repetitive working cycles, and $\approx 15\%$ of the energy is sent back into the dc bus. In this case, a valid alternative is to send back the energy into the ac distribution system.

The schematic shown in Fig. 11.67 is capable of taking the kinetic energy and sending it into the ac grid. As reviewed earlier, the regeneration operating mode reverses the polarity of the dc current i_i, and because the diode-based front-end converter cannot take negative currents, a thyristor-based front-end converter is added. Similarly to the burning resistor approach, a closed-loop strategy based on the actual dc bus voltage v_i modifies the commutation angle α of the thyristor rectifier in order to keep such voltage under a given reference.

11.7.2.2 Regenerative Operating Mode as Normal operating Mode

Fewer industrial applications are capable of returning energy into the ac distribution system on a continuous basis. For instance, mining companies usually transport their product downhill for a few kilometers before processing it. In such cases, the drive maintains the transportation belt conveyor at constant speed and takes the kinetic energy. Due to the large amount of energy and the continuous operating mode, the drive should be capable of taking the kinetic energy, transforming it into electric energy, and sending it into the ac distribution system. This would make the drive a generator that would compensate for the active power required by other loads connected to the electric grid.

The schematic shown in Fig. 11.68 is a modern alternative for adding regeneration capabilities to the VSI-based drive on a continuous basis. In contrast to the previous alternatives, this scheme uses a VSI topology as an active front-end converter, which is generally called voltage-source rectifier (VSR). The VSR operates in two quadrants, that is, positive dc voltages and positive/negative dc currents as reviewed earlier. This feature makes it a perfect match for ASDs based on a VSI. Some of the advantages of using a VSR topology are the following: (i) The ac supply current can be as sinusoidal as required (by increasing the switching frequency of the VSR or the ac line inductance), (ii) the operation can be done at a unity displacement power factor in both motoring and regenerative operating modes, and (iii) the control of the VSR is done in both motoring and regenerative operating modes by a single dc bus voltage loop.