5.3.4 SiC JFET

The SiC JFET has some benefits, such as a resistive forward characteristic in the first and third quadrants and a monolithic integrated body diode. It is comparable with available SiC Schottky diodes in terms of stored charge, low output capacitance, low gate charge, and low switching losses that makes it attractive for use.

The first commercialized SiC transistor was normally the ON JFET from SemiSouth Laboratories and SiCED Electronics Development. They were easy to implement as there were no reliability issues with gate oxide as with SiC MOSFETs. The JFETs are only depletion-mode, normally ON-type devices that conduct current at zero gate voltage and are fully blocked when the gate voltage is below the pinch-off voltage. The most successful JFET type, in terms of voltage and current ratings, has been the lateral channel JFET (LCJFET), shown in Fig. 5.8 The LCJFET allows optimization of the channel parameters and is easy to fabricate. Due to the combined lateral-vertical channel design, the LCJFET has significantly reduced Miller capacitance. A parasitic diode formed with the buried P region and the N drift region can be used as a freewheeling diode without an external antiparallel diode. Also, the current through the channels can flow in the reverse direction when enough gate-source voltage is applied; therefore, the LCJFET can work in synchronous rectification circuits.

When JFETs are ON, they exhibit constant resistance that can be minimized by increasing the gate voltage slightly higher than zero. A normally-ON device is not easy to use in a power application because losing the control can cause undesired conduction of the switch and, consequently, can lead to shoot-through current damaging the circuit [97].

A cascode configuration, shown in Fig. 5.9, composed of a SiC JFET and a series-connected low-voltage Si MOSFET, can overcome the problem and make a normally-ON JFET behave similarly to a conventional MOSFET. Typically, a 30 V MOSFET with very low ON-resistance controls the JFET conduction. When the two devices are conducting, the conduction losses of the MOSFET will be insignificant. When the Si MOSFET is turned on, the gate-source voltage of the JFET becomes zero, allowing current to pass from the drain to the source. The forward characteristics of a cascode configuration are determined by the gate-source voltage applied to the MOSFET.

During the OFF-state, the cascode exhibits a rugged avalanche behavior. Since in a cascode configuration the control device is a low-voltage Si MOSFET, it is easy to replace a power device with a cascode configuration packed as one device, because the control is made with the same voltage levels. The temperature coefficient of the ON-resistance of a SiC JFET is positive, which naturally protects the device from overshooting during high-temperature operation. However, there are some limitations with a cascode configuration. The maximum operating temperature in a cascode configuration is limited by the Si MOSFET, the Si MOSFET internal body diode shows a low dv/dt rating, limiting the switching frequency of the JFET, and the conduction losses are higher since the two devices are connected in series [98].

To overcome these limitations, gate drivers that can block a JFET have been designed. The driver output voltage swings from zero to negative voltage. The negative voltage level is less than the maximum pinch-off voltage of the device and, therefore, could cause a gate avalanche condition. In order to limit uncontrolled avalanche current, a parallel circuit, that includes a resistor, capacitor, and diode connected in series to the JFET gate, can be used. This parallel circuit is capable of limiting the avalanche current but supplying the high gate current peaks required for fast switching [99]. A disadvantage of using a special JFET driver is that a negative supply voltage should be provided to the drive circuit that complicates the control circuit of the device. Also, replacing a power device with a JFET in a power application is more complicated because the driver and the control are also affected.

In 2011, normally OFF vertical channel JFETs (VCJFETs) compatible with standard gate drive circuitry and featuring a positive temperature coefficient for ease in paralleling were commercially available. VCJFETs were based on a patented vertical channel trench structure from SemiSouth Laboratories, Inc. A typical high-voltage VCJFET is shown in Fig. 5.10.

When the channel voltage is smaller (V_CH<V_CHsat), a VCJFET works in the linear region and has an approximately constant ON-state resistance; the value of which is the sum of the channel and drift region resistance. The drain current, I_D, can be calculated by the following equation [100]:

$I_D=I_P\left[\frac{3V_{CH}}{V_P}-\frac{2}{V_P^{3/2}}\left[{\left(V_{CH}-V_{GS}+V_{\mathit{bi}}\right)}^{3/2}-{\left(V_{\mathit{bi}}-V_{GS}\right)}^{3/2}\right]\right]$

where I_P is the pinch-off current depending on the channel parameters, such as electron mobility, μ_n; doping concentration, N_CH; VCJFET thickness, Z; half of the width of the channel region, a; and the effective length of the channel. The pinch-off current is calculated by the following equation:

$I_P=\frac{q^2{\mu }_n{N}_{CH}^{2}Z{a}^3}{3{\varepsilon }_{\mathit{SiC}}{L}_{\mathit{eff}}}$

Since the drift region of a high-voltage SiC VCJFET is designed to support high voltage, the drift region is thick and lightly doped. Hence, the drift resistance will be significantly higher than other resistance through which the drain current is flowing. Therefore, the drift resistance should be included for calculating the channel voltage, V_CH:

$V_{CH}=V_{DS}-I_D{R}_{\mathit{Drift}}$

where R_Drift is the drift resistance. To simplify the expression for calculating the drift resistance, the current spreading effect of the current coming from the channel can be neglected; then, the drift resistance can be calculated as the resistance of the rectangular area in the drift region under the channel:

$R_{\mathit{Drift}}=\frac{L_{\mathit{Drift}}-W_D}{q{\mu }_n{N}_{\mathit{Drift}}Z{W}_{\mathit{Drift}}}$

where L_Drift and W_Drift are the drift region thickness and the width and N_Drift is the doping concentration of the lightly doped drift region.

The pinch-off voltage depends on the channel parameters and can be calculated by the equation:

$V_P=\frac{q{N}_{CH}{a}^2}{2{\varepsilon }_{\mathit{SiC}}}$

The built-in voltage is

$V_{\mathit{bi}}=\frac{kT}{q}ln\left(\frac{N_{CH}{N}_P}{n_i^2}\right)$

where N_P is the doping concentration of the gate.

When the channel voltage is increased so that V_CH>V_CHsat, the drain current saturates. The saturation current is defined by the following equation:

$V_{\mathit{CHsat}}=V_P-V_{GS}+V_{\mathit{bi}}$

There are two reasons for the drain current to saturate. One reason is that the depletion region becomes progressively wider toward the drain side causing a reduction of channel width and an increase of channel resistance. The other reason is that due to the presence of a high electric field in the channel, the carrier velocity saturates. The saturated drain current, I_DSAT, can be calculated by the equation [100]:

$I_{\mathit{DSAT}}=I_P\left[1-3\frac{V_{\mathit{bi}}-V_{GS}}{V_P}+2{\left(\frac{V_{\mathit{bi}}-V_{GS}}{V_P}\right)}^{3/2}\left[1+\lambda \left(V_{CH}-V_{\mathit{CHSAT}}\right)\right]\right]$

The multiplication term $\left[1+\lambda \left(V_{CH}-V_{\mathit{CHSAT}}\right)\right]$ in Eq. (5.96) is used to account for the channel modulation effect.

A benefit of a VCJFET is that it can be used in directions, forward and reverse, in a converter circuit. The reverse I–V characteristics do not saturate as do the forward I–V characteristics. The reason for this is that when the drain current is in the reverse direction, V_GD>V_GS, the channel closes so the drain side will be wide open. As a result, as V_SD increases, the channel is never pinched off when V_GS>V_th, while when V_GS<V_th, the channel is always pinched off on the side of the source and wide open on the drain side. Therefore, it is possible for a VCJFET to be used for freewheeling, although no parasitic diode is formed between the source and the drain [101].

In order to model the switching losses of a VCJFET, the capacitance between gate and source, C_GS, and the capacitance between gate and drain, C_GD, should be known. The gate-source capacitance is

$C_{GS}=\frac{K_{GS}{\varepsilon }_{\mathit{SiC}}{A}_{GS}}{W_S}$

where K_GS is the coupling area, the coefficient of the gate and source; A_GS is the coupling area between gate and source; and W_S is the depletion width between the gate and source. The depletion width can be calculated by

$W_S=\sqrt{\frac{2{\varepsilon }_{\mathit{SiC}}}{q{N}_{CH}}}\left(V_{\mathit{bi}}-V_{GS}\right)$

The gate-to-drain capacitance is

$C_{GD}=\frac{{\varepsilon }_{\mathit{SiC}}{A}_{GD}}{W_D}$

where the width of the depletion region between the gate and the drain is

$W_D=\sqrt{\frac{2{\varepsilon }_{\mathit{SiC}}}{q{N}_{CH}}}\left(V_{CH}+V_{\mathit{bi}}-V_{GS}\right)$

Some of the parameters of SiC JFETs and MOSFETs are presented in Table 5.7 as their switching losses FOM (SLFOM) and conduction losses FOM (CLFOM). The MOSFET FOMs are smaller although the MOSFET current is higher. In 2009, it was stated that a SiC MOSFET would be the device of choice as soon as the SiO₂/SiC interface and reliability issues were resolved [104]. The two companies that were producing JFETs no longer exist. Infineon Technologies discontinued their JFET products. Other SiC companies are more interested in production and development of SiC MOSFETs; therefore, the future of the SiC JFET is still unknown.

Table 5.7

Parameters and FOMs for 1200 V SiC devices

Type	Part number	Company	ID (A)	$R_{{}_{SP-\mathit{ON}}}$ (mΩ)	QSW (nC)	QG (nC)	SLFOM	CLFOM
JFET	IJW120R100T1 [102]	Infineon	26	100	48	72	4800	7200
MOSFET	SCT3017AL [103]	Cree	40	52	65	115	3380	5980

5.3.5 SiC BJT

Power BJTs in SiC are very attractive for power switching applications due to their very low specific ON-resistance and high-temperature operation with high power densities [105]. The common-emitter gain, β; the specific on-resistance, R_{SP_ON}; and the open-base breakdown voltage, BV_CEO, are important parameters that should be accounted for in choosing a device for a power application. The current gain should be high enough to reduce the base current that controls the BJT. Considerable work has been done to improve device performance. One of the main challenges is to increase the current gain of 4H-SiC BJTs [106] that is limited by the surface recombination [105]. Reducing the surface recombination current by optimizing the surface passivation improves the current gain [107]. Also, the common-emitter current gain can be improved by increasing the minority carrier lifetime in the base and emitter regions [108]. The maximum current gain for high-voltage SiC BJTs that has been reported in the literature is 335 for a 600 V device [109].

To increase the blocking voltage, the growth of high-purity SiC homoepitaxial thin films on SiC single-crystal wafers is required to form N⁻N⁺ wafer structures [110]. The maximum open-base breakdown voltage, BV_CEO, for a SiC BJT was reported to be 6 kV, but the gain was only 3 [111]. Further work is necessary to improve the design and to develop a new processing technology so that an increase in BV_CEO can be achieved without sacrificing the current gain of the transistor. Also, the conduction and switching power losses should be minimized. The conduction losses depend on the collector-emitter voltage and the collector current.

The voltage drop, V_CE, across the high-power SiC BJT is composed of six components, including the voltages across the junctions, J₀, J₁, and pseudojunction, J₂; the voltage across the two depletion regions, V_d1 and V_d2; and the voltage across the carrier storage region (CSR), $V_{N^{-}}$:

$V_{CE}=V_{j0}+V_{j1}+V_{j2}-V_{d1}-V_{d2}+V_{N^{-}}$

A basic one-dimensional structure of a power BJT is illustrated in Fig. 5.11. The BJT is divided into four regions: N⁺ emitter, P base, N⁻ drift, and N⁺ collector. The external (emitter base and collector currents, I_E, I_B, and I_C) and internal electron and hole and displacement currents (at junctions J₀—I_n0, I_p0; J₁—I_n1, I_p, and I_disp1; and J₂—I_n2, I_p2, and I_disp2) are indicated for each region.

The N⁺ emitter layer of a power BJT can be simply characterized as a hole sink. The hole current at the junction, J₀, is obtained by the following equation:

$I_{p0}=qA{h}_n{n}_{B0}{P}_B$

where n_B0 is the electron concentration at junction J₀ and P_B is the base doping concentration. The N⁺ emitter recombination parameter, h_n, depends on emitter properties, such as doping level (N_E), hole diffusivity (D_p), and hole minority lifetime (τ_p). The electron current component at junction J₀ is determined by

$I_{n0}=I_C-I_{p0}$

and the voltage drop across junction J₀ is

$V_{j0}=V_{T}ln\left(\frac{n_{B0}\left(n_{B0}+P_B\right)}{n_i^2}\right)$

The equation for the P-base region can be used to derive the boundary current at junction J₁. The lumped-charge method is used to model the behavior in the base region due to its moderate doping level and comparatively narrow base width. The injected carrier distribution in the base region during conduction is shown in Fig. 5.12.

Using the continuity equation for the base region, the injected minority carrier charge is described by the relation:

$\frac{d{Q}_B}{dt}+\frac{Q_B}{{\tau }_{BHL}}=I_{n0}-I_{n1}=I_B+I_{p1}+I_{\mathit{disp}1}-I_{p0}$

where τ_BHL is the high-level lifetime in the P-base region.

The total electron charge in the base is expressed as

$Q_B=\frac{n_{B0}+n_{B1}}{2}qA{W}_B$

where W_B is the base width. The electron concentration at the base region boundary on the collector side, n_B1, is related to the excess carrier concentration, p_x1, by the doping concentration of the base, P_B, by the equation:

$n_{B1}=\frac{p_{x1}^2}{P_B}$

Since the diffusion length in the base region is much greater than the base width, the gradient of the electron concentration is approximately linear, giving the electron current at the base-collector junction, J₁, as

$I_{n1}=q{D}_{n}A\frac{n_{B0}-n_{B1}}{W_B}$

The base-emitter voltage V_BE is calculated by the equation:

$V_{\mathit{BE}}=V_{T}ln\left(\frac{n_{B0}{P}_B}{n_i^2}+1\right)$

The voltage drop in N⁻ drift region is calculated during the ON-state in a manner similar to that of a PiN diode. The injected excess carrier concentration is determined by the ADE. As for all power switches, high-level injection and quasineutral conditions exist. Under high-level injection conditions, the ADE for the lightly doped drift describes the carrier dynamics of the majority carriers:

$D\frac{{\partial }^{2}p\left(x,t\right)}{\partial x^2}=\frac{p\left(x,t\right)}{\tau }+\frac{\partial p\left(x,t\right)}{\partial t}$

where D is the ambipolar diffusion coefficient, τ is the high-level carrier lifetime within the drift region, and p(x, t) is the excess carrier concentration. The Fourier series solution of the ADE is given by the following first-order differential equations as each of them refers to a harmonic, p_k(t), of the total minority carrier density, p(x,t):

For k>0

$\begin{array}{l}D\left[{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x_2}{\left.{\left(-1\right)}^k-\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x_1}\right]\\ =\frac{x_2-x_1}{2}\left(\frac{d{p}_k\left(t\right)}{dt}+\left[\frac{1}{\tau }+\frac{D{k}^2{\pi }^2}{{\left(x_2-x_1\right)}^2}\right]p_k\left(t\right)\right)\\ +\left({\displaystyle \sum _{\begin{array}{l}n=1\\ n\ne k\end{array}}^{\infty }\frac{n^2}{n^2-k^2}}\left[\frac{d{x}_1}{dt}-{\left(-1\right)}^{n+k}\frac{d{x}_2}{dt}\right]p_n\left(t\right)+\frac{p_k}{4}\left(\frac{d{x}_1}{dt}-\frac{d{x}_2}{dt}\right)\right)\end{array}$

for $k=0$

$\begin{array}{l}D\left[{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x_2}-{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x_1}\right]=\left(x_2-x_1\right)\frac{d{p}_0\left(t\right)}{dt}+\frac{p_0\left(t\right)}{\tau }\\ +{\displaystyle \sum _{n=1}^{\infty }\left[\frac{d{x}_1}{dt}-{\left(-1\right)}^n\frac{d{x}_2}{dt}\right]}{p}_n\left(t\right)\end{array}$

The solution to the ADE is determined by using the boundary conditions at the edges of the charge storage region. The representation requires the width of the undepleted region and the hole and electron currents at the boundaries of the drift region, which give the gradients of the carrier concentrations at x₁ and x₂, respectively. For the given direction of the currents (Fig. 5.13), the required boundary conditions are given by the equations:

${\left.\frac{\partial p}{\partial x}\right|}_{x_1}={\left.\frac{1}{2q}\left(\frac{J_n}{D_n}+\frac{J_p}{D_p}\right)\right|}_{x_1}\mathrm{and}{\left.\frac{\partial p}{\partial x}\right|}_{x_2}={\left.\frac{1}{2q}\left(\frac{J_n}{D_n}+\frac{J_p}{D_p}\right)\right|}_{x_2}$

Using the boundary condition Equation (5.112), the left side of Eq. (5.111), for even and odd numbers of k, can be calculated by the following equations:

$I_{\mathit{even}}=D\left({\left.\frac{\partial p}{\partial x}\right|}_{x_2}-{\left.\frac{\partial p}{\partial x}\right|}_{x_1}\right)=\frac{1}{2qA}\left|\begin{array}{l}{I}_{n1}\\ I_{p1}\\ I_{n2}\\ I_{p2}\end{array}\right|\left|-\frac{D}{D_n}-\frac{D}{D_p}+\frac{D}{D_n}+\frac{D}{D_p}\right|$

$I_{\mathit{odd}}=D\left({\left.\frac{\partial p}{\partial x}\right|}_{x_2}-{\left.\frac{\partial p}{\partial x}\right|}_{x_1}\right)=-\frac{1}{2qA}\left|\begin{array}{l}{I}_{n1}\\ I_{p1}\\ I_{n2}\\ I_{p2}\end{array}\right|\left|\frac{D}{D_n}\frac{D}{D_p}\frac{D}{D_n}\frac{D}{D_p}\right|$

The boundary carrier densities, p_x1 and p_x2, at the boundaries, x₁ and x₂, are calculated using the equations:

$p_{x_1}={\displaystyle \sum _{k=1}^n{p}_k}\mathrm{and}{p}_{x_2}={\displaystyle \sum _{k=1}^n{\left(-1\right)}^k{p}_k}$

The voltages across the N⁻N⁺ and N⁻P⁺ depletion layers, V_d1 and V_d2, are calculated by the following equations:

$\begin{array}{l}{V}_{d1}=\left\{\begin{array}{cc}\hfill 0\hfill & \hfill \mathrm{if}{p}_{x1}>0,\hfill \\ \hfill -K_{FV}{p}_{x1}\hfill & \hfill \mathrm{otherwise}.\hfill \end{array}\right.\\ V_{d2}=\left\{\begin{array}{cc}\hfill 0\hfill & \hfill \mathrm{if}{p}_{x1}>0,\hfill \\ \hfill -K_{FV}{p}_{x2}\hfill & \hfill \mathrm{otherwise}\text{.}\hfill \end{array}\right.\end{array}$

The feedback constant, K_FV, is set to 10⁻¹², which gives good convergence and minimal error [68]. The associated depletion widths, W_d1 and W_d2, are calculated using a step doping concentration change on each side of the junction:

$\begin{array}{l}{W}_{d1}=\sqrt{\frac{2\varepsilon V_{d1}}{q{N}_{N^{-}}+\frac{\left|I_c\right|}{A{v}_{sat}}}}\\ W_{d2}=\sqrt{\frac{2\varepsilon V_{d2}}{q{N}_{N^{-}}+\frac{\left|I_c\right|}{A{v}_{sat}}}}\end{array}$

The boundary positions, x₁ and x₂, are calculated by

$\begin{array}{l}{x}_1=W_{d1}\\ x_2=W_{N^{-}}-W_{d2}\end{array}$

The displacement currents, I_disp1 and I_disp2, are due to the changing depletion widths at junctions J₁ and J₂:

$\begin{array}{l}{I}_{\mathit{disp}1}=C_{J1}\frac{d{V}_{d1}}{dt}=\varepsilon A\frac{1}{W_{d1}}\frac{d{V}_{d1}}{dt}\\ I_{\mathit{disp}2}=C_{J2}\frac{d{V}_{d2}}{dt}=\varepsilon A\frac{1}{W_{d2}}\frac{d{V}_{d2}}{dt}\end{array}$

The voltages across junctions J₁ and J₂ are

$\begin{array}{l}{V}_{j1}=2V_T\mathrm{In}\left(\frac{p_1}{n_i}\right)\\ V_{j2}=V_T\mathrm{In}\left(\frac{p_{x2}}{N_C}\right)\end{array}$

The voltage drop across the carrier storage region, $V_{N^{-}}$, is calculated based on the injected carrier concentration discussed in Section 5.3.2.2.

$\begin{array}{l}{V}_{N^{-}}\approx \frac{I_C}{qA\left({\mu }_n+{\mu }_p\right)}\frac{x_2-x_1}{М-1}{\displaystyle \sum _{к=0}^{М-1}\left[\frac{1}{p_{T\left(k\right)}-p_{T\left(k-1\right)}}ln\left(\frac{p_{T\left(k\right)}}{p_{T\left(k-1\right)}}\right)\right]}\\ +V_T\left(\frac{{\mu }_n-{\mu }_p}{{\mu }_n+{\mu }_p}\right)ln\left(\frac{p_{x2}}{p_{x1}}\right)\end{array}$

where the carrier distribution, p_T(k), is calculated as

$p_{T\left(k\right)}=p\left(x_1+\frac{k\left(x_2-x_1\right)}{M-1}\right)+\frac{{\mu }_n{N}_{N^{-}}}{{\mu }_n+{\mu }_p}$

The N⁺ collector region has similar properties to the N⁺ emitter region as it also can be presented as a hole sink. The hole current at junction J₂ is obtained by the equation:

$I_{p2}=qA{h}_n{p}_{x2}^2$

The electron current at junction J₂ is

$I_{n2}=I_c+I_{p2}-I_{\mathit{disp}2}$

During the ON-state, the voltages across the N⁻N⁺ and N⁻P⁺ depletion layers, V_d1 and V_d2, are equal to zero, and the collector-emitter voltage is

$V_{CE}=V_{j0}+V_{j1}+V_{j2}+V_{N^{-}}$

Substituting the junctions' voltages from Eqs. (5.104), (5.120) in Eq. (5.125) and simplifying, the following equation will be obtained:

$V_{CE}=V_{T}ln\left(n_{B0}\left(n_{B0}+P_B\right)p_{x1}^2\frac{p_{x2}}{N_C}\right)+4V_{T}ln\left(\frac{1}{n_i}\right)+V_{N^{-}}$

Since the thickness of the lightly doped drift region of a SiC BJT is smaller than the lightly doped drift region of a Si device, their boundary carrier densities, p_x1 and p_x2, at the boundaries, x₁ and x₂, are bigger [71]. Therefore, for the same doping concentration of the four regions of a power SiC BJT and a power Si BJT, the first term of Eq. (5.126) for a SiC device is big compared with a Si one. Also, if it is assumed that the intrinsic carrier concentrations of Si and SiC are 10¹⁰ and 10⁻¹⁰ cm⁻³ and the thermal voltage, V_T=0.256, the second term of a Si device is a negative number (approximately −2.36 V) that will subtract from the first term and make collector-emitter voltage smaller, while for a SiC BJT, the second term is a positive number (~2.36 V) that will add to the first term and make the collector-emitter voltage bigger. Only the voltage drop in the lightly doped drift region for SiC will be small compared with a Si one, since the thickness in Si is significantly larger and the doping concentration in Si is lower. To have benefits of conductivity modulation and therefore small ON-resistance, SiC BJTs similar to SiC PiN diode should be designed for higher than 4 kV [112]. Also, the BJT is a bipolar device having minority and majority carrier flowing during operation; therefore, the drift region stores charge that decreases the device switching speed and thus can only operate at switching frequencies less than can be obtained with a MOSFET structure.

5.3.6 SiC IGBT

As previously mentioned, the rapid improvement in 4H-SiC material quality and the maturing of SiC device processing in recent years have enabled the development of high-voltage SiC power devices (MOSFETs and JFETs). However, the ON-resistance of SiC MOSFETs and JFETs rapidly increases as the blocking voltage and operating junction temperature increase because they are unipolar devices and conductivity modulation is not happening in the lightly doped drift region. This makes the conduction loss of the unipolar devices unacceptable for applications with a blocking voltage higher than 10 kV. For these applications, bipolar devices are preferred because they have been shown to have a small voltage drop due to strong conductivity modulation in their drift regions [113].

Simple gate drive interfaces make 4H-SiC IGBTs attractive devices. Chronologically, the first fabricated and characterized IGBTs were P-channel because there was a practical limitation in producing the low resistivity P⁺-type SiC substrate required for fabricating N-channel IGBTs [114]. But with the advantages of the SiC technology, N-channel IGBTs have been built. Both N- and P-channel SiC IGBTs have demonstrated high blocking voltage capability, as the first IGBT fabricated in 2006 had a blocking voltage of 5.8 kV. Since then, different IGBTs have been built; for example, 12 kV P-channel IGBTs with 14 mΩ cm² ON-resistance [115], 13 kV N-channel IGBTs with 22 mΩ cm² ON-resistance [116], and 20 kV self-aligned P-channel DMOS-IGBTs have been reported [117]. The 20 kV P-channel IGBT has a less than 15 times a smaller voltage drop at 31 A cm⁻² current density compared with a theoretical MOSFET with the same blocking voltage [117]. The last reported IGBT with ultrahigh blocking voltage of 27 kV was reported in 2015 [118].

Different SiC device research groups have been working on optimizing the IGBT parameters and fabricating and characterizing devices so that soon IGBTs will be on the market. For a given blocking voltage, a trade-off between conduction and switching loses should be made to optimize the IGBT parameters. A reason for this is that there is a huge amount of charge stored in the IGBT lightly doped drift region during the ON-state and that has to be removed during turn-OFF [119].

In [120], the device group from Cree Inc. has fabricated a 10 kV MOSFET and an N-type IGBT capable of flowing 10 and 4 A, respectively. Both devices were processed identically through the device fabrication process each as a MOS part where the lightly doped drift region had the same length and doping concentration. The only difference between the two devices is that the N-channel IGBTs have a moderately doped N field-stop (FS) buffer layer and a heavily doped P⁺ injector, while the MOSFET has an N⁺ substrate. The DC characteristics of the devices were measured, and it was observed that the forward voltage drops of the two structures were the same, ~5 V.

The switching results indicated that both devices were much faster than the highest voltage, commercially available Si IGBT. The MOSFET turn-OFF transient time was faster than the IGBT turn-OFF time of 140 and 400 ns, respectively. A reason for slow turn-OFF time is that the IGBT is a bipolar device and stores minority and majority charges in the lightly doped drift region that are removed slowly, while the MOSFET is a unipolar device and is not dependent on carrier recombination during turn-OFF. The IGBT turn-OFF transient can be improved by reducing gate resistance and optimizing the internal capacitance and increasing the high-level lifetime.

Seven years later, the Cree Inc. group demonstrated a 20.7 kV N-channel IGBT with a forward voltage drop of 6.4 V at a collector current of 20 A and a 17 kV N-channel IGBT with a forward voltage drop of 5.7 V at a collector current of 20 A [121]. The two IGBTs were fabricated with the same mask sets and identical fabrication process. Although the lightly doped drift region for the 20.7 kV IGBT was significantly increased in width to support higher voltage, the voltage drop did not increase significantly, which can be attributed to conductivity modulation that takes place during the conduction state of the IGBT. Similar to a SiC PiN diode and a BJT, as an IGBT is a bipolar device, the junction voltage drops are dominant in determining the forward voltage drop with a blocking voltage smaller than 20 kV. The ON-resistance for an IGBT will be dominated by the parasitic resistance, such as channel resistance and the contact resistance, while the resistance of the lightly doped drift region will not be much larger due to high-level injection in the lightly doped drift region leading to conductivity modulation.

Results of a comparison of N-channel and P-channel SiC IGBTs have shown comparable static characteristics that can be explained by the fact that during the ON-state, an IGBT is operating at high-level injection. Regardless of the structure of an IGBT, the behavior of the carriers in the lightly doped drift region is governed by the ADE:

$D\frac{{\partial }^{2}p\left(x,t\right)}{\partial x^2}=\frac{p\left(x,t\right)}{\tau }+\frac{\partial p\left(x,t\right)}{\partial t}$

Operating at high-level injection means that the injected carriers in the lightly doped drift region have significantly higher values than the background impurity doping concentration. The electron and hole concentrations in the drift region during the ON-state are equal:

$p\left(x,t\right)=n\left(x,t\right)$

Their concentrations depend on the boundary conditions at each end of the drift region, the minority charge-carrier lifetime, and the drift region width. Assuming that N-channel and P-channel IGBTs are processed identically through the device fabrication process and the gate-source voltage and collector current are the same, then the carrier concentration in the drift region of the two devices will be equal, and therefore, the voltage drop across the drift regions will be the same. The IGBT junction voltages are functions of the doping concentrations, and they will be the same for the identically processed N- and P-channel IGBTs. Therefore, the total voltage drop for identically processed N-channel and P-channel SiC IGBTs will be significantly the same when the devices are subjected to the same conditions: gate-source voltage, collector current, and temperature.

On the other hand, N-channel IGBTs offer far superior switching characteristics over P-channel IGBTs. In Ref. [122], the simulation results of the switching characteristics of N-channel and P-channel 15 kV SiC IGBTs are given that support this fact. The rate of increase in the collector-emitter voltage of an N-channel IGBT is 40 V ns⁻¹ and for a P-channel IGBT is 5 V ns⁻¹. The current decay for the N-channel IGBT is also faster than the current decay for the P-channel IGBT. A physical explanation for this is that in the beginning of the turn-OFF process, the collector-emitter voltage, V_CE, rises from the forward voltage, V_F, to the DC supply voltage, V_DC, and the rate of change of the V_CE depends on the rate of removal of the stored charge through the emitter side. During this time, the recombination and displacement currents are significantly smaller than the minority carrier current and can be neglected. The minority current is responsible for the charge removal. As the V_CE rises, the depletion region expands toward the collector junction. The minority carriers are swept out through the depletion region, and the majority of carriers are pushed toward the collector where most of them will recombine in the P⁺ injector layer for an N-channel IGBT or N⁺ injector layer for a P-channel IGBT [119]. Due to the large rate of change in the minority carrier current, the depletion region expends faster in an N-channel IGBT than in a P-channel IGBT, and therefore, the collector voltage for N-channel an IGBT rises at a faster rate. During the second phase of the turn-OFF process, after the collector-emitter voltage, V_CE, reaches the DC supply voltage, V_DC, the freewheeling diode is turned ON that allows the collector current to fall down to a value depending on the remaining storage charge. During this time, the V_CE overshoots due to the energy stored in the stray inductance in the collector-emitter loop. After that, the collector current depends only on the remaining storage charge, and the recombination rate depends on the high-level carrier lifetime [123]. Since the holes' lifetime is smaller than the electrons' lifetime, the tailing current phase is shorter for an N-channel IGBT compared with a P-channel IGBT. Also, an N-channel IGBT has faster charge extraction due to the large ionization energy of acceptors in 4H-SiC [122]. Since the total losses for an N-channel IGBT are smaller compared with a P-channel IGBT, further developments in IGBT should be focused on an N-channel IGBT [118].

Similar to other power devices, IGBTs consist a thick lightly doped drift region that is required to support high voltage and prevent an avalanche breakdown. The drift region thickness, the doping concentration, and the minority carrier lifetime are important IGBT design parameters. Their values are optimized so that the sum of the conduction and switching losses is minimized for a desired blocking voltage. The drift region thickness and doping concentration are optimized to obtain minimum conduction loses (forward voltage drop) for the same blocking voltage. Increasing the doping concentration requires a thicker drift region to sustain the high voltage and prevent an avalanche breakdown. The minority lifetime effects the conducting and switching losses. An increase in the lifetime enhances the conductivity modulation, and therefore, the forward voltage drop is reduced, while the recombination process becomes slower and results in high switching losses. A compromise between conduction and switching losses should be made to optimize the carrier lifetime in the drift region.

To decrease the drift region thickness for the same IGBT blocking voltage, an FS layer adjacent to the lightly doped drift region is used, making the IGBT an asymmetrical device. In [124], it is shown that a 15 kV N-channel symmetrical IGBT does not have an FS layer and the thickness of the drift region is 247 μm, while for an asymmetrical N-channel IGBT, the thickness is 150 μm. Therefore, the voltage drop in the lightly doped drift region is significantly smaller for an asymmetrical device. Also, due to the FS layer, the depletion width starts to expand across the whole drift region when an IGBT is switched OFF and a punch-through effect is observed. Therefore, the depletion width that is equal to the drift region thickness should be designed first. The punch-through effect benefits the switching characteristics of an IGBT. After the punch-through, the sweep-out of the excess carriers practically stops, and the charge removal is performed mostly due to the recombination process in the FS layer. Therefore, the current tail disappears under the punch-through condition. The punch-through effect has some disadvantages also. During punch-through, the parasitic capacitance associated with increasing of the V_CE turns into a much smaller capacitance instead of a large diffusion capacitance [121]. This capacitance resonates with the parasitic stray inductance in the collector-emitter loop resulting in voltage overshooting and a ringing phenomenon, which should be carefully considered. The thickness of the FS layer is an important device parameter. Increasing the FS layer thickness results in superior turn-OFF speed but slightly increases the forward voltage drop, while decreasing the FS layer thickness slows down the turn-OFF speed but offers superior conduction capability [125].

To reduce the ON-state resistance of the lightly doped drift region of an N-channel IGBT, some power device designers have inserted a thin, heavily doped N⁺ current spreading layer (CSL) beneath the P-type base region, forming a JFET layer between the two P bases. An CSL helps to distribute the electron flow more uniformly, minimizing the current crowding at the top of the drift region and reducing the drift layer resistance. Both regions, CSL and JFET, are formed as N-type epitaxial layers having higher doping concentration than the drift layer. Increasing the doping concentration in the JFET region helps to reduce the ON-state resistance; however, it causes an increase in the electric field at the SiC-SiO₂ interface during the blocking state. Simulation results have shown that for a drift region width higher than 1.6 μm, the oxide field reaches 4 MV cm⁻¹ prior to the avalanche breakdown in SiC. Decreasing the JFET width increases the resistance since it pinches off the current path but reduces the cell area; consequently, the effect of the specific ON-resistance is negligible [77]. An optimum width of the JFET region can be determined. When an IGBT has an optimum width, its blocking voltage is limited by the avalanche breakdown for the entire range of the lightly doped drift region. In [126], it is shown that for their design, the optimum width is 1 μm.

To optimize the parameters of a PT IGBT, a physics-based model, given in [127], can be used. For this purpose, the device is divided into five regions, as shown in Fig. 5.14: P emitter (collector terminal), N⁺ field-stop layer, N⁻ drift region, P well, and N⁺ emitter. Fig. 5.14 also shows the external currents (emitter and collector currents I_E and I_C), the internal electron and hole currents (at junctions J₀ I_n0 and I_p0, J₁ $I_{n_1}$ and $I_{p_1}$, and J₂ $I_{n_2}$ and $I_{p_2}$), and the capacitive currents from the displacement layers ($I_{\mathit{dis}{p}_2}$ and I_CG). The IGBT is a gate-controlled device and is used as a controllable switch in power electronic applications. Given its P-N-P-N structure, the IGBT is a voltage bidirectional switch, that is, it can conduct current in one direction only, but it can block the voltage of both polarities. The reverse-blocking capability is rarely used in conventional power converter configurations. Frequently, an antiparallel diode is added as a separate chip to accommodate converter configurations, such as the voltage source inverter, which require a current bidirectional switch. In the normal forward blocking operation of the IGBT, a depletion layer is formed at the MOS end of the drift region (at the N⁻ drift region/P-well junction), while in a reverse-blocking operation, it is formed at the P emitter/drift region junction. In forward blocking, a depletion layer is never formed at the P emitter. For this reason, no displacement current for junction J₀ is included. The model can be easily extended to reverse-blocking IGBTs by allowing a depletion layer at the junction J₀.

The hole and electron currents in the P-emitter layer end of a power IGBT at junctions, J₀, I_p0, and I_n0, depend on the process happening in the FS layer. The sum of them is equal to the IGBT collector current:

$I_C=I_{p0}+I_{n0}$

where N_N is the doping concentration of the FS layer.

Adding an FS layer allows a reduction in the drift region thickness for the same blocking voltage and also speeds up the IGBT turn-off process but creates two junctions, J₀ and J₁. Due to electron reverse injection into the P⁺ emitter, there is a small electron current I_n0 at junction J₀. These electrons travel through the buffer layer from the drift region. The hole current, I_p0, injected from the P⁺ emitter, travels mostly by diffusion through the FS layer. Since the layer is typically quite thin in comparison with the hole diffusion length, $L_{p_N}$, there is little recombination, and most of the holes reach the drift region. This hole current is I_p1 and represents the hole injection from the buffer layer into the drift region.

The difference between the two hole currents at junctions J₁ and J₀ is due to the recombination, and it is compensated for by an increase in the electron current, so that the electron current I_n1 at junction J₁ can be presented by a sum of the recombination component plus the reverse injection electron current I_n0. Static conditions are assumed up to now, while under dynamic conditions, an additional hole current component due to variations in the stored charge in the buffer layer should be considered.

Assuming a quasistatic state, the continuity equation of the holes in the buffer layer is then expressed by

$D_{pN}\frac{d^{2}p\left(x\right)}{d{t}^2}=\frac{p\left(x\right)}{{\tau }_{pN}}$

where τ_pN is the minority lifetime and D_pN is the hole diffusivity in the field-stop layer. The solution for the excess hole concentration in the buffer layer is given by

$p\left(x\right)=\frac{\left[p_{N0}sinh\left(\frac{W_N-x}{L_{pN}}\right)+p_{NW}sinh\left(\frac{x}{L_{pN}}\right)\right]}{sinh\left(\frac{W_N}{L_{pN}}\right)}$

where W_N is the width of the buffer layer, p_N0 and p_NW are the hole concentrations at the two edges of the field-stop layer (junctions J₀ and J₁), and L_pN is the hole diffusion length.

Under the low-level injection, the minority hole current is mostly diffusion current, so it is expressed as

$I_p=qA{D}_{pN}\frac{dp}{dx}$

Thus, the hole current at the junction J₀ is obtained substituting the derivative of Eq. (5.131) for $x=0$ into Eq. (5.132):

$\begin{array}{l}{I}_{p0}=qA{D}_{pN}{\left.\frac{dp}{dx}\right|}_{x=0}\\ =\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}\left[p_{N0}cosh\left(\frac{W_N}{L_{pN}}\right)-p_{NW}\right]\end{array}$

Assuming quasiequilibrium, the reverse injection current I_n0 at junction J₀ is given by

$I_{n0}=\frac{A{I}_{sne}{N}_N{p}_{N0}}{n_i^2}$

where I_sne is the emitter electron saturation current.

The current continuity at the boundaries of the buffer layer requires that

$I_C=I_{n0}+I_{p0}=I_{n1}+I_{p1}+I_{\mathit{dis}1}$

Then, the hole concentration at the junction J₁ is obtained by substituting Eqs. (5.133), (5.134) into Eq. (5.135) and then reorganizing the equation to the form:

$p_{N0}={\left[\frac{A{I}_{sne}{N}_N}{n_i^2}+\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}\right]}^{-1}\left[I_C+\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}{p}_{NW}\right]$

The hole current I_p1 at junction J₁ is obtained similar to I_p0, only $x=W_N$:

$\begin{array}{l}{I}_{p1}=qA{D}_{pN}{\left.\frac{dp}{dx}\right|}_{x=W_N}\\ =\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}\left[p_{N0}-p_{NW}cosh\left(\frac{W_N}{L_{pN}}\right)\right]+I_{QN}\end{array}$

The current, I_QN, represents the capacitive current due to the variation in the charge Q_N stored in the buffer region:

$I_{QN}=-\frac{d{Q}_N}{dt}$

The charge Q_N can be approximated as

$Q_N=qA{W}_N\frac{p_{N0}+p_{NW}}{2}$

The hole concentration, p_NW, at the boundary between the buffer layer and the drift region is obtained by applying the Boltzmann relationship for the junction J₂ under the assumption of high-level injection in the drift region ($p_{N^{-}0}>>N_{N^{-}}$):

$p_{NW}=\frac{p_{N^{-}0}\left(p_{N^{-}0}+N_{N^{-}}\right)}{N_N}=\frac{p_{N^{-}0}^2}{N_N}$

where $p_{N^{-}0}$ is the hole concentration in the beginning and $N_{N^{-}}$ is the doping concentration of the N⁻ drift region.

The voltages across the junctions J₀ and J₁ are

$V_{J0}=V_{T}ln\left(\frac{p_{N0}{N}_N}{n_i^2}\right)$

$V_{J1}=V_{T}ln\left(\frac{N_{N^{-}}}{p_{N^{-}0}}\right)$

The voltage drop in the N⁻ drift region is calculated during the ON-state. The charge distribution and the boundary current components in the N⁻ region are shown in Fig. 5.15. The injected excess carrier concentration is determined by the ADE. As for all bipolar power switches, high-level injection and quasineutral conditions exist. Under high-level injection conditions, the ADE (Eq. 5.35) describes the carrier dynamics.

It was mentioned that, during forward blocking of an IGBT, no depletion layer forms at junction J₁; therefore, its thickness, x₁, can be approximated as zero. Therefore, the charge storage region, which operates under high-level injection and is described by the ADE, Eq. (5.35), has $x_1\text{≡}0$ and $\frac{d{x}_1}{dt}\text{≡}0$. The Fourier series solution of the ADE, given by Eq. (5.39), can be simplified to

For $k>0$

$\begin{array}{l}{D}_{N^{-}}\left[{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x2}{\left(-1\right)}^k-{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x1}\right]\\ =\frac{x_2}{2}\left(\frac{d{p}_k\left(t\right)}{dt}+\left[\frac{1}{\tau }+\frac{D_{N^{-}}{k}^2{\pi }^2}{x_{{}_2}^2}\right]p_k\left(t\right)\right)+\\ -\left({\displaystyle \sum _{\begin{array}{l}n=1\\ n\ne k\end{array}}^{\infty }\frac{n^2}{n^2-k^2}}\left[{\left(-1\right)}^{n+k}\frac{d{x}_2}{dt}\right]p_n\left(t\right)+\frac{p_k\left(t\right)}{4}\left(\frac{d{x}_2}{dt}\right)\right)\end{array}$

For $k=0$

$D\left[{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x_2}-{\left.\frac{\partial p\left(x,t\right)}{\partial x}\right|}_{x1}\right]=x_2\left(\frac{d{p}_0\left(t\right)}{dt}+\frac{p_0\left(t\right)}{\tau }\right)-{\displaystyle \sum _{n=1}^{\infty }\left[{\left(-1\right)}^n\frac{d{x}_2}{dt}\right]}{p}_n\left(t\right)$

The solution to the ADE is determined by using the boundary conditions at the edges of the charge storage region:

${\left.\frac{\partial p}{\partial x}\right|}_{x_1}={\left.\frac{1}{2q}\left(\frac{J_n}{D_n}-\frac{J_p}{D_p}\right)\right|}_{x_1}\mathrm{and}{\left.\frac{\partial p}{\partial x}\right|}_{x_2}={\left.\frac{1}{2q}\left(\frac{J_n}{D_n}-\frac{J_p}{D_p}\right)\right|}_{x_2}$

The current continuity equation at junction J₂ is determined by

$I_C=I_{n_2}+I_{p_2}+I_{\mathit{dis}{p}_2}+I_{CG}$

The electron current at junction J₂ is the MOS channel current:

$I_{n_2}=I_{mos}$

Substituting Eqs. (5.146) in (5.145) and then in Eq. (5.143), the left side of the solution of the ADE (Eq. 5.143), for even and odd numbers of k, can be calculated by the following equations:

$\begin{array}{l}{I}_{\mathit{odd}}=-D\left({\left.\frac{\partial p}{\partial x}\right|}_{x_2}+{\left.\frac{\partial p}{\partial x}\right|}_{x_1}\right)=\left|\begin{array}{l}{I}_{n_1}\\ I_{mos}\\ I_C\\ I_{\mathit{dis}{p}_2}\\ I_{CG}\end{array}\right|\frac{1}{2qA}\left|2-2\frac{2D}{D_p}-\frac{D}{D_p}-\frac{D}{D_p}\right|\\ I_{\mathit{even}}=D\left({\left.\frac{\partial p}{\partial x}\right|}_{x_2}-{\left.\frac{\partial p}{\partial x}\right|}_{x_1}\right)=\frac{1}{2qA}\left|\begin{array}{l}{I}_{n1}\\ I_{mos}\\ I_C\\ I_{\mathit{disp}2}\\ I_{CG}\end{array}\right|\left|-2+20+\frac{D}{D_p}+\frac{D}{D_p}\right|\end{array}$

The boundary carrier densities p_x1 and p_x2 at the boundaries x₁ and x₂ are calculated using the equations:

$p_{x_1}={\displaystyle \sum _{k=0}^{M-1}{p}_k}\mathrm{and}{p}_{x_2}={\displaystyle \sum _{k=0}^{M-1}{\left(-1\right)}^k{p}_k}$

The voltage across the N⁻P depletion layer, $V_{d_2}$, is calculated by the following equation:

$V_{d_2}=\left\{\begin{array}{cc}\hfill 0\hfill & \hfill \mathrm{if}{p}_{x_1}>0,\hfill \\ \hfill -K_{FV}{p}_{x_2}\hfill & \hfill \mathrm{otherwise}\text{.}\hfill \end{array}\right.$

The associated depletion width, $W_{d_2}$, is calculated using a step doping concentration change on each side of the junction:

$W_{d_2}=\sqrt{\frac{2\varepsilon V_{d_2}}{q{N}_{N^{-}}+\frac{\left|I_C\right|}{A{v}_{sat}}}}$

The boundary position x₂ is calculated by

$x_2=W_{N^{-}}-W_{d_2}$

The displacement current at x₂ is composed of two components: $I_{\mathit{dis}{p}_2}$ flowing into the P well and I_CG associated with Miller capacitance and accumulation layer charge. The P-well displacement current is given by

$I_{\mathit{dis}{p}_2}=C_{J_2}\frac{d{V}_{d2}}{dt}=\varepsilon A\frac{1}{W_{d_2}}\frac{d{V}_{d_2}}{dt}$

To calculate the Miller capacitance, it is assumed that the depletion layer extends under the gate from P well and only extends downward through the drift region once the accumulation layer has been removed from the gate in the center of the intercell region. Therefore, the width of the Miller capacitance, W, is

$W=W_{d2}-l_m-l_1$

where l_m is an intercell half width and l₁ is a width due to voltage V_GE:

$l_1=\sqrt{\frac{2\varepsilon V_{GE}}{q{N}_{N^{-}}}}$

The Miller capacitance is given by the series combination of the oxide capacitance C_oxAa_i and the depletion capacitance $\frac{\varepsilon A{a}_i}{W}$:

$C_{CG}=\frac{C_{\mathit{ox}}A{a}_i}{1+\frac{C_{\mathit{ox}}}{\varepsilon }W}$

where a_i is the ratio of intercell area to the total die area.

Due to Miller capacitance, the current I_CG is

$I_{CG}=C_{CG}\left(\frac{d{V}_{d2}}{dt}-\frac{d{V}_{GE}}{dt}\right)$

where

$\frac{d{V}_{GE}}{dt}=\frac{1}{C_{GE}+C_{GC}}\left(I_G+C_{CG}\frac{d{V}_{d2}}{dt}\right)$

The voltage drop in the carrier storage region $V_{N^{-}}$ is calculated based on the injected carrier concentration:

$\begin{array}{l}{V}_{N^{-}}\approx \frac{I_C}{qA\left({\mu }_n+{\mu }_p\right)}\frac{x_2-x_1}{М-1}{\displaystyle \sum _{к=0}^{М-1}\left[\frac{1}{p_{T\left(k\right)}-p_{T\left(k-1\right)}}ln\left(\frac{p_{T\left(k\right)}}{p_{T\left(k-1\right)}}\right)\right]}\\ +V_T\left(\frac{{\mu }_n-{\mu }_p}{{\mu }_n+{\mu }_p}\right)ln\left(\frac{p_{x2}}{p_{x1}}\right)\end{array}$

where the carrier distribution p_T(k) is calculated as

$p_{T\left(k\right)}=p\left(x_1+\frac{k\left(x_2-x_1\right)}{M-1}\right)+\frac{{\mu }_n{N}_{N^{-}}}{{\mu }_n+{\mu }_p}$

IGBTs are used as switches, operating mainly in two stages: ON and OFF. The MOS region can be modeled as a simple MOSFET. During the ON-state, the MOSFET operates either in the triode region or in the saturation region, while during the OFF-state, it operates in cut-OFF. Therefore, during the OFF-state, the gate-source voltage is smaller than the threshold voltage $\left(V_{GS}<V_{TH}\right)$, and current I_mos is zero. During the ON-state, the gate-source voltage is larger than the threshold voltage $\left(V_{GS}>V_{TH}\right)$, and current I_mos is calculated by

$I_{mos}=\left\{\begin{array}{cc}\hfill \frac{K_p}{2}\left[2V_{DS}\left(V_{GS}-V_{TH}\right)-V_{DS}^2\right]\hfill & \hfill \mathrm{if}{V}_{DS}\le V_{GS}-V_{TH}\hfill \\ \hfill \frac{K_p}{2}{\left(V_{GS}-V_{TH}\right)}^2\hfill & \hfill \mathrm{otherwise}\hfill \end{array}\right.$

The voltage drop V_CE across PT IGBT is composed of three components: voltages across the junction J₁, voltage across the two depletion regions V_d2, and voltage across the carrier storage region $V_{N^{-}}$.

$V_{CE}=V_{j_1}+V_{d_2}+V_{N^{-}}$

5.3.7 SiC Thyristor

As the trend of power electronics industry is moving toward high voltage, high current, and high frequency, the conduction and switching losses of the power semiconductor devices should be at an acceptable level. Up to now, SCRs are still the most powerful devices currently available in pulse power applications. A single SCR can block 8 kV and conduct 4 kA, and a GTO can block 6 kV and conduct 6 kA [128]. However, due to the high switching losses of SCRs and GTOs, their maximum operation frequency is limited to 1 kHz. Because of their switching and driving characteristics, the device paralleling for high-power applications is impossible. SCRs and Si GTOs have a positive temperature coefficient and their operating temperature is limited to 100°C junction temperature, since the leakage current increases significantly above that temperature. Typically, this requires expensive active liquid cooling to maintain safe operation conditions. The leakage current of a SiC GTO is extremely small at 300°C and only requires forced air cooling.

SiC GTOs and IGBTs are two devices that can soon be utilized in utility-based power handling equipment, such as flexible AC transmission systems (FACTS) and high-voltage DC transmissions (HVDCT). A 4H-SiC thyristor is a better candidate because it is capable of higher current densities than a SiC IGBT, since the physical mechanism for conductivity modulation is more effective in the thyristor than the IGBT. Also, SiC IGBTs are limited to 150°C junction temperature due to a limitation of the gate oxide reliability.

In the near future, large-area SiC GTOs will be utilized in FACTS and HVDCT due to three main advantages: a smaller number of devices connected in series since they have higher blocking capability (20–30 kV with the present technology), low current leakage, and reduced cooling requirements due to the ability of SiC GTOs to operate at higher junction temperatures (300°C if the packaging issues are solved). However, the thyristor requires more complex external circuitry as it is a current-controlled device.

The first SiC symmetrical thyristors (700 V with a rated current of 6 A and a forward drop of 3.9 V) were demonstrated by Cree, Inc. [129]. Since then, scientists from Cree and other institutions have designed and fabricated different asymmetrical NPNP devices. The limitations of the epilayer thickness and device footprint have been the main obstacles for increasing the blocking voltage and the current capability of the devices, but different scientific groups have worked in the last two decades to improve design, fabrication, and characterization of different power semiconductor devices that were used for an evaluation of SiC GTOs from 1.77 kV blocking voltage with 4 V voltage drop at 100 A and 200°C [130] demonstrated in 2005 to a 22 kV blocking voltage with approximately 6.5 V voltage drop at 100 A and 150°C reported 10 years later. The most important developments of this evaluation were increasing the wafer diameter to 5.9′′ (150 mm) [131]; the electrically active defects, such as dislocations, point defects, and silicon inclusion, have been drastically reduced; the problem of the foreword voltage drop, V_F, drift due to high density of the basal plane dislocation has been solved by improving the epitaxial growth; and improving the life time of the minority carrier concentration in the lightly doped drift region.

Due to very high blocking voltage (>20 kV) for SiC GTOs, they have a low-doped thick drift region that has high resistivity. In order to obtain significantly low ON-state losses, the ambipolar diffusion length of the minority carriers in the drift region should be significantly large, that is, the minority carrier lifetime must be made as long as possible. For an N-type SiC epilayer, a significant improvement of carrier lifetime has been achieved from 0.69 to 9.5 μs by reducing the Z_1/2 center via two-step thermal treatment (thermal oxidation and Ar annealing) for a 148 μm N-type epilayer [132]. However, there is some difficulty for enhancement of the carrier lifetimes in p-type epilayers [133]. In [134], the lifetime in P-type SiC epilayer was improved from 1 to 4 μs by oxidation at 1300°C for 5 h prior to the metal contact processing; however, the carrier lifetime was not uniform across the chip area. The lifetime uniformity can be enhanced by controlling the point defects in SiC by low-energy electron irradiation [132].

Currently, the thyristors are made on N⁺ 4H-SiC substrates, because P⁺ substrates have higher resistance than the N⁺ substrates. Recently, a significant improvement in N⁺ 4H-SiC substrate quality has been reported. An IGBT with an ultrahigh blocking voltage of 27 kV was built on N⁺ 4H-SiC substrate [118]. For a Si power thyristor to minimize power losses, the epilayer is N⁻ type. Therefore, in the future, power thyristors will build on P⁺ substrate with an N⁻ epilayer.

To optimize the parameters of the transistor, a physics-based model for GTOs employing a Fourier-based solution for the ambipolar diffusion equation of the N⁻ lightly doped drift region and a lumped-charge method for the P-base region can be used. A new level-3 physics-based model for GTOs employs a Fourier-based solution for the ambipolar diffusion equation of the lightly doped N⁻ drift region, and a lumped-charge method for the P-base region is provided below. In addition to the external electric characteristics, the model can also provide internal physical and electric information, such as junction voltages, and the charge distribution in the buffer layer and the base regions. Fig. 5.16 shows the schematic structure of a SiC high-power thyristor with the direction of the flowing currents.

A major difficulty in analyzing and modeling the performance of bipolar power devices is due to the different carrier density distribution in the different regions. The behavior of the GTO is modeled by dividing the device into different regions.

The P⁺ and N⁺ emitter regions have high doping concentration, and therefore, there is a significant electron concentration adjacent to the P⁺N junction and a significant hole concentration adjacent to the PN⁺ junction due to the equal concentrations of holes and electrons. As a result of these high concentrations, minority carriers flow into the highly doped P⁺ and N⁺ emitter regions, where they recombine with holes and electrons, respectively. The process is known as emitter recombination. The resulting electron and hole currents due to the recombination are

$I_{n0}=qA{h}_p{p}_{N0}^2$

$I_{p3}=qA{h}_n{n}_{PW}^2$

where p_N0 and n_PW are the hole and the electron concentrations at junctions J₀ and J₃, respectively. The recombination parameters, h_p and h_n, calculated by Eqs. (5.32), (5.63), depend on the emitter properties, such as doping level ($N_{P^{+}}$ and $N_{N^{+}}$), electron and hole diffusivities (D_n and D_p), and electron and hole lifetime (τ_n and τ_p). The hole and emitter currents in the P⁺ and N⁺ emitter regions are

$I_{p0}=I_A-I_{n0}$

$I_{n3}=I_A-I_{p3}$

Adding a buffer layer allows a reduction of the drift region thickness for the same blocking voltage and speeds up the thyristor turn-off process, but it creates two junctions, J₁ and J₂. Due to electron reverse injection into the P⁺ emitter, there is a small electron current, I_n0, at junction J₀. These electrons travel through the buffer layer coming from the drift region. The hole current, I_p0, injected from the P⁺ emitter travels mostly by diffusion through the buffer layer. Since the buffer layer is typically quite thin in comparison with the diffusion length in the buffer layer, $L_{p_N}$, there is little recombination in the buffer layer, and most of the hole current reaches the drift region. This current, I_p1, presents the hole injection from the buffer layer into the drift region.

The difference between the two hole currents at the junction J₁ and J₀ is due to the recombination, and it is compensated by an increase in the electron current, so that the electron current I_n1 at junction J₁ can be presented by a sum of the recombination component plus the reverse injection electron current I_n0. Static conditions are assumed up to now, while under the dynamic condition an additional hole current component due to variations in the stored charge in the buffer layer should be consider.

Assuming a quasistatic state, the continuity equation of the holes in the buffer layer is then expressed by

$D_{pN}\frac{d^{2}p\left(x\right)}{d{t}^2}=\frac{p\left(x\right)}{{\tau }_{pN}}$

where τ_pN is the minority lifetime and D_pN is the hole diffusivity in the buffer layer. The solution for the excess hole concentration in the buffer layer is given by

$p\left(x\right)=\frac{\left[p_{N0}sinh\left(\frac{W_N-x}{L_{pN}}\right)+p_{NW}sinh\left(\frac{x}{L_{pN}}\right)\right]}{sinh\left(\frac{W_N}{L_{pN}}\right)}$

where W_N is the width of the buffer layer, p_N0 and p_NW are the hole concentrations at the two edges of the buffer layer (junctions J₀ and J₁), and L_pN is the diffusion length of the holes.

Under the low-level injection, the minority hole current is mostly diffusion current, so it is expressed as

$I_p=qA{D}_{pN}\frac{dp}{dx}$

Thus, the hole current at the junction J₀ is obtained by substituting the derivative of Eq. (5.167) for $x=0$ into Eq. (5.168):

$I_{p1}=qA{D}_{pN}{\left.\frac{dp}{dx}\right|}_{x=0}=\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}\left[p_{N0}cosh\left(\frac{W_N}{L_{pN}}\right)-p_{NW}\right]$

Assuming quasiequilibrium, the reverse injection current I_n0, at junction J₀ is given by

$I_{n1}=\frac{I_{sne}{N}_N{p}_{N0}}{n_i^2}$

where I_sne is the emitter electron saturation current, which is usually small, and N_N is the doping concentration of the buffer layer.

The current continuity at the boundaries of the buffer layer requires that

$I_A=I_{n0}+I_{p0}=I_{n1}+I_{p1}+I_{\mathit{dis}1}$

Then, the hole concentration at the junction J₁ is obtained by substituting Eqs. (5.169), (5.170) into Eq. (5.171) and then reorganizing to the form:

$p_{N0}={\left[\frac{A{I}_{sne}{N}_N}{n_i^2}+\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}\right]}^{-1}\left[I_A+\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}{p}_{NW}\right]$

The hole current, I_p1, at junction J₁ is obtained similar to I_p0, only $x=W_N$:

$\begin{array}{l}{I}_{p1}=qA{D}_{pN}{\left.\frac{dp}{dx}\right|}_{x=W_N}\\ =\frac{qA{D}_{pN}}{L_{pN}sinh\left(\frac{W_N}{L_{pN}}\right)}\left[p_{N0}-p_{NW}cosh\left(\frac{W_N}{L_{pN}}\right)\right]+I_{QN}\end{array}$

The current, I_QN, represents the capacitive current due to the variation in the charge, Q_N, stored in the buffer region.

$I_{QN}=-\frac{d{Q}_N}{dt}$

The charge, Q_N, can be approximated as

$Q_N=qA{W}_N\frac{p_{N0}+p_{NW}}{2}$

The hole concentration, p_NW, at the boundary between the buffer layer and the drift region, is obtained by applying the Boltzmann relationship for the junction J₁ under the assumption of high-level injection in the drift region $\left(p_{N^{-}0}>>N_{N^{-}}\right)$:

$p_{NW}=\frac{p_{N^{-}0}\left(p_{N^{-}0}+N_{N^{-}}\right)}{N_N}=\frac{p_{N^{-}0}^2}{N_N}$

where $p_{N^{-}0}$ is the hole concentration in the beginning and $N_{N^{-}}$ is the doping concentration of the N⁻ drift region that is denoted below as p_x1.

The voltages across the junctions, J₀ and J₁, are

$V_{J1}=V_{T}ln\left(\frac{p_{N0}{N}_N}{n_i^2}\right)$

$V_{J2}=V_{T}ln\left(\frac{N_{N^{-}}}{p_{N^{-}0}}\right)$

The GTO thyristor requires a thick drift region to support a high blocking voltage. A simple charge control modeling approach cannot be applied for the drift region because the transient duration compares with or is shorter than the transient time of the charge carriers. In this case, the charge dynamics in the drift region can be described by the continuity and the transport equations. The charge profile in the thick drift region can be assumed as one-dimensional over more than 90% of the volume, which makes the analysis simple. Also, high-level injection conditions can be assumed during the time of the transient and static state. Under this assumption and quasineutrality, the one-dimensional ambipolar diffusion equation that describes the carrier dynamics in the majority of this region is given by Eq. (5.35). The equations from Section 5.3.2.2 for SiC PiN diodes in Eqs. (5.35)–(5.61) are the same for a power GTO, so it will not be repeated.

The junction voltage V_J2 between the lightly doped drift region N⁻ and the P base is

$V_{J2}=2V_{T}ln\left(\frac{p_{x2}}{n_i}\right)$

The lumped-charge method can be used to model the charge behavior in the base region due to high doping level and comparatively narrow base width. Using the continuity equation for the base region, the injected minority carrier charge can be described by the relation below:

$\frac{d{Q}_P}{dt}+\frac{Q_P}{{\tau }_{PHL}}=I_{n3}-I_{n2}=I_{p2}+I_G+I_{\mathit{disp}2}-I_{p3}$

where τ_PHL is the high-level lifetime in the P-base region. The electron concentration at the P-base region boundary, n_P0, is related to p_x2 by the doping concentration of the base, N_P, by the equation:

$n_{P0}=\frac{p_{x2}^2}{N_P}$

The total electron charge in the base can be expressed as

$Q_P=\frac{n_{P0}+n_{PW}}{2}qA{W}_P$

where n_PW is the electron concentration at the base region boundary from the N⁺ emitter side and W_P is the base width. Since the diffusion length in the P-base region is much greater than the base width, the gradient of the electron concentration may be approximated linearly. Then, the electron current at junction, J₃, is

$I_{n3}=q{D}_{n}A\frac{n_{PW}-n_{P0}}{W_P}$

The junction voltage V_J3 between the P-base and the N⁺ emitter can be calculated by the equation:

$V_{J2}=V_T\mathrm{In}\left(\frac{n_{PW}\left(n_{PW}+N_P\right)}{n_i^2}\right)$

The voltage drop V_AK across the SiC thyristor is composed of seven components including voltages across junctions J₀, J₁, J₂, and J₃, the voltage across the two depletion regions, V_d1 and V_d2, and the voltage across the drift region, $V_{N^{-}}$:

$V_{AK}=V_{J0}+V_{J1}+V_{J2}+V_{J3}+V_{d1}+V_{d2}+V_{N^{-}}$

5.4.1 Lateral GaN Schottky Barrier Diodes

To achieve a high-efficiency, high-density power conversion system, the high-voltage diodes used in a system should have low turn-ON voltage, V_T, low ON-resistance, R_ON, low leakage current, and short reverse recovery time. Due to the wide bandgap of GaN and high electron mobility in the 2DEG, AlGaN-/GaN-based lateral Schottky barrier diodes (SBDs) on a Si, sapphire, or SiC substrate have demonstrated superior performance over rectifiers made in other material systems, such as gallium arsenide (GaAs)-based devices. The advantages of lateral GaN-based devices are that they have a very low ON-resistance because of the extremely high electron concentrations in the 2DEG, up to 10–20 times higher that GaAs-based devices. Lateral SBDs have a small junction capacitance compared with conventional Schottky diodes and, therefore, low reverse recovery times. Also, a lateral design approach enables the standard GaN HEMT process flow to be used for integrating a Schottky diode with a high-voltage transistor [135].

A cross section of a typical lateral AlGaN/GaN heterostructure Schottky diode is shown in Fig. 5.17. The epitaxial layers are grown by metal-organic chemical vapor deposition on a substrate, and then, two types of contacts, ohmic and Schottky, are formed.

The quality of the epitaxial GaN depends on the quality of the substrate. Si, sapphire, SiC, and GaN can be used for the substrate. Si substrates have good quality, are significantly large in size, and are inexpensive. They can be used for GaN devices for low-power-density applications, where the losses are not high and the device temperature does not exceed the maximum operating junction temperature. Using a Si substrate for GaN devices introduces a number of critical issues due to the lattice mismatch and the difference in the thermal expansion coefficients, which affects the quality and device reliability [34]. Sapphire substrates are cost-effective and widely used for electronic devices with high power density and high-pulsed-output power densities, but it has a high lattice mismatch to GaN and poor thermal conductivity. Therefore, it is difficult to remove heat produced during operation. For high-power-density applications, the GaN devices should be grown on a SiC substrate since the SiC thermal conductivity is three times higher than Si, which leads to improved heat dissipation. The qualities of SiC substrates have improved significantly in the last few years, but they are still not widely available at low cost. GaN substrates have only recently been developed and used for power devices, although they are most important for optical applications. By using GaN substrates, the lattice mismatch is fully eliminated, but the cost of these substrates is high, and large diameters are not available. GaN layers grown on GaN substrates have low defect densities compared with layers grown on other types of substrate. Therefore, for devices of the same physical dimensions, devices utilizing GaN substrates will exhibit better OFF-state and ON-state characteristics.

Growth of GaN onto a Si or a sapphire substrate offers the very attractive potential for incorporating GaN devices. However, because of the large difference in lattice constant, crystal structure, and thermal expansion coefficient, it is difficult to epitaxially grow GaN. To solve this problem, a buffer layer that minimizes the mismatch between the substrate and GaN allows growth with a quality equal to GaN. Several buffer layer types have been used to grow GaN on Si, for example, SiC [136], AlN [137], GaAs [138] and silicon nitride (Si₃N₄) [139]_. An AlN buffer layer is one of the best candidates for obtaining high-quality GaN on a Si substrate. It was found in [140] that a thicker AlN buffer layer resulted in higher crystalline quality of consequently grown GaN film.

The heterostructure consisting of undoped GaN and undoped zinc blende (cubic) (Al_0.3Ga_0.7N) is grown on the AlN buffer layer. Due to spontaneous and piezoelectric polarization, a 2DEG is created in the channel at the AlGaN/GaN interface [141]. The sheet electron density and the mobility in the channel are significantly high, ~10¹³ cm⁻² and 1500 cm²(V s)⁻¹, respectively, which result in low ON-state resistance.

Two types of contacts are formed in a lateral SBD. Metals or alloys such as palladium (Pd), platinum (Pt), indium-platinum (IrPt), palladium-silver (PdAg), and nickel/gold (Ni/Au) that have higher work functions than GaN can be used to form a Schottky barrier to the channel. The Schottky barrier is formed to the AlGaN interfacial layer of an AlGaN/GaN heterostructure. Since the channel has a high electron concentration, the depletion length is significantly shorter than in conventional diodes, although the lateral SBDs have a greater barrier height.

The ohmic contacts of a GaN power device (diodes and transistors), in most cases, represent a metal stack that is formed by thermal evaporation of different metals in multilayers following by rapid thermal annealing. The devices should be optimized to have low specific conduction resistance, and they should also be thermally stable. For N-type GaN, metal stacks such as titanium/aluminum/molybdenum/gold (Ti/Al/Mo/Au) and titanium/aluminum/platinum/gold (Ti/Al/Pt/Au) can be used to form ohmic contacts because of their excellent characteristics. A specific contact resistivity as low as 4.7×10⁻⁷ Ω cm⁻² was obtained by rapid thermal annealing of evaporated Ti/Al/Mo/Au [142]. Also, Ti/Al/Pt/Au contacts on GaN have shown a minimum contact resistivity of 8.4×10⁻⁵ Ω?cm⁻² after annealing [143].

Applying a positive bias, higher than the turn-ON voltage, V_T, to the anode, causes electrons to flow from cathode to the anode. For an applied anode to cathode voltage, V_AC, higher than 3kT/q, the current through the diode is

$I_A=A{A}^{⁎}{T}^2{e}^{-\frac{q{\varphi }_B}{kT}}\left(e^{-\frac{q{V}_{\mathit{AC}}}{kT}}-1\right)$

where A is the Schottky contact area and A⁎ is the Richardson constant (26.4 A cm⁻²K⁻²), and the potential barrier at the metal-semiconductor interface, ϕ_B, depends on the work function of the metal or alloy used for the Schottky contact.

As a negative bias is applied to the Schottky contact, a depletion layer between the Schottky contact and the 2DEG is formed. Increasing the negative voltage, the depletion layer expands and the junction capacitance decreases, resulting in a nonlinear capacitance-voltage characteristic [144]. A simple equivalent circuit model of a Schottky/2DEG diode is shown in Fig. 5.18. It consist of a voltage-dependent junction capacitance, C_j, series resistance, R_s, and a shunt capacitance, C_sh, [144].

The junction capacitance, C_j, is

$C_j\left(V_{\mathit{AC}}\right)=\frac{W\varepsilon }{\pi }Aln\left(\frac{{\left(R^2+d_{dep}^2\right)}^{1/2}+R}{{\left(R^2+d_{dep}^2\right)}^{1/2}-R}\right)$