7.1. The Configurable Processor as Controller

Configurable processor technology is often regarded as a path to creating processors with extremely high performance. The technology can also create processors with extremely small area and the Diamond 108Mini processor is an example of such a core. Figure 7.1 is a block diagram of the Diamond 108Mini processor core.

Figure 7.1. The Diamond 108Mini processor core implements a full 32-bit RISC processor while consuming only 0.41 mm² of silicon and approximately 100 μW/MHz when implemented in a 130 nm, G-type process technology.

[View full size image]

The Diamond 108Mini processor architecture contains all of the basic elements of the Xtensa ISA (instruction-set architecture). It has a 32-entry general-purpose register file, a 5-stage execution pipeline, 32-bit addressing, and a simple region-protection unit (RPU) that can be used to implement straightforward memory management. The Diamond 108Mini also incorporates the Diamond Series processor core software-debug stack, as shown on the left of Figure 7.1. This debug stack provides external access to the processor’s internal, software-visible state through a 5-pin IEEE 1149.1 JTAG TAP (test access port) interface and through a trace port that provides additional program-trace data.