1.7. I/O Bandwidth and Processor Core Clock Rate

This dichotomy is a significant point of difference between processor chips and processor cores. A processor core’s ability to support multiple simultaneous I/O transactions on several buses profoundly expands the possibilities for high-performance system architectures and topologies that would be uneconomical or impossible using packaged processor ICs for board-level system designs. Consequently, SOC designers should not feel the same pressures to pursue processors with high clock rates that PC designers use to achieve performance goals.

However, entrenched system-design habits and rules of thumb developed from the industry’s 35 years of collective, microprocessor-based, board-level system-design experience frequently prompt even experienced system designers to compare processor cores solely on clock frequency, as they might for packaged processor chips. One of the goals of this book is to convince you that SOC processor cores are not as interchangeable as once thought and that high processor clock rates are no longer as important for SOC design as they were for high-performance, board-level system designs. In fact, as discussed above, the quest for high clock rates carries severely negative consequences with respect to power dissipation, system complexity, reliability, and cost. Achieving system performance goals at lower clock rates virtually always results in superior system designs.

Note that this does not mean that high processor-core clock rates are never important. Sometimes, just there is no alternative. However, if more task concurrency at lower clock rates can achieve system-performance goals, then that design approach will almost always prove superior. Ideally, the best SOC processor core will therefore be one that both:

• delivers high performance at low clock rates,

• can achieve high clock rates if needed.