Chapter 15. The Future of SOC Design

Cost [of design] is the greatest threat to continuation of the semiconductor roadmap... Today, many design technology gaps are crises.

—ITRS:2005

We have to have major technology shifts every 10 to 12 years to keep up with silicon

—Gary Smith, Gartner Dataquest

In March, 2006, researchers at the National Nano Fab Center located at the Korea Advanced Institute of Science and Technology (KAIST) announced successful fabrication of an experimental FinFET with a gate length of 3 nm. (A finFET is a field-effect transistor with a 3D gate structure that surrounds the device’s two vertical channels on three sides.) According to the KAIST development team, achieving this milestone means that we can expect Moore’s law to be enforceable until at least the year 2026 without resorting to new and exotic non-silicon structures such as carbon nanotubes.

The expanding ability to imprint many billions of tiny FETs on a chip drives system designers to find efficient, cost-effective ways to use all those FETs in their system-on-chip (SOC) designs. According to the ITRS:2005 report, many significant challenges must be overcome if the industry doesn’t want to continue losing its ability to fully exploit the transistor bounty it enjoys under Moore’s law. This final chapter explores the identified pitfalls that await the SOC-design community and then discusses how ideas discussed in previous chapters can help avert those pitfalls.